reorganize and directory structure for spec7_blink design

943d58b1 · Peter Jansweijer · 77897d56 · 943d58b1 · 943d58b1 · 943d58b1
Commit 943d58b1 authored Jun 28, 2021 by Peter Jansweijer
16 changed files
--- a/hdl/spec7_blink/sim/.gitignore
+++ b/hdl/spec7_blink/sim/.gitignore
--- a/hdl/spec7_blink/sim/VCom_Functional.tcl
+++ b/hdl/spec7_blink/sim/VCom_Functional.tcl
 # VCom_Functional.tcl
 # compile for functional simulation

-vcom -explicit  -93 -work work ../top/spec7_blink.vhd
+vcom -explicit  -93 -work work ../../top/spec7_blink/spec7_blink.vhd
--- a/hdl/spec7_blink/sim/VSim_Functional.tcl
+++ b/hdl/spec7_blink/sim/VSim_Functional.tcl
-vsim -t ns -G/spec7_blink/Q=4 work.spec7_blink
-do wave.tcl
-do testje.tcl
-
-wave zoomfull
+vsim -t ns -G/spec7_blink/Q=4 work.spec7_blink
+do wave.tcl
+do test.tcl
+
+wave zoomfull
--- a/hdl/spec7_blink/sim/modelsim.ini
+++ b/hdl/spec7_blink/sim/modelsim.ini
--- a/hdl/spec7_blink/sim/testje.tcl
+++ b/hdl/spec7_blink/sim/testje.tcl
-force CLK_DMTD_P 0,1 4000 ps -rep 8 ns
-force CLK_DMTD_N 1,0 4000 ps -rep 8 ns
-run 4 us
-#run 200 ms
-
+force CLK_DMTD_P 0,1 4000 ps -rep 8 ns
+force CLK_DMTD_N 1,0 4000 ps -rep 8 ns
+run 4 us
+#run 200 ms
+
--- a/hdl/spec7_blink/sim/wave.tcl
+++ b/hdl/spec7_blink/sim/wave.tcl
-onerror {resume}
-quietly WaveActivateNextPane {} 0
-add wave -noupdate /spec7_blink/CLK_DMTD_P
-add wave -noupdate /spec7_blink/Q
-add wave -noupdate -expand /spec7_blink/LED
-add wave -noupdate /spec7_blink/u3_O
-TreeUpdate [SetDefaultTree]
-WaveRestoreCursors {{Cursor 1} {1114 ns} 0}
-quietly wave cursor active 1
-configure wave -namecolwidth 150
-configure wave -valuecolwidth 100
-configure wave -justifyvalue left
-configure wave -signalnamewidth 0
-configure wave -snapdistance 10
-configure wave -datasetprefix 0
-configure wave -rowmargin 4
-configure wave -childrowmargin 2
-configure wave -gridoffset 0
-configure wave -gridperiod 1
-configure wave -griddelta 40
-configure wave -timeline 0
-configure wave -timelineunits ns
-update
-WaveRestoreZoom {0 ns} {4200 ns}
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /spec7_blink/CLK_DMTD_P
+add wave -noupdate /spec7_blink/Q
+add wave -noupdate -expand /spec7_blink/LED
+add wave -noupdate /spec7_blink/u3_O
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {1114 ns} 0}
+quietly wave cursor active 1
+configure wave -namecolwidth 150
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ns
+update
+WaveRestoreZoom {0 ns} {4200 ns}
--- a/hdl/spec7_blink/syn/proj_file_list.txt
+++ b/hdl/spec7_blink/syn/proj_file_list.txt
-../top/spec7_blink.vhd
-spec7_blink.xdc
--- a/hdl/spec7_blink/syn/.gitignore
+++ b/hdl/spec7_blink/syn/.gitignore
--- a/hdl/spec7_blink/syn/README.TXT
+++ b/hdl/spec7_blink/syn/README.TXT
-Synthesis and Place&Route README.TXT 		January 25, 2018
--------------------------------------------------------
-
-Scripts:
--------
-1) do_vivado.cmd          start vivado (calling viv_do_all.tcl)
-2) do_vivado_tcl.cmd      start vivado tcl console.
-                          You may want to type:
-                          a) "start_gui" to start the vivado gui
-                          b) "source proj_properties.tcl" to find the path to the scripts and next
-                             "source $script_dir/viv_do_all.tcl"
-3) do_elf.cmd             combines the software and the empty "%DesName%.bit" file. Uses "software.elf", "%DesName%.bit"
-                          and "%DesName%_bd.bmm" and merges them into "%DesName%_elf.bit"
-4) do_vivado_prog.cmd     download the configuration ("%DesName%_elf.bit") into the Evaluation board via the USB
-                          download cable.
-Project info and sources:
--------
-proj_properties.tcl       contains the project properties (name, device etc.)
-proj_file_list.txt        a text file with all project sources. Remember that the wr-cores files are listed
-                          using "hdlmake list-files > proj_file_list.txt" in
-                          directory "../../wr-cores/syn/clbv3_ref_design"
-                          
-Scripts that are called by the scripts above or can be executed separately on the tcl command line:                          
--------
-viv_do_synt.tcl           sourced by viv_do_all.tcl, starts vivado synthesis run
-viv_do_impl.tcl           sourced by viv_do_all.tcl, starts vivado implementation run
-viv_do_program.tcl        sourced by do_vivado_prog.cmd
+Synthesis and Place&Route README.TXT 		January 25, 2018
+--------------------------------------------------------
+
+Scripts:
+--------
+1) do_vivado.cmd          start vivado (calling viv_do_all.tcl)
+2) do_vivado_tcl.cmd      start vivado tcl console.
+                          You may want to type:
+                          a) "start_gui" to start the vivado gui
+                          b) "source proj_properties.tcl" to find the path to the scripts and next
+                             "source $script_dir/viv_do_all.tcl"
+3) do_elf.cmd             combines the software and the empty "%DesName%.bit" file. Uses "software.elf", "%DesName%.bit"
+                          and "%DesName%_bd.bmm" and merges them into "%DesName%_elf.bit"
+4) do_vivado_prog.cmd     download the configuration ("%DesName%_elf.bit") into the Evaluation board via the USB
+                          download cable.
+Project info and sources:
+--------
+proj_properties.tcl       contains the project properties (name, device etc.)
+proj_file_list.txt        a text file with all project sources. Remember that the wr-cores files are listed
+                          using "hdlmake list-files > proj_file_list.txt" in
+                          directory "../../wr-cores/syn/clbv3_ref_design"
+                          
+Scripts that are called by the scripts above or can be executed separately on the tcl command line:                          
+--------
+viv_do_synt.tcl           sourced by viv_do_all.tcl, starts vivado synthesis run
+viv_do_impl.tcl           sourced by viv_do_all.tcl, starts vivado implementation run
+viv_do_program.tcl        sourced by do_vivado_prog.cmd
--- a/hdl/spec7_blink/syn/do_vivado.cmd
+++ b/hdl/spec7_blink/syn/do_vivado.cmd
-rem do_vivado.cmd  PeterJ,    19-Jan-2018.
-@prompt $$$s
-
-rem ### Cleanup old log files and stuff
-del *.log
-del *.jou
-
-rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
-rem ### in your (User) Environment Variables
-"%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_do_all.tcl
+rem do_vivado.cmd  PeterJ,    19-Jan-2018.
+@prompt $$$s
+
+rem ### Cleanup old log files and stuff
+del *.log
+del *.jou
+
+rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
+rem ### in your (User) Environment Variables
+"%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_do_all.tcl
--- a/hdl/spec7_blink/syn/do_vivado_prog.cmd
+++ b/hdl/spec7_blink/syn/do_vivado_prog.cmd
-rem prog.cmd  PeterJ,    23-Jan-2018.
-@prompt $$$s
-
-rem ### Cleanup old log files and stuff
-del vivado_prog.log
-
-rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
-rem ### in your (User) Environment Variables
-"%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_do_program.tcl -log vivado_prog.log
+rem prog.cmd  PeterJ,    23-Jan-2018.
+@prompt $$$s
+
+rem ### Cleanup old log files and stuff
+del vivado_prog.log
+
+rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
+rem ### in your (User) Environment Variables
+"%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_do_program.tcl -log vivado_prog.log
--- a/hdl/spec7_blink/syn/do_vivado_tcl.cmd
+++ b/hdl/spec7_blink/syn/do_vivado_tcl.cmd
-rem do_vivado_tcl.cmd  PeterJ,    19-Jan-2018.
-@prompt $$$s
-
-rem ### Usually one wants to start Vivado in tcl mode to inspect an existing design,
-rem ### therefore don't delete log files and setting. Else remove "rem" statements in the lines below.
-rem set DesName=clbv3_wr_ref_top
-
-rem set LogName=%DesName%-vivado
-
-rem ### Cleanup old log files and stuff (
-rem del vivado*.log
-rem del vivado*.jou
-
-rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
-rem ### in your (User) Environment Variables
-"%VIVADO%\vivado.bat" -mode tcl
+rem do_vivado_tcl.cmd  PeterJ,    19-Jan-2018.
+@prompt $$$s
+
+rem ### Usually one wants to start Vivado in tcl mode to inspect an existing design,
+rem ### therefore don't delete log files and setting. Else remove "rem" statements in the lines below.
+rem set DesName=clbv3_wr_ref_top
+
+rem set LogName=%DesName%-vivado
+
+rem ### Cleanup old log files and stuff (
+rem del vivado*.log
+rem del vivado*.jou
+
+rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
+rem ### in your (User) Environment Variables
+"%VIVADO%\vivado.bat" -mode tcl
--- a/hdl/syn/spec7_blink/proj_file_list.txt
+++ b/hdl/syn/spec7_blink/proj_file_list.txt
+../../top/spec7_blink/spec7_blink.vhd
+../../top/spec7_blink/spec7_blink.xdc
--- a/hdl/spec7_blink/syn/proj_properties.tcl
+++ b/hdl/spec7_blink/syn/proj_properties.tcl
-#
-#	projetc_properties.tcl
-#	This file contains the general project properties such as the project name and
-# the directory where Vivado is doing it's job
-#
-
-set proj_name spec7_blink
-set proj_dir work
-set script_dir [pwd]/../../../sw/scripts
-set generics ""
-             
-# SPEC7 equipped with ZYNQ XC7Z035FBG676-1 (speed grade -1 has lowest performance)
-#set device xc7z035fbg676-1
-set device xc7z030fbg676-1
+#
+#	projetc_properties.tcl
+#	This file contains the general project properties such as the project name and
+# the directory where Vivado is doing it's job
+#
+
+# ====================================================
+# DESIGN TO BUILD:
+# ====================================================
+set spec7_design spec7_blink
+
+# ====================================================
+# SELECT DEVICE TO BUILD:
+# ====================================================
+# SPEC7 equipped with ZYNQ XC7Z035FBG676-1 (speed grade -1 has lowest performance)
+set device xc7z035fbg676-1
+#set device xc7z030fbg676-1
+# ====================================================
+
+set proj_name spec7_blink
+set proj_dir work
+set script_dir [pwd]/../../../sw/scripts
+set generics ""
+             
--- a/hdl/spec7_blink/top/spec7_blink.vhd
+++ b/hdl/spec7_blink/top/spec7_blink.vhd
--- a/hdl/spec7_blink/syn/spec7_blink.xdc
+++ b/hdl/spec7_blink/syn/spec7_blink.xdc
-##### REFERENCE CLOCK #####
-# CLK_DMTD input pins (on board 124.992 MHz Xtal)
-# Note that 125.000 MHz is routed via AD9516!
-set_property PACKAGE_PIN D15 [get_ports CLK_DMTD_P]
-set_property IOSTANDARD LVDS [get_ports CLK_DMTD_P]
-set_property PACKAGE_PIN D14 [get_ports CLK_DMTD_N]
-set_property IOSTANDARD LVDS [get_ports CLK_DMTD_N]
-create_clock -period 8.000 -name CLK_DMTD_P [get_ports CLK_DMTD_P]
-
-# LED_0 to 3
-set_property IOSTANDARD LVCMOS25 [get_ports {LED[0]}]
-set_property PACKAGE_PIN AC26 [get_ports {LED[0]}]
-set_property IOSTANDARD LVCMOS25 [get_ports {LED[1]}]
-set_property PACKAGE_PIN AB26 [get_ports {LED[1]}]
-set_property IOSTANDARD LVCMOS25 [get_ports {LED[2]}]
-set_property PACKAGE_PIN AE26 [get_ports {LED[2]}]
-set_property IOSTANDARD LVCMOS25 [get_ports {LED[3]}]
-set_property PACKAGE_PIN AE25 [get_ports {LED[3]}]
-
-# Suicide & Watchdog
-# Bank 13 (HR) VCCO - 2.5 V
-set_property PACKAGE_PIN AC22 [get_ports suicide_n_o]
-set_property IOSTANDARD LVCMOS25 [get_ports suicide_n_o]
-set_property PACKAGE_PIN AC21 [get_ports wdog_n_o]
-set_property IOSTANDARD LVCMOS25 [get_ports wdog_n_o]
-
-set_property PACKAGE_PIN V19 [get_ports prsnt_m2c_l_i]
-set_property IOSTANDARD LVCMOS25 [get_ports prsnt_m2c_l_i]
+##### REFERENCE CLOCK #####
+# CLK_DMTD input pins (on board 124.992 MHz Xtal)
+# Note that 125.000 MHz is routed via AD9516!
+set_property PACKAGE_PIN D15 [get_ports CLK_DMTD_P]
+set_property IOSTANDARD LVDS [get_ports CLK_DMTD_P]
+set_property PACKAGE_PIN D14 [get_ports CLK_DMTD_N]
+set_property IOSTANDARD LVDS [get_ports CLK_DMTD_N]
+create_clock -period 8.000 -name CLK_DMTD_P [get_ports CLK_DMTD_P]
+
+# LED_0 to 3
+set_property IOSTANDARD LVCMOS25 [get_ports {LED[0]}]
+set_property PACKAGE_PIN AC26 [get_ports {LED[0]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {LED[1]}]
+set_property PACKAGE_PIN AB26 [get_ports {LED[1]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {LED[2]}]
+set_property PACKAGE_PIN AE26 [get_ports {LED[2]}]
+set_property IOSTANDARD LVCMOS25 [get_ports {LED[3]}]
+set_property PACKAGE_PIN AE25 [get_ports {LED[3]}]
+
+# Suicide & Watchdog
+# Bank 13 (HR) VCCO - 2.5 V
+set_property PACKAGE_PIN AC22 [get_ports suicide_n_o]
+set_property IOSTANDARD LVCMOS25 [get_ports suicide_n_o]
+set_property PACKAGE_PIN AC21 [get_ports wdog_n_o]
+set_property IOSTANDARD LVCMOS25 [get_ports wdog_n_o]
+
+set_property PACKAGE_PIN V19 [get_ports prsnt_m2c_l_i]
+set_property IOSTANDARD LVCMOS25 [get_ports prsnt_m2c_l_i]