Commit 77897d56 authored by Peter Jansweijer's avatar Peter Jansweijer

removed old directory structure spec7_ref_design

parent 12c440cd
/spec7.lib
/*.bram
/*.mem
/*.bak
/*.wlf
/*.vstf
/*.lnk
/*.jou
/*.log
/transcript
\ No newline at end of file
set Simulation TRUE
if {$Simulation} {
puts "Note: Simulation"
set g_simulation 1
} else {
puts "Note: Synthesis"
set g_simulation 0
}
source ../../../sw/scripts/VSim_Current_Revision.tcl
puts "elf file used for lm32 in WRPC: [set elf_file_lm32_wrpc "..\\..\\..\\sw\\precompiled\\wrps-sw_v4_2_KPx5\\wrc.elf"]"
set lm32_wrpc_instpath "lm32_wrpc_memory"
# !!! Note !!!: Don't forget to compile the software (elf file) for simulation (avoid printf etc. to speed up simulation time)
# !!! Note !!!: The double \\ are there since the DOS command below needs backslashes and a single backslash is seen as a switch in tcl
# Generate a "lm32_memory.mem" file from the "elf" file content
exec cmd.exe /c updatemem -meminfo spec7_wr_ref_top.smi -data $elf_file_lm32_wrpc -proc $lm32_wrpc_instpath -force
# Convert the "mem" to a "bram" (a format used by the White Rabbit "memory_loader_pkg.vhd")
do ../../../sw/scripts/mem2bram.tcl lm32_wrpc_memory 131072
# Now a fresh "lm32_wrpc_memory.bram" is in place for simulation and is loaded into xwb_dpram
# Note that -novopt causes No Optimization (some internal signals might get non-vivible by optimization)
# Note that "-L unisim" is needed to find the primitive "BSCANE2" thta is instantiated in "$LM32_Sources/platform/kintex7/jtag_tap.v "
#suppress warning Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value <> is not in bounds of NATURAL.
#suppress warning Warning: (vsim-8684) No drivers exist on out port <blabla>
# -novopt is now deprecated
#vsim -voptargs="+acc" -novopt
vsim -voptargs="+acc=lnprv" \
-G/spec7_wr_ref_top/g_simulation=$g_simulation \
-G/spec7_wr_ref_top/g_dpram_initf=lm32_wrpc_memory.bram \
-t ps -L unisim -lib work work.spec7_wr_ref_top
do wave.tcl
do test.tcl
view signals
#run 100 us
#stop
#wave zoom full
#
# End
#
This diff is collapsed.
<?xml version="1.0" encoding="UTF-8"?>
<MemInfoSimulation Version="1" Minor="1">
<Processor Endianness="Big" InstPath="lm32_wrpc_memory">
<AddressSpace Name="lm32_wrpc_memory_dpram" ECC="NONE" Begin="0" End="131071">
<BusBlock>
<BitLane MemType="lm32_wrpc_memory_dpram" MemType_DataWidth="32" MemType_AddressDepth="131071">
<DataWidth MSB="31" LSB="0"/>
<AddressRange Begin="0" End="32767"/>
<Parity ON="false" NumBits="0"/>
<MemFile Name="lm32_wrpc_memory.mem"/>
</BitLane>
</BusBlock>
</AddressSpace>
</Processor>
<Config>
<Option Name="Part" Val="xc7k160tfbg676-2"/>
</Config>
<DRC>
<Rule Name="RDADDRCHANGE" Val="false"/>
</DRC>
</MemInfoSimulation>
+incdir+../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src
+incdir+../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi
/.Xil
/work
/*.bak
/*.jou
/*.log
/*.prm
/*.mcs
/*.bin
/*.bit
/spec7_write_top_bd.bmm
/revisiondate_log.txt
/hdl_version.xdc
Synthesis and Place&Route README.TXT January 25, 2018
--------------------------------------------------------
Scripts:
--------
1) do_vivado.cmd start vivado (calling viv_do_all.tcl)
2) do_vivado_tcl.cmd start vivado tcl console.
You may want to type:
a) "start_gui" to start the vivado gui
b) "source proj_properties.tcl" to find the path to the scripts and next
"source $script_dir/viv_do_all.tcl"
3) do_elf.cmd combines the software and the empty "%DesName%.bit" file. Uses "software.elf", "%DesName%.bit"
and "%DesName%_bd.bmm" and merges them into "%DesName%_elf.bit"
4) do_vivado_prog.cmd download the configuration ("%DesName%_elf.bit") into the Evaluation board via the USB
download cable.
Project info and sources:
--------
proj_properties.tcl contains the project properties (name, device etc.)
proj_file_list.txt a text file with all project sources. Remember that the wr-cores files are listed
using "hdlmake list-files > proj_file_list.txt" in
directory "../../wr-cores/syn/clbv3_ref_design"
Scripts that are called by the scripts above or can be executed separately on the tcl command line:
--------
viv_do_synt.tcl sourced by viv_do_all.tcl, starts vivado synthesis run
viv_do_impl.tcl sourced by viv_do_all.tcl, starts vivado implementation run
viv_do_program.tcl sourced by do_vivado_prog.cmd
rem do_vivado.cmd PeterJ, 19-Jan-2018.
@prompt $$$s
rem ### Cleanup old log files and stuff
del *.log
del *.jou
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_do_all.tcl
rem prog.cmd PeterJ, 23-JUl-2018.
@prompt $$$s
rem ### Clean up old log files and stuff
del vivado_gen_bin_mcs.log
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_gen_bin_mcs.tcl -log vivado_gen_bin_mcs.log
rem prog.cmd PeterJ, 23-Jan-2018.
@prompt $$$s
rem ### Cleanup old log files and stuff
del vivado_prog.log
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_do_program.tcl -log vivado_prog.log
rem do_vivado_tcl.cmd PeterJ, 19-Jan-2018.
@prompt $$$s
rem ### Usually one wants to start Vivado in tcl mode to inspect an existing design,
rem ### therefore don't delete log files and setting. Else remove "rem" statements in the lines below.
rem set DesName=clbv3_wr_ref_top
rem set LogName=%DesName%-vivado
rem ### Cleanup old log files and stuff (
rem del vivado*.log
rem del vivado*.jou
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode tcl
This diff is collapsed.
#
# projetc_properties.tcl
# This file contains the general project properties such as the project name and
# the directory where Vivado is doing it's job
#
# ====================================================
# ====================================================
# SELECT DESIGN TO BUILD:
# ====================================================
# Reference Design (using fmc-dio-5chttla => https://ohwr.org/project/fmc-dio-5chttla/wikis/home)
# HPSEC Design (using Bulls-Eye connector)
set spec7_design spec7_ref_top
#set spec7_design spec7_hpsec_top
# ====================================================
# ====================================================
# SELECT DEVICE TO BUILD:
# ====================================================
# SPEC7 equipped with ZYNQ XC7Z035FBG676-1 (speed grade -1 has lowest performance)
set device xc7z035fbg676-1
#set device xc7z030fbg676-1
# ====================================================
# ====================================================
# SELECT PPS SINLGE / DIFFERENTIAL:
# ====================================================
# When Bulls-Eye connector is used as input (HPSEC).
# Differential: B01/B02 (LVDS)
# Single-ended: B11 (TTL, 5V tolerant)
set pps_in "single"
#set pps_in "diff"
# ====================================================
set proj_name spec7_wr_ref_top
set proj_dir work
set script_dir [pwd]/../../../sw/scripts
set lm32_wrpc_initf [pwd]/../../../sw/precompiled/wrps-sw-v5_spec7/wrc.bram
set lm32_wrpc_elf [pwd]/../../../sw/precompiled/wrps-sw-v5_spec7/wrc.elf
set lm32_wrpc_instpath "lm32_wrpc_memory"
# update revision except when argument "no_update_revison" is passed (as for example by viv_do_programm.tcl)
if {$argc == 0 || $argv != "no_update_revision"} {
source $script_dir/revisiondate.tcl
set generics "g_design=$spec7_design \
g_use_pps_in=$pps_in \
g_dpram_initf=$lm32_wrpc_initf"
}
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