Commit 672cae07 authored by Peter Jansweijer's avatar Peter Jansweijer

Add spec7 documentation

parent c334f75a
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@misc{ Nobody06,
author = "Nobody Jr",
title = "My Article",
year = "2006" }
@misc{ PCIexpressx16Graphics150WATX,
author = "PCI-SIG",
title = "PCI Express x16 Graphics 150W-ATX Specfication Revision 1.0",
year = "25-Oktober-2004" }
@misc{ SPEC,
author = "OHWR.org",
title = "Simple PCIe FMC carrier (SPEC)",
year = "December 19, 2019",
howpublished = "\url {https://ohwr.org/project/spec/wikis/home}"}
}
@misc{ SPEC7,
author = "OHWR.org",
title = "Simple PCIe FMC carrier 7 (SPEC7)",
year = "April 7, 2020",
howpublished = "\url {https://ohwr.org/project/spec7/wikis/home}"}
}
@misc{ fmc-dio-5chttla,
author = "OHWR.org",
title = "fmc-dio-5chttla FMC 5-channel Digital I/O module",
year = "Januari 31, 2020",
howpublished = "\url {https://ohwr.org/project/fmc-dio-5chttla/wikis/home}"}
}
@misc{ wrpc,
author = "OHWR.org",
title = "White Rabbit PTP Core (WRPC)",
year = "July 20, 2020",
howpublished = "\url {https://ohwr.org/project/wr-cores/wikis/wrpc-core}"}
}
@misc{ HPSEC,
author = "OHWR.org",
title = "High Precision Slaved External Clock (HPSEC)",
year = "April 28, 2020",
howpublished = "\url {https://ohwr.org/project/hpsec/wikis/home}"}
}
@misc{ VITA-57,
author = "VITA Standards Organization",
title = "FPGA Mezzanine Card (FMC) Standard VITA 57",
howpublished = "\url {https://www.vita.com/}"}
}
@misc{SFF-8472,
author = "SFF-Commite",
title = "SFF-8472 Diagnostic Monitoring Interface for Optical Transceivers Rev 12.2",
year = "21-Nov-2014",
howpublished = "\url{ftp://ftp.seagate.com/sff/SFF-8472.PDF}"
}
@misc{SFF-8431,
author = "SFF-Commite",
title = "SFF-8431 SFP+ 10 Gb/s and low speed Electrial interface Rev 4.1",
year = "06-Juy-2009",
howpublished = "\url {ftp://ftp.seagate.com/sff/SFF-8431.PDF}"
}
@misc{DS191,
author = "Xilinx",
title = "DS191: Zynq-7000 SoC (Z-7030, Z-7035, Z-7045, and Z-7100): DC and AC Switching Characteristics",
year = "02-Juy-2018",
howpublished = "\url {https://www.xilinx.com/support/documentation/data_sheets/ds191-XC7Z030-XC7Z045-data-sheet.pdf}"
}
@misc{PCI-SIG,
author = "PCI-SIG",
howpublished = "\url {https://pcisig.com/}"
}
@misc{White_Rabbit_calibration_procedure,
author = "Grzegorz Daniluk",
title = "White Rabbit calibration procedure",
year = "2015"}
@misc{Hittite_HMC865LC3,
author = "Hittite Microwave",
title = "MC865LC3 32 Gbps LIMITING AMPLIFIER",
year = "2015"}
@misc{Vishay_CH,
author = "Vishay",
title = "50 GHz Thin Film Microwave Resistors CH Vishay Document Number: 53014",
year = "29-Nov-2010"}
@misc{Micron_Qspi_flash,
author = "Micron Technology, Inc.",
title = "MT25QL128ABA8ESF catalog",
year = "2020",
howpublished = "\url{https://www.micron.com/products/nor-flash/serial-nor-flash/part-catalog/mt25ql128aba8esf-0sit}"
}
@misc{Xilinx_AR16996,
author = "Xilinx",
title = "Answer Record 16996",
year = "27-april-2016",
howpublished = "\url{https://www.xilinx.com/support/answers/16996.html}"
}
@misc{Xilinx_AR55572,
author = "Xilinx",
title = "Answer Record 55572",
year = "18-may-2018",
howpublished = "\url{https://www.xilinx.com/support/answers/55572.html}"
}
@misc{DS1856E-M50+,
author = "Maxim intergrated",
title = "DS1856M Dual Temperature-Controlled Resistors with Calibration Monitors and Password Protection 19-6395;rev 1",
year = "2013"}
@misc{White_Rabbit_absolute_calibration,
author = "P.P.M Jansweijer {,} H.Z. Peek{,}T.J. Pinkert{,}G.C Visser",
title = "White Rabbit Absolute Calibration Procedure Version 1.0",
year = "4-April-2016"
}
@misc{CDCLVD2102,
author = "Texas Instruments",
title = "Dual1:2LowAdditiveJitterLVDSBuffer",
year = "may-2010",
howpublished = "\url {https://www.ti.com/lit/ds/symlink/cdclvd2102.pdf?ts=1590402921717}"
}
\addcontentsline{toc}{section}{References}
\bibliographystyle{unsrt}
\begin{thebibliography}{9}
\bibitem{SFF-8472}
SFF-8472 Diagnostic Monitoring Interface for Optical Transceivers.\\
%\href{http://en.wikibooks.org/wiki/LaTeX}{http://en.wikibooks.org/wiki/LaTeX}
\href{Seagete SFF FTP}{ftp://ftp.seagate.com/sff/SFF-8472.PDF}
\bibitem{SFF-8431}
SFF-8431 SFP+ 10 Gb/s and low speed Electrial interface. Rev 4.1\\
\href{Seagete SFF FTP}{ftp://ftp.seagate.com/sff/SFF-8431.PDF}
\bibitem{White Rabbit calibration procedure}
Grzegorz Daniluk, White Rabbit calibration procedure, November 9, 2015.\\
\href{http://www.ohwr.org/documents/213}{http://www.ohwr.org/documents/213}
\bibitem{Hittite_HMC865LC3}
HMC865LC3 32 Gbps LIMITING AMPLIFIER, v01.0614\\
\bibitem{Vishay_CH}
50 GHz Thin Film Microwave Resistors CH Vishay, Document Number: 53014
46 Revision: 29-Nov-10\\
\bibitem{DS1856E-M50+}
DS1856M Dual,Temperature-Controlled Resistors with Calibration Monitors and Password Protection
19-6395; Rev 1\\
\href{Datasheet}{https://www.maximintegrated.com/en/products/comms/optical-communications/DS1856M.html}
\end{thebibliography}
\newpage
\section{SPEC7 Firmware and Software}
\subsection{SPEC7 reference design and SPEC7 WRITE design}
There are two designs, a SPEC7 reference design and a SPEC7 WRITE design that have many things in common.
Figure~\ref{fig:SPEC7_PCIe_Block_diagram} is a block diagram which that focuses on the PCIe connections common to both.
\begin{figure}[H]
\centering
\includegraphics[width=0.8\textwidth]{./pictures/Blockschematics/SPEC7_BlockDiagram_PCIe.pdf}
\caption{PCIe block diagram.} %{see footnote\protect\footnotemark}
\label{fig:SPEC7_PCIe_Block_diagram}
\end{figure}
\noindent
As explained in the introduction (see: ~\ref{sec:Overview of the SPEC7.}) the Zynq FPGA contains a Processing System (PS) and a Programmable Logic (PL) section.
The PCIe endpoint, located in PL, has two BARs.
BAR0 (64 KB) is connected to a DMA engine that is looped back via its AXI stream interface.
It is implemented for test purposes.
BAR1 (1 MB) is divided in two 512 KB sections.
The lower 512 KB of the address space is connected to A WR PTP Core (WRPC~\cite{wrpc}).
This connection enables direct access to the DPRAM (that contains the LM32 executable), the virtual UART and other registers that are mapped on the WRPC wishbone bus (for details, please refer to ~\cite{wrpc}).
The upper 512 KB of the address space is connected to a basic ARM Processing System that resides in the PS section of the FPGA.
A basic processing system is a minimum requirement for FPGA configuration from QSPI (see also Appendix~\ref{app:QSPI boot Tutorial}).
\subsubsection{SPEC7 reference design}
The SPEC7 reference design operates the SPEC7 like users were used to with the SPEC~\cite{SPEC} reference design.
A Digital IO FMC~\cite{fmc-dio-5chttla} can be plugged onto the SPEC7 so 1PPS/10MHz in and 1PPS out signals are available.
Table ~\ref{tab:DIO_RefDesign_LEMO_connections} shows which reference design signal is assigned to what DIO LEMO connector.
\begin{table}[H]
\begin{center}
\begin{tabular}{|c|c|c|}
\hline \textbf{DIO LEMO nr.} & Reference design signal & direction\\
\hline 1 & PPS & out\\
\hline 2 & n.a. & n.a. \\
\hline 3 & abscal\_txts & out\\
\hline 4 & PPS & in \\
\hline 5 & 10 MHz & in \\
\hline
\end{tabular}
\caption{DIO LEMO connector reference design signal assignment. }
\label{tab:DIO_RefDesign_LEMO_connections}
\end{center}
\end{table}
\subsubsection{SPEC7 WRITE design}
The SPEC7 reference design operates the SPEC7 without DIO card.
The design aims for lower phase noise than the "standard" SPEC7 reference design.
Differential timing signals (PPS and 10MHz) are routed to the Bulls Eye connector J4.
The PPS out signal is re-clocked to remove FPGA switching phase noise.
In Grand Master mode the design accepts 10MHz and 1PPS input via connector J4.
Bulls Eye connector J4 provides a well defined high bandwidth connection to the outside world.
It should be used when the SPEC7 is deployed in demanding applications where users aim for the highest quality signals, for example when SPEC7 is used in combination with a high precision external oscillator (like the HPSEC design ~\cite{HPSEC}).
\subsection{HDL synthesis}
Before running the synthesis process you have to make sure your environment is set up correctly.
You will need Vivado 2019.2 from your Xilinx vendor.
\subsubsection{Downloading the sources}
The SPEC7 sources are part of the wr-cores repository.
Usualy the \emph{hdlmake} tool is used to gather the sources needed to build the firmware.
Unfortunately \emph{hdlmake} does not support \emph{.tcl}, "Block Memory Mapping" (\emph{.bmm}) or Memory Mapping Information (\emph{.mmi}) files.
Tcl scripting is needed for automatic ARM processing system block diagram generation.
The \emph{.bmm} and \emph{.mmi} files are needed to merge software into the FPGA configuration bitfile without the need for re-synthesis of the firmware.
A top SPEC7 repository facilitates the above.
The wr-cores repository, containing the sources, is its submodule:
%git clone https://gitlab.nikhef.nl/peterj/spec7.git
\begin{lstlisting}[frame=single]
git clone https://ohwr.org/project/spec7.git
cd spec7
git checkout proposed_master
git submodule init
git submodule update
cd hdl/wr-cores
git submodule init
git submodule update
\end{lstlisting}
Synthesis is started in the corresponding project \emph{syn} directory.
It is important to source the script from the project/syn directory because it contains the project specific files:
\begin{itemize}
\item \emph{proj\_properties.tcl}: project specific settings (for example target FPGA)
\item \emph{proj\_file\_list.txt}: list of files needed by the project (i.e. the output of \emph{hdlmake list-files} plus a few files that are not supported by \emph{hdlmake}.)
\end{itemize}
\subsubsection{Building the SPEC7 reference design}
To build the firmware for the reference design:
\begin{lstlisting}[frame=single]
%cd hdl\spec7_ref_design\syn
\end{lstlisting}
Start Vivado and source the tcl script.
\begin{lstlisting}[frame=single]
vivado
%source ..\..\..\sw\scripts\viv_do_all.tcl
\end{lstlisting}
Synthesis en bitfile generation may take quite some time.
If the process is successful then you will end up with:
\begin{itemize}
\item \emph{spec7\_ref\_design\_z035\_YYDDMM\_HHMM.bit}
\item \emph{spec7\_ref\_design\_z035\_YYDDMM\_HHMM.mmi}
\item \emph{spec7\_ref\_design\_z035\_YYDDMM\_HHMM.log}
\end{itemize}
in the spec7\_ref\_design directory, where YYMMDD\_HHMM is the build date and time.
The \emph{.log} file contains the SHA codes from the repositories and sub-modules that were used for the build.
\subsubsection{Building the SPEC7 WRITE design}
The SPEC7 reference design operates the SPEC7 without DIO card.
Timing signals are routed to the Bulls Eye connector J4.
In Grand Master mode the design accepts 10MHz and 1PPS input via this connector.
The design also generates 10MHz and 1PPS out via this connector.
\begin{lstlisting}[frame=single]
%cd hdl\spec7_write_design\syn
\end{lstlisting}
Start Vivado and source the tcl script.
\begin{lstlisting}[frame=single]
vivado
%source ..\..\..\sw\scripts\viv_do_all.tcl
\end{lstlisting}
If the process is successful then you will end up with:
\begin{itemize}
\item \emph{spec7\_write\_design\_z035\_YYDDMM\_HHMM.bit}
\item \emph{spec7\_write\_design\_z035\_YYDDMM\_HHMM.mmi}
\item \emph{spec7\_write\_design\_z035\_YYDDMM\_HHMM.log}
\end{itemize}
in the spec7\_write\_design directory, where YYMMDD\_HHMM is the build date and time.
The \emph{.log} file contains the SHA codes from the repositories and sub-modules that were used for the build.
\subsubsection{Merging .bit and .elf files}
The Vivado installation is contains an \emph{updatemem} command.
An FPGA configuration \emph{.bit} file that contains a memory space (like the LM32 memory embedded in wr-cores) can be updated with new memory content (i.e. executable software) using \emph{updatemem}.
In order to be able to do this, \emph{updatemem} needs information to locates all BRAM blocks that build up the memory space.
This information is provided by the generated Memory Mapping Information \emph{.mmi} file.
One can merge new compiled software in Executable Loader Format \emph{.elf} with the \emph{.bit} without the need for time consuming re-synthesis.
A script is available to merge an \emph{.elf} file with a \emph{.bit} and \emph{.mmi} file using \emph{updatemem}.
First get into the project directory; the location of the new build \emph{.bit} and \emph{.mmi}.
\begin{lstlisting}[frame=single]
cd ..
\end{lstlisting}
next
\begin{lstlisting}[frame=single]
..\..\sw\scripts\do_vivado_mmi_elf.cmd <bitfile>.bit <elffile>.elf
\end{lstlisting}
which will generate a \emph{bitfile\_elf.bit}.
\newpage
\ No newline at end of file
\section{Introduction}
The SPEC7~\cite{SPEC7} is the successor of the SPEC~\cite{SPEC}.
SPEC7 stands for Simple PCIe FMC Carrier, based on Xilinx 7-series FPGAs.
More specifically the board utilizes a Xilinx Zynq-7000 FPGA (Z030 or Z035) with Dual-Core ARM processor integrated.
The FMC PCIe Carrier is an FMC carrier that can hold one FMC card and an SFP connector.
As was the case with the SPEC, the SPEC7 is specifically designed to enable White Rabbit deployment.
To facilitate this, the board contains Voltage Controlled Crystal Oscillators (VCXOs) and Digital to Analog Converters (DACs).
The design was optimized for low phase noise.
For demanding users (like metrology institutes) the SPEC7 can be equipped with an external oscillator in order to further decrease phase noise.
It is left to the demanding user how much money is spend on a better external oscillator such that they can make their own trade-offs.
An example design that uses a high precision external oscillator is the High Precision External Slave Clock (HPSEC~\cite{HPSEC}) design which incorporates a SPEC7.
\newpage
\subsection{Overview of the SPEC7}
\label{sec:Overview of the SPEC7.}
%\footnote{White Rabbit Absolute Calibration Procedure
\begin{figure}[H]
\centering
\includegraphics[width=0.8\textwidth]{./pictures/Blockschematics/SPEC7_BlockDiagram.pdf}
\caption{SPEC7 block diagram.} %{see footnote\protect\footnotemark}
\label{fig:SPEC7_Block_diagram}
\end{figure}
\noindent
Xilinx Zynq-7000 devices contain a Processing System (PS) and Programmable Logic (PL). Both PS, PL and their respective connections are shown in the SPEC7 block diagram (figure ~\ref{fig:SPEC7_Block_diagram}).
\subsection{White Rabbit Clocking}
\label{sec:White Rabbit Clocking}
The SPEC7 contains an LTC6950 PLL which is used to distribute and generate the White Rabbit 125 MHz reference clock.
The LTC6960 needs to be configured via SPI by software.
Two LEDs show the status of the LTC6950.
LED D74 is lit red when there is no reference clock found.
LED D72 is lit green when the PLL is locked.
Without configuration and without reference clock LED D74 is on (default after power up with no FPGA image).
Mode bits WR\_MODE(1:0) determine how clocks are routed.
Table ~\ref{tab:WR_MODE} and the paragraphs below explain how clocks are routed according to the WR\_MODE(1:0) status.
\begin{table}[H]
\begin{center}
\begin{tabular}{|c|c|}
\hline \textbf{WR\_MODE(1:0)} & \\
\hline 00 & Reserved \\
\hline 01 & Free-running Master \\
\hline 10 & Slave \\
\hline 11 & Grand Master \\
\hline
\end{tabular}
\caption{WR\_MODE(1:0) (FPGA pins C12, B12) select White Rabbit Clocking options. }
\label{tab:WR_MODE}
\end{center}
\end{table}
The following sections describe the White Rabbit modes that can be selected.
\subsubsection{Mode Slave}
Traditionally the SPEC7 is used as a WR-node which means that it operates in mode slave.
Figure ~\ref{fig:Mode Slave} shows how the DAC is selected to tune the VCXO that feeds the LTC6950.
In this mode the PLL is switched of and the LTC6950 is only used as a clock distribution system.
In this mode LEDs D72 (Lock) and D74 (NoRef) are both off.
\begin{figure}[H]
\centering
\includegraphics[width=0.6\textwidth]{./pictures/Blockschematics/SPEC7_LT6950_Mode_Slave.pdf}
\caption{Clock selection for Mode Slave.} %{see footnote\protect\footnotemark}
\label{fig:Mode Slave}
\end{figure}
The configuration shown in figure~\ref{fig:Mode Slave} also allows for the traditional WR \emph{mode master} and \emph{mode gm} where the 125 MHz VCXO is taken as a reference clock or the 125 MHz VCXO is phase locked and aligned to an external 10MHz source, respectively.
\subsubsection{Mode Master}
The SPEC7 can be operated as a free running master.
In this mode an on board TCXO 10MHz oscillator is switched on (see figure ~\ref{fig:Mode Master}).
This clock is fed to the PLL of the LTC6950.
The PLL Charge Pump signal is now tuning the VCXO.
The PLL divides by 2 and multiplies by 25 to generate and distribute the 125MHz reference clock.
In this mode LEDs D72 (Lock) is on and D74 (NoRef) is off.
\begin{figure}[H]
\centering
\includegraphics[width=0.6\textwidth]{./pictures/Blockschematics/SPEC7_LT6950_Mode_Master.pdf}
\caption{Clock selection for Mode Master.} %{see footnote\protect\footnotemark}
\label{fig:Mode Master}
\end{figure}
\subsubsection{Mode Grand Master}
The SPEC7 can be operated as Grand Master.
In this mode and external 10MHz (sine-wave) reference (and 1PPS) is applied (see figure ~\ref{fig:Mode Grand Master}).
This clock is fed to the PLL of the LTC6950.
The PLL Charge Pump signal is now tuning the VCXO.
The PLL divides by 2 and multiplies by 25 to generate and distribute the 125MHz reference clock.
When a reference clock is present then LED D74 (NoRef) should be off.
When a reference clock has the proper frequency and the PLL can lock then LED D72 (Lock).
\begin{figure}[H]
\centering
\includegraphics[width=0.6\textwidth]{./pictures/Blockschematics/SPEC7_LT6950_Mode_GrandMaster.pdf}
\caption{Clock selection for Mode Grand Master.} %{see footnote\protect\footnotemark}
\label{fig:Mode Grand Master}
\end{figure}
\subsection{JTAG Header J9}
The JTAG chain on the SPEC7 is routed through the Zynq FPGA and the FMC.
By default the JTAG chain is connected to the PL of the Zynq FPGA (see table ~\ref{tab:PL_JTAG_pins}). This enables a JTAG connection between the logic in the FPGA and devices JTAG present on the FMC.
\begin{table}[H]
\begin{center}
\begin{tabular}{|c|c|c|}
\hline \textbf{PL User JTAG} & Direction & FPGA Pin\\
\hline TCK & out & K12 \\
\hline TMS & out & E13 \\
\hline TDI & out & C13 \\
\hline TDO & in & A13 \\
\hline
\end{tabular}
\caption{PL FPGA pins that connect to the SPEC7 JTAG chain. }
\label{tab:PL_JTAG_pins}
\end{center}
\end{table}
The presence of an FMC is detected by the PRSNT\_M2C signal.
When an FMC card is absent then the FMC connector TDI and TDO are automatically connected by an electronic switch.
A Xilinx Download Cable can be plugged in connector J9 to configure the FPGA.
Once a Download Cable is plugged into J9 the JTAG chain it is automatically connected.
Presence of a Download Cable is detected by pin 1 of J9 (see figure ~\ref{fig:JTAG multiplexer}).
Most\footnote{Download cables that do \textbf{not} have pin 1 grounded are Xilinx Platform Cable USB II and Digilent JTAG-HS2. This causes an error \enquote{no device detected on target} in Vivado.} programming cables have pin 1 grounded.
\begin{figure}[H]
\centering
\includegraphics[width=0.6\textwidth]{./pictures/Blockschematics/JTAG_multiplexer.pdf}
\caption{J9: Presence of an FMC and a Xilinx Download Cable is automatically detected.} %{see footnote\protect\footnotemark}
\label{fig:JTAG multiplexer}
\end{figure}
%\footnotetext{taken from White Rabbit Absolute Calibration Procedure}
\nomenclature{SFP}{Small Form-factor Pluggable.}
\nomenclature{QPDIO}{Quadrant Photodiode.}
\newpage
\ No newline at end of file
\section{Known bugs \& Errors}
\begin{enumerate}
\item The EN pin of U28 is '1' which enables OUT0/1 but disables OUT2/3.
In contrast to what is stated in the schematics, Table 1 of datasheet CDCLVD2102 see \cite{CDCLVD2102} shows that both outputs are enabled when EN is "open"
\label{sec:Mini_USB_when_operating_stand_alone}
\item Although ESD protected, SiliconLabs CP2105 (U54, dual UART) seems to be a weak spot.
When the SPEC7 is operated stand alone then the chassis of a PC that is connected to the mini USB connector (X2) must be at SPEC7 ground potential.
\
\end{enumerate}
\ No newline at end of file
\section{Measured Data}
The following chapter presents measured results.
All measurements are done with the default firmware for the SPEC7.
\subsection{Phase Noise}
\label{subsec:Phase Noise}
%\label{app:125 MHz reference generato}
The following setup is used to measure the phase noise of the SPEC7 card as shown in figure~\ref{fig:Phase noise measurement setup.}.
For more information about the custom 125 MHz reference generator see appendix ~\ref{app:125 MHz reference generator}.
Phase noise is measured at point C using a Rohde\&Schwarz phase noise analyzer (FSWP). Point C is the Bulls Eye connector.
\begin{figure}[H]
\centering
\includegraphics[width=0.8\textwidth]{./pictures/Blockschematics/PhaseNoiseSetupMasterSlaveSPEC7.pdf}
\caption{Phase noise measurement setup} %{see footnote\protect\footnotemark}
\label{fig:Phase noise measurement setup.}
\end{figure}
\begin{figure}[H]
\centering
\includegraphics[width=0.8\textwidth]{./pictures/Meas/SPEC7V2-10MhzPhaseNoise_updated.pdf}
\caption{Phase noise 10 MHz output (J4 A03/A04).} %{see footnote\protect\footnotemark}
\label{fig:Phase noise 10 Mhz output.}
\end{figure}
A small bump around 13 KHz can be seen in the phase noise plot of figure ~\ref{fig:Phase noise 10 Mhz output.}.
The cause of the phase noise around 13KHz can also be seen in the spectrum and spectrogram of figure ~\ref{fig:10MHz_spectrogram}.
The noise sources are the 2V5 and 1V8 Switched Mode Power Supplies (N6, N5: Intel EN6347QA).
Keep in mind that this noise has no major effect since it only reaches -135 dBc/Hz over a limited bandwidth.
\begin{figure}[H]
\centering
\includegraphics[width=0.8\textwidth]{./pictures/Meas/10MHz spectrum_with_bumps.PNG}
\caption{Spectrum of the 10 MHz with some noise at 13 KHz distance from the carrier.} %{see footnote\protect\footnotemark}
\label{fig:10MHz_spectrogram}
\end{figure}
The phase noise between $10^5$ and $10^6$ in figure~\ref{fig:Phase noise 10 Mhz output.} is caused by the 500 MHz \mbox{MMCME2\_ADV} PLL in the FPGA that is used in the spec7\_ref\_design to create a White Rabbit phase aligned 10MHz.
\begin{figure}[H]
\centering
\includegraphics[width=0.8\textwidth]{./pictures/Meas//SPEC7V2-125MhzPhaseNoise.pdf}
\caption{Phase noise 125 MHz output (J4 A05/A06).} %{see footnote\protect\footnotemark}
\label{fig:Phase noise 125 Mhz output.}
\end{figure}
\subsection{Spurs}
The figures below show the frequency spectrum for the 10 MHz and 125 MHz outputs.
\begin{figure}[H]
\centering
\includegraphics[width=0.8\textwidth]{./pictures/Meas/10MHZ-SPECTRUM.png}
\caption{Spectrum 10 MHz Output.} %{see footnote\protect\footnotemark}
\label{fig:Spectrum 10 MHz Output.}
\end{figure}
\begin{figure}[H]
\centering
\includegraphics[width=0.8\textwidth]{./pictures/Meas/125MHZ-SPECTRUM.png}
\caption{Spectrum 125 MHz Output.} %{see footnote\protect\footnotemark}
\label{fig:Spectrum 125 MHz Output.}
\end{figure}
\subsection{Time Domain}
\textbf{\textcolor{red}{allen dev plot}}
\subsection{Restart Error}
\begin{figure}[H]
\centering
\includegraphics[width=0.8\textwidth]{./pictures/Blockschematics/TimeInterValSetup.pdf}
\caption{PPS Restart Error measurement setup.} %{see footnote\protect\footnotemark}
\label{fig:PPS Restart Error measurement setupr.}
\end{figure}
\begin{figure}[H]
\centering
\includegraphics[width=0.8\textwidth]{./pictures/Meas/RestartErrorSpec7.png}
\caption{PPS Restart Error.} %{see footnote\protect\footnotemark}
\label{fig:PPS Restart Error.}
\end{figure}
\subsection{PPS Pulse to Pulse Jitter}
\subsection{Boot time on board flash memory}
The SPEC7 is capable of booting from a dual Quad-SPI flash memory setup. Two Micron \cite{Micron_Qspi_flash} chips (2x MT25QL256ABA8E12-1SIT in a Dual QUAD SPI configuration) are present on the card and connected to the Zynq Processor System. The SPEC7 can reach boot times down to 735 milliseconds. This can be seen in figure~\ref{fig:QSPI_uncompressed}, where the 12V supply voltage (red) is depicted along an user application (green), the yellow line is a probed qspi clock signal to display when the memory is being accessed.
\begin{figure}[H]
\centering
\includegraphics[width=0.8\textwidth]{./pictures/Meas/QSPI_x8_NO_COMPRESSION.png}
\caption{QPSI boot time of an uncompressed bitfile. Notice how the QSPI clock signal (yellow) is divided into two "stages". The first is the Bootloader being loaded into the Zynq, the second stage is the bitstream being loaded into the programmable logic.}
\label{fig:QSPI_uncompressed}
\end{figure}
These 735 milliseconds are currently a worst case scenario. Boot times can be greatly reduced by enabling bitsream compression\cite{Xilinx_AR16996}, along with other optimizations\cite{Xilinx_AR55572}. An example of booting a compressed bitstream is depicted in figure~\ref{fig:QSPI_compressed} where the boot time is reduced to 265 milliseconds.
\begin{figure}[H]
\centering
\includegraphics[width=0.8\textwidth]{./pictures/Meas/QSPI_x8_COMPRESSION.png}
\caption{QPSI boot time of an compressed bitfile.}
\label{fig:QSPI_compressed}
\end{figure}
\newpage
\section{PCIe interface}
The PCIe interface is only tested on the physical level for transaction rates 2.5GT/sec and 5GT/sec.
The device under test is a Zynq Z035 device.
The 2.5GT/sec eye diagram is shown in figure ~\ref{fig:PCIe 2.5Gbit/sec eyediagram.}.
The 5GT/sec eye diagram is shown in figure ~\ref{fig:PCIe 5Gbit/sec eyediagram.}.
\begin{figure}[H]
\centering
\includegraphics[width=0.8\textwidth]{./pictures/Meas/2Gbit5Eye_7035.png}
\caption{PCIe 2.5GT/sec eye diagram.} %{see footnote\protect\footnotemark}
\label{fig:PCIe 2.5Gbit/sec eyediagram.}
\end{figure}
\begin{figure}[H]
\centering
\includegraphics[width=0.8\textwidth]{./pictures/Meas/5GbitEye_7035.png}
\caption{PCIe 5GT/sec eye diagram.} %{see footnote\protect\footnotemark}
\label{fig:PCIe 5Gbit/sec eyediagram.}
\end{figure}
More information about the test setup can be found in appendix ~\ref{app:Physical layer PCI-E test set up}
Figure ~\ref{fig:lscpi_screen} shows the SPEC7 being recognized by the oprerating system (i.e. \enquote{lspci}).
\begin{figure}[H]
\centering
\includegraphics[width=0.8\textwidth]{./pictures/Other/lspci_screen.jpg}
\caption{Example result of lspci: SPEC7 is recognized} %{see footnote\protect\footnotemark}
\label{fig:lscpi_screen}
\end{figure}
\nomenclature{RBW}{Receiver Bandwidth.}
\nomenclature{OCXO}{Oven Controlled Crystal Oscillator}
\newpage
\ No newline at end of file
This diff is collapsed.
\section{Optional Heatsink, Fans and RF-Shielding}
\label{sec:Optional Heatsink And Fans}
The SPEC7 may be optionally be equipped with a heatsink, fans or an Clip-On EMI Shielding Can.
Table ~\ref{tab:Heatsink_Fans} shows manufacturers and part numbers that will fit the SPEC7 design.
\subsection{Heatsink}
Depending on the application the Zynq FPGA on the SPEC7 may need a heatsink and/or a fan.
The type of heatsink that will fit on the SPEC7 is a "Square Skived Fin 5ommx50mm, Height=14mm, mounted on PCB", Manufacturer AAVID, Part Number 342943 (see figure~\ref{fig:AAVID_342943}).
Note that the total height of the heatsink (14 mm) plus Zynq (2.44 mm) is now 16.44 mm while the PCIe specification restricts the total height to 14.47mm.
Unfortunately this is inevitable since a market survey showed that there were no other suitable cooling profiles found on the market.
If a cooling profile is necessary and the total height poses a problem then a work around is to mill-off 2 mm from the profile.
\begin{figure}[H]
\centering
\includegraphics[width=0.4\textwidth]{./pictures/Other/AAVID_342943.jpg}
\caption{Heatsink AAVID 342943} %{see footnote\protect\footnotemark}
\label{fig:AAVID_342943}
\end{figure}
\subsection{Fans}
A 5V DC fan for the FPGA can be connected to connector X3. The FPGA fan can be controlled via FPGA pin AD26.
For FMC cards that need cooling, a 5V DC fan can be mounted in at the back of the SPEC7 at the location of the hole in the PCB.
Both a fan from Sunon Fans, part number "UB5U3-700" (see figure~\ref{fig:Sunon_Fan_UB5U3-700}) or "Delta Electronics", part number "KDB0305HA3-00C1J" will fit.
The fan can be connected to X1 and can be controlled via FPGA pin AD25.
\begin{figure}[H]
\centering
\includegraphics[width=0.4\textwidth]{./pictures/Other/SunonFan.jpg}
\caption{Sunon Fan UB5U3-700} %{see footnote\protect\footnotemark}
\label{fig:Sunon_Fan_UB5U3-700}
\end{figure}
The counterpart for X1 and X3 is a Molex connector, part number 0022013027.
\subsection{RF-Shielding Can}
The SPEC7 is equipped with RF Shield Clips such that a Clip-On EMI Shield can be placed over the clocking circuits to minimize phase noise degradation due to external EMI noise sources.
Placing of this EMI shield is optional.
All measurements that are reported in this document are performed without a shield.
%\begin{table}[hbt!]
\begin{table}[H]
\begin{center}
\begin{tabular}{|c|c|c|}
\hline & \textbf{Manufacturer} & \textbf{Part Number} \\
\hline \textbf{Heatsink} & AAVID & 342943 \\
\hline \textbf{Fan 5V DC} & Sunon Fans & UB5U3-700 \\
\hline \textbf{Fan 5V DC} & Delta Electronics & KDB0305HA3-00C1J \\
\hline \textbf{Counterpart X1, X3} & Molex & 0022013027 \\
\hline \textbf{\makecell{ Clip-On EMI Shielding Can \\ 35x50mm, Height=10mm}} & Holland Shielding & 1500-35-50-10-TS0.20 \\
\hline
\end{tabular}
\caption{Optional Heatsink, Fans, Connecto, RF-Shielding Can}
\label{tab:Heatsink_Fans}
\end{center}
\end{table}
\newpage
\ No newline at end of file
\section{Overview of the system.}
\label{sec:Oe}
\subsection{Block schematic}
\label{subsec:Block schematic}
In the following figure ~\ref{fig:Block_Schematic_SFP_Cal_Module} is the block schematic shown. One of the critical block is the "RF probe"
for the complete schematic see ~\ref{app:Schematic}
\nomenclature{TVS}{Transient-voltage-suppression diode.}
This diff is collapsed.
\section{Power \& Maximum Ratings}
\label{sec:Power and Maximum ratings}
\subsection{Power Ratings}
%\begin{table}[hbt!]
\begin{table}[H]
\begin{center}
\begin{tabular}{|c|c|c|c|c|}
\hline \textbf{Description} & \textbf{Value} & \textbf{Unit} & \textbf{Tolerance} & \textbf{Note} \\
\hline \textbf{Input voltage Range } & 12 & V & +/-5\% & \\
\hline \textbf{Absolute Maximum input voltage} & 12.65 & V & & Note 1\\
\hline \textbf{Nominal current draw} & 1 & A & & Note 2\\
\hline
\end{tabular}
\caption{ATX power connector}
\label{fig:ATX power connector}
\end{center}
\end{table}
\begin{enumerate}
\item \textbf{\textcolor{red}{Stress above the stated voltage will damage the SPEC7 and/or a possible connected FMC mezzanine.}}
\item \textbf{\textcolor{black}{The stated current is only when a a White rabbit core is loaded, the actual current consumption heavily depends on your end application }}
\end{enumerate}
\subsection{Power Up Sequence}
The SPEC7 can either be powered when plugged into a PCIe slot or it can be used stand alone by using an external 12V power supply.
When plugged into a PCI slot then the main power of the SPEC7 is derived from 12V on the PCIe connector while the FMC card is powered by 3V3 on the PCIe connector.
This is done in order not to exceed the maximum power that may be drawn per PCIe slot.
Many different voltages are needed by the Zynq FPGA and DDR3 memories.
The power supplies are enabled sequentially.
Figure~\ref{fig:PowerSequenceLeCroy--00017.jpg} shows the power sequence after 12V is applied.
First 3V3 non-switched (3V3\_NWS) is created by the 10A switched mode power supply N2.
Next 1V35 is enabled which serves as a pre-regulator for the 1V0 VCCINT regulator.
Finally VCCINT is supplied by a linear regulator in order to create a low noise 1V0 voltage since the phase noise performance of the FPGA depends on the quality of VCCINT.
\begin{figure}[H]
\centering
\includegraphics[width=0.8\textwidth]{./pictures/Meas/PowerSequenceLeCroy--00017.jpg}
\caption{Power Sequence: 12V input $\Rightarrow$ 3V3 Non Switched $\Rightarrow$ 1V35 PreCore $\Rightarrow$ 1V0 VCCINT} %{see footnote\protect\footnotemark}
\label{fig:PowerSequenceLeCroy--00017.jpg}
\end{figure}
Figure~\ref{fig:PowerSequenceLeCroy--00018.jpg} shows the power sequence of power supplies for the FPGA.
After VCCINT is applied then the FPGA BANK voltages 1V8, 1V35 and 2V5 are supplied.
\begin{figure}[H]
\centering
\includegraphics[width=0.8\textwidth]{./pictures/Meas/PowerSequenceLeCroy--00018.jpg}
\caption{Power Sequence: 1V0 VCCINT $\Rightarrow$ 1V8 $\Rightarrow$ 1V35 $\Rightarrow$ 2V5} %{see footnote\protect\footnotemark}
\label{fig:PowerSequenceLeCroy--00018.jpg}
\end{figure}
When all FPGA voltages are supplied then finally 3V3 is enabled.
In order to lower the inrush current MOSFET V3 is switched on gradually as can be seen in figure~\ref{fig:PowerSequenceLeCroy--00019.jpg}
\begin{figure}[H]
\centering
\includegraphics[width=0.8\textwidth]{./pictures/Meas/PowerSequenceLeCroy--00019.jpg}
\caption{Gradually turn on V3 to enable 3V3} %{see footnote\protect\footnotemark}
\label{fig:PowerSequenceLeCroy--00019.jpg}
\end{figure}
Depending on whether the SPEC7 is powered by a PCIe slot or by an external power supply, either MOSFET V2 or V4 is gradually switch on to enable 3V3 for the FMC card (see figure~\ref{fig:PowerSequenceLeCroy--00026.jpg})
\begin{figure}[H]
\centering
\includegraphics[width=0.8\textwidth]{./pictures/Meas/PowerSequenceLeCroy--00026.jpg}
\caption{Gradually turn on V4 to enable 3V3 for the FMC card} %{see footnote\protect\footnotemark}
\label{fig:PowerSequenceLeCroy--00026.jpg}
\end{figure}
\subsection{Power Down Sequence}
Xilinx DS191 ~\cite{DS191} paragraph \enquote{PS Power-On/Off Power Supply Sequencing} states: \enquote{Before VCCINT reaches 0.80V the reference clock to the PS\_CLK input is disabled to ensure PS eFUSE integrity.} Figure~\ref{fig:PowerSequenceLeCroy--00020.jpg} shows that this condition is met.
\begin{figure}[H]
\centering
\includegraphics[width=0.8\textwidth]{./pictures/Meas/PowerSequenceLeCroy--00020.jpg}
\caption{Power Down Sequence} %{see footnote\protect\footnotemark}
\label{fig:PowerSequenceLeCroy--00020.jpg}
\end{figure}
\newpage
\ No newline at end of file
\section{Safety directions}
\begin{center}
\textbf{Please read this chapter before using the SPEC7}
\end{center}
\begin{figure}[H]%
\centering
\subfloat{{\includegraphics[width=5cm]{Waring_Pics/logo-attention.png} }}%
\qquad
\subfloat{{\includegraphics[width=5cm]{Waring_Pics/ESD.png} }}%
% \caption{2 Figures side by side}%
\label{fig:ESD_Warning_notes}%
\end{figure}
\begin{itemize}
\item Never exceed the maximum rated input voltage, a higher voltage as stated as maximum will damage the device.
See section ~\ref{sec:Power and Maximum ratings} for maximum allowed voltages.
\item The electronics is \textbf{ESD} sensitive, use a safe \textbf{ESD} workplace.
\item Although ESD protected, SiliconLabs CP2105 (U54, dual UART) seems to be a weak spot.
When the SPEC7 is operated stand alone then the chassis of the PC that is connected to the mini USB connector (X2) must be at SPEC7 ground potential.
See also section~\ref{sec:Mini_USB_when_operating_stand_alone}.
\end{itemize}
%Blablabla said Nobody ~\cite{Nobody06}
\newpage
\nomenclature{ESD}{Electrostatic Discharge.}
\section{Specifications}
\subsection{General}
\begin{itemize}
\item 2-lane PCIe Gen2
\item Xilinx Zynq-7000 FPGA (XC7Z030-1FBG676C) with Dual-Core ARM processor integrated
\item Possible upgrade to XC7Z035-1FBG676C or XC7Z045-1FBG676C
\item 4 GTX Transceivers (2 used for PCIe, 1 for SFP, 1 external accessible)
\item 2 GTX Reference Clocks (1 for PCIe, 1 for WR Clock)
\item FMC slot with High Pin Count (HPC) connector (only fully populated as LPC)
\item Z035 and Z045 support 4 GTX transceivers DP[3:0]\_M2C/C2M an 2 extra GTX Reference Clocks
\item JTAG accessible from the FPGA. JTAG switches automatically to the download cable when it is plugged.
\end{itemize}
\subsection{Clocking resources}
\begin{itemize}
\item 1x Fixed frequency 33.33 MHz oscillator for Application Processor Unit (APU)
\item 1x 10-280 MHz VCXO controlled by I2C and a DAC with SPI interface. Starts up at 125 MHz (Silicon Labs Si570/Si571, freely usable)
\item 1x 125.000 MHz VCXO controlled by a DAC with SPI interface (used by White Rabbit PTP core)
\item 1x 124.992 MHz VCXO controlled by a DAC with SPI interface (used by White Rabbit PTP core)
\item Low jitter external 10MHz via LTC6950 (supporting mode Grand Master \& AbsCal)
\item 10MHz TCXO for IEEE1588 v2.1 compliance (see J5.6.1) in Free-running Master mode.
\end{itemize}
\subsection{On board memory}
\begin{itemize}
\item 1x 8 Gbit (1 GByte) DDR3 connected to the 32-bit wide Memory Interface (main use for the APU)
\item 1x 8 Gbit (1 GByte) DDR3 connected to the programmable logic (32 bit wide)
\item 2x QSPI 256 Mbit flash PROM for multi-boot FPGA power-up configuration, storage of the FPGA firmware.
\item 64K (8K x 8-bit) I2C Serial EEPROM (24AA64T-I/MC) for storing serial number, calibration parameters and other critical data such as the MAC address of the card
\item 2x 2K (128 x 8-bit) I2C Serial EEPROM (24AA025E48) which provides EUI-48 (2 MAC addresses for APU and for WR)
\item MicroSD slot for flash memory for storing programs
\end{itemize}
\subsection{Miscellaneous}
\begin{itemize}
\item Thermometer (XADC) and semi-unique ID (DNA\_PORTE2) provided by the FPGA
\end{itemize}
\subsection{Front panel containing}
\begin{itemize}
\item 1x Small Formfactor Pluggable+ (SFP+) cage for fiber-optic transceiver (WhiteRabbit
support).
\item Programmable Red and Green LEDs
\item FMC front panel
\end{itemize}
\subsection{Internal connectors}
\begin{itemize}
\item 1x JTAG header for Xilinx programming during debugging
\item 1x mini USB Type B connector (serves 2 UARTs, one UART interface of the ARM and one to user logic, e.g. PTP core; Warning! See chapter ~\ref{sec:Mini_USB_when_operating_stand_alone}.)
\item 1x USB Type A connector connected to USB 2.0 port of the ARM
\item Ethernet RJ45 connector, magnetics and MicroChip KSZ9031RNX, 10/100/1000 Mbps PHY (interface to ARM GigE)
\item Samtec Bulls Eye connector (BDRA)
\item 2x connector for optional cooling fans
\item FPGA configuration via JTAG header, via ARM (i.e. Dual QSPI or using [PS PCAP / ICAP](see chapter 6.1.8 Zynq-7000 SoC Technical Reference Manual)
\end{itemize}
\subsection{Stand-alone features}
\begin{itemize}
\item External 12V 150W-ATX power supply connector
\item USB Type A connector
\item mini USB Type B connector (Warning! See chapter ~\ref{sec:Mini_USB_when_operating_stand_alone}.)
\item 10/100/1000 Mbps copper Ethernet RJ45
\item SFP+ cage for fibre-optic transceiver(White Rabbit support)
\item 7x LEDs (2x front panel, 4x on PCB, 1x PCI SMB-bus)
\item 5x buttons
\item 1 PS\_POR connected to reset controller
\item 1 PS\_SRTS\_B
\item 1 PL system reset
\item 1 general purpose
\item 1 PROGram button for FPGA
\end{itemize}
\newpage
\ No newline at end of file
\newpage
% Start of the revision history table
\addcontentsline{toc}{section}{Revision History}
\begin{versionhistory}
\vhEntry{0.0}{13-03-2020}{G C Visser}{Created.}
\vhEntry{0.1}{16-07-2020}{P Jansweijer}{1st (very) preliminary public version.}
\vhEntry{0.2}{15-09-2020}{P Jansweijer}{add details on reference and WRITE design.}
\vhEntry{0.3}{30-05-2021}{P Jansweijer}{SPEC7.git origin set to ohwr.org.}
\vhEntry{0.4}{24-09-2021}{P Jansweijer}{add note on 10MHz phase noise bump.}
\setcounter{table}{0}
\end{versionhistory}
\newpage
\ No newline at end of file
Schematic place holder
\ No newline at end of file
Schematic place holder
\ No newline at end of file
\author{G.C. Visser, P.P.M. Jansweijer, P. Bos}
\title{SPEC7 V2}
\date{24-09-2021}
\def\DocVer{Rev 0.4}
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\input{./Chapters/FirmwareSoftware.tex}
\input{./Chapters/Pinout.tex}
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\input{./Chapters/Power_And_Maxium_Ratings.tex}
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% The work described in this document is a part of the ASTERICS infrastructure cluster which is a part of the European Horizon
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for %%a in (*.svg) do call :do_convert %%a
goto donext
:do_convert
set PREFIX=%~n1
echo "Converting %1 to pdf"
start /wait inkscape -z -D --file=%1 --export-pdf=%PREFIX%.pdf
start /wait inkscape -z -D --file=%1 --export-png=%PREFIX%.png
goto :eof
:donext
#! /bin/bash
for f in *.svg
do
echo converting $f to pdf
inkscape -D --export-filename=${1%.*}.pdf $f
done
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