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SPEC7
Commit 65913abe authored by Peter Jansweijer's avatar Peter Jansweijer
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moved spec7 files from wr-cores up to spec7.git

parent 90697cb8
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hdl/board/Manifest.py 0 → 100644
View file @ 65913abe
files = [
"even_odd_det.vhd",
"wr_spec7_pkg.vhd",
"wrc_board_spec7.vhd",
"xwrc_board_spec7.vhd",
]
modules = {
"local" : [
"../wr-cores/board/common",
]
}
hdl/board/even_odd_det.vhd 0 → 100644
View file @ 65913abe
-------------------------------------------------------------------------------
-- Title : 10MHz-1PPS even/odd 125 MHz reference clock phase detector
-- Project : WR PTP Core and EMPIR 17IND14 WRITE
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-- : http://empir.npl.co.uk/write/
-------------------------------------------------------------------------------
-- File : even_odd_det.vhd
-- Author(s) : Peter Jansweijer <peterj@nikhef.nl>
-- Company : Nikhef
-- Created : 2020-08-24
-- Last update: 2020-08-24
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: When a PLL is used to generate 125 MHz from 10 MHz then the PLL
-- can lock on the even or odd 10MHz phase w.r.t. the 1 PPS. This
-- module detects where (even/odd) the lock was achieved.
--
-------------------------------------------------------------------------------
-- Copyright (c) 2020 Nikhef
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity even_odd_det is
port (
rst_n_i : in std_logic;
clk_ref_i : in std_logic;
clk_10m_ext_i : in std_logic;
clk_sys_62m5_i : in std_logic;
pps_i : in std_logic;
even_odd_n_o : out std_logic;
enable_sync_i : in std_logic;
sync_done_o : out std_logic;
sync_o : out std_logic
);
end entity even_odd_det;
architecture rtl of even_odd_det is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal rst : std_logic;
signal clk_10m_ext_pos : std_logic;
signal clk_10m_ext_neg : std_logic;
signal clk_10m_ext_pos_del : std_logic;
signal rising_pps : std_logic;
signal rising_clk_10m : std_logic;
signal arm_clk_10m_det : std_logic;
signal even_odd_n : std_logic;
signal enable_sync : std_logic;
signal enable : std_logic;
signal sync_done : std_logic;
begin -- architecture rtl
rst <= not rst_n_i;
cmp_iddr: IDDR
generic map (
DDR_CLK_EDGE => "SAME_EDGE")
port map (
Q1 => clk_10m_ext_pos,
Q2 => clk_10m_ext_neg,
C => clk_ref_i,
CE => '1',
D => clk_10m_ext_i,
R => rst,
S => '0');
-- If rising_edge clk_10m_ext_i is during clk_ref_i = '1' ("even") then
-- clk_10m_ext_pos and clk_10m_ext_neg are asserted at the same time
-- else ("odd") clk_10m_ext_pos is asserted before clk_10m_ext_neg in.
process (clk_ref_i, rst_n_i)
begin
if (rst_n_i = '0') then
clk_10m_ext_pos_del <= '0';
even_odd_n <= '0';
elsif rising_edge(clk_ref_i) then
clk_10m_ext_pos_del <= clk_10m_ext_pos;
-- detect a rising edge clk_10m_ext_pos (always 1 clk_ref_i tick
-- after the clock tick in which ppsi had a rising edge).
if (clk_10m_ext_pos_del = '0' and clk_10m_ext_pos = '1') then
-- detect simultanious assertion of clk_10m_ext_neg
if clk_10m_ext_neg = '1' then
even_odd_n <= '1';
else
even_odd_n <= '0';
end if;
end if;
end if;
end process;
-- detect rising edge PPS
cmp_pps_rising_edge: gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_ref_i,
rst_n_i => rst_n_i,
data_i => pps_i,
ppulse_o => rising_pps);
-- detect rising edge clk_10m
cmp_clk_10m_rising_edge: gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_ref_i,
rst_n_i => rst_n_i,
data_i => clk_10m_ext_i,
ppulse_o => rising_clk_10m);
-----------------------------------------------------------------------------
-- After rising edge PPS wait for first rising edge clk_10m and
-- trigger a sync clk_ref_62m5 divider if enabled.
-----------------------------------------------------------------------------
process (clk_ref_i, rst_n_i)
begin
if rst_n_i = '0' then
arm_clk_10m_det <= '0';
elsif rising_edge(clk_ref_i) then
if rising_pps = '1' then
arm_clk_10m_det <= '1';
elsif arm_clk_10m_det = '1' and rising_clk_10m = '1' then
arm_clk_10m_det <= '0';
end if;
end if;
end process;
-- update even_odd_n and synchronize clk_ref div2 divider if enabled
process (clk_ref_i, rst_n_i)
begin
if rst_n_i = '0' then
even_odd_n_o <= '0';
sync_o <= '0';
elsif rising_edge(clk_ref_i) then
sync_o <= '0';
if arm_clk_10m_det = '1' and rising_clk_10m = '1' then
even_odd_n_o <= even_odd_n;
if enable = '1' then
sync_o <= '1';
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- sync sequence enable and done
-----------------------------------------------------------------------------
-- synchronize enable_sync_i (clk_sys_62m5_i domain) to clk_ref_i
cmp_sync_ffs_enable_sync_i: gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_ref_i,
rst_n_i => rst_n_i,
data_i => enable_sync_i,
ppulse_o => enable_sync);
process (clk_ref_i, rst_n_i)
begin
if rst_n_i = '0' then
enable <= '0';
elsif rising_edge(clk_ref_i) then
if enable_sync = '1' then
enable <= '1';
elsif arm_clk_10m_det = '1' and rising_clk_10m = '1' then
enable <= '0';
end if;
end if;
end process;
sync_done <= not enable;
-- synchronize sync_done (clk_10m_ext_i domain) to clk_sys_62m5_i domain
cmp_sync_ffs_sync_done: gc_sync_ffs
generic map (
g_sync_edge => "positive")
port map (
clk_i => clk_sys_62m5_i,
rst_n_i => rst_n_i,
data_i => sync_done,
synced_o => sync_done_o);
end architecture rtl;
hdl/board/wr_spec7_pkg.vhd 0 → 100644
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hdl/board/wrc_board_spec7.vhd 0 → 100644
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hdl/board/xwrc_board_spec7.vhd 0 → 100644
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hdl/syn/spec7_golden_image/.gitignore 0 → 100644
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/.Xil
/work
/*.bak
/*.jou
/*.log
/*.prm
/*.mcs
/*.bin
/*.bit
/spec7_write_top_bd.bmm
/revisiondate_log.txt
/hdl_version.xdc
hdl/syn/spec7_golden_image/Manifest.py 0 → 100644
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board = "spec7"
target = "xilinx"
action = "synthesis"
syn_device = "xc7z035"
syn_grade = "-1"
syn_package = "fbg676"
syn_top = "spec7_golden_image_top"
syn_project = "spec7_golden_image_top.xpr"
syn_tool = "vivado"
modules = { "local" : "../../top/spec7_golden_image/"}
\ No newline at end of file
hdl/syn/spec7_golden_image/README.TXT 0 → 100644
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Synthesis and Place&Route README.TXT January 25, 2018
--------------------------------------------------------
Scripts:
--------
1) do_vivado.cmd start vivado (calling viv_do_all.tcl)
2) do_vivado_tcl.cmd start vivado tcl console.
You may want to type:
a) "start_gui" to start the vivado gui
b) "source proj_properties.tcl" to find the path to the scripts and next
"source $script_dir/viv_do_all.tcl"
3) do_elf.cmd combines the software and the empty "%DesName%.bit" file. Uses "software.elf", "%DesName%.bit"
and "%DesName%_bd.bmm" and merges them into "%DesName%_elf.bit"
4) do_vivado_prog.cmd download the configuration ("%DesName%_elf.bit") into the Evaluation board via the USB
download cable.
Project info and sources:
--------
proj_properties.tcl contains the project properties (name, device etc.)
proj_file_list.txt a text file with all project sources. Remember that the wr-cores files are listed
using "hdlmake list-files > proj_file_list.txt" in
directory "../../wr-cores/syn/clbv3_ref_design"
Scripts that are called by the scripts above or can be executed separately on the tcl command line:
--------
viv_do_synt.tcl sourced by viv_do_all.tcl, starts vivado synthesis run
viv_do_impl.tcl sourced by viv_do_all.tcl, starts vivado implementation run
viv_do_program.tcl sourced by do_vivado_prog.cmd
hdl/syn/spec7_golden_image/do_vivado.cmd 0 → 100644
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rem do_vivado.cmd PeterJ, 19-Jan-2018.
@prompt $$$s
rem ### Cleanup old log files and stuff
del *.log
del *.jou
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_do_all.tcl
hdl/syn/spec7_golden_image/do_vivado_gen_bin_mcs.cmd 0 → 100644
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rem prog.cmd PeterJ, 23-JUl-2018.
@prompt $$$s
rem ### Clean up old log files and stuff
del vivado_gen_bin_mcs.log
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_gen_bin_mcs.tcl -log vivado_gen_bin_mcs.log
hdl/syn/spec7_golden_image/do_vivado_prog.cmd 0 → 100644
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rem prog.cmd PeterJ, 23-Jan-2018.
@prompt $$$s
rem ### Cleanup old log files and stuff
del vivado_prog.log
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_do_program.tcl -log vivado_prog.log
hdl/syn/spec7_golden_image/do_vivado_tcl.cmd 0 → 100644
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rem do_vivado_tcl.cmd PeterJ, 19-Jan-2018.
@prompt $$$s
rem ### Usually one wants to start Vivado in tcl mode to inspect an existing design,
rem ### therefore don't delete log files and setting. Else remove "rem" statements in the lines below.
rem set DesName=clbv3_wr_ref_top
rem set LogName=%DesName%-vivado
rem ### Cleanup old log files and stuff (
rem del vivado*.log
rem del vivado*.jou
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode tcl
hdl/syn/spec7_golden_image/proj_file_list.txt 0 → 100644
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# From directory ....spec7/hdl/syn/spec7_golden_image
# hdlmake list-files > proj_file_list.txt
../../top/spec7_golden_image/spec7_golden_image_top.vhd
../../top/spec7_golden_image/spec7_golden_image_top.xdc
# bmm not supported by hdlmake? Need to add it manually...
../../ip/processing_system_pcie.bd
# include hardware version ID un FPGA USER_ID register:
hdl_version.xdc
hdl/syn/spec7_golden_image/proj_properties.tcl 0 → 100644
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#
# projetc_properties.tcl
# This file contains the general project properties such as the project name and
# the directory where Vivado is doing it's job
#
# ====================================================
# ====================================================
# SELECT DESIGN TO BUILD:
# ====================================================
set spec7_design spec7_golden_image_top
# ====================================================
# ====================================================
# SELECT DEVICE TO BUILD:
# ====================================================
# SPEC7 equipped with ZYNQ XC7Z035FBG676-1 (speed grade -1 has lowest performance)
set device xc7z035fbg676-1
#set device xc7z030fbg676-1
# ====================================================
set proj_name spec7_golden_image_top
set proj_dir work
set script_dir [pwd]/../../../sw/scripts
# update revision except when argument "no_update_revison" is passed (as for example by viv_do_programm.tcl)
if {$argc == 0 || $argv != "no_update_revision"} {
source $script_dir/revisiondate.tcl
set generics "g_design=$spec7_design"
}
hdl/syn/spec7_ref_design/.gitignore 0 → 100644
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/.Xil
/work
/*.bak
/*.jou
/*.log
/*.prm
/*.mcs
/*.bin
/*.bit
/spec7_write_top_bd.bmm
/revisiondate_log.txt
/hdl_version.xdc
hdl/syn/spec7_ref_design/Manifest.py 0 → 100644
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board = "spec7"
target = "xilinx"
action = "synthesis"
syn_device = "xc7z035"
syn_grade = "-1"
syn_package = "fbg676"
syn_top = "spec7_wr_ref_top"
syn_project = "spec7_wr_ref_top.xpr"
syn_tool = "vivado"
modules = { "local" : "../../top/spec7_ref_design/"}
\ No newline at end of file
hdl/syn/spec7_ref_design/README.TXT 0 → 100644
View file @ 65913abe
Synthesis and Place&Route README.TXT January 25, 2018
--------------------------------------------------------
Scripts:
--------
1) do_vivado.cmd start vivado (calling viv_do_all.tcl)
2) do_vivado_tcl.cmd start vivado tcl console.
You may want to type:
a) "start_gui" to start the vivado gui
b) "source proj_properties.tcl" to find the path to the scripts and next
"source $script_dir/viv_do_all.tcl"
3) do_elf.cmd combines the software and the empty "%DesName%.bit" file. Uses "software.elf", "%DesName%.bit"
and "%DesName%_bd.bmm" and merges them into "%DesName%_elf.bit"
4) do_vivado_prog.cmd download the configuration ("%DesName%_elf.bit") into the Evaluation board via the USB
download cable.
Project info and sources:
--------
proj_properties.tcl contains the project properties (name, device etc.)
proj_file_list.txt a text file with all project sources. Remember that the wr-cores files are listed
using "hdlmake list-files > proj_file_list.txt" in
directory "../../wr-cores/syn/clbv3_ref_design"
Scripts that are called by the scripts above or can be executed separately on the tcl command line:
--------
viv_do_synt.tcl sourced by viv_do_all.tcl, starts vivado synthesis run
viv_do_impl.tcl sourced by viv_do_all.tcl, starts vivado implementation run
viv_do_program.tcl sourced by do_vivado_prog.cmd
hdl/syn/spec7_ref_design/do_vivado.cmd 0 → 100644
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rem do_vivado.cmd PeterJ, 19-Jan-2018.
@prompt $$$s
rem ### Cleanup old log files and stuff
del *.log
del *.jou
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_do_all.tcl
hdl/syn/spec7_ref_design/do_vivado_gen_bin_mcs.cmd 0 → 100644
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rem prog.cmd PeterJ, 23-JUl-2018.
@prompt $$$s
rem ### Clean up old log files and stuff
del vivado_gen_bin_mcs.log
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_gen_bin_mcs.tcl -log vivado_gen_bin_mcs.log
hdl/syn/spec7_ref_design/do_vivado_prog.cmd 0 → 100644
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rem prog.cmd PeterJ, 23-Jan-2018.
@prompt $$$s
rem ### Cleanup old log files and stuff
del vivado_prog.log
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_do_program.tcl -log vivado_prog.log
hdl/syn/spec7_ref_design/do_vivado_tcl.cmd 0 → 100644
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rem do_vivado_tcl.cmd PeterJ, 19-Jan-2018.
@prompt $$$s
rem ### Usually one wants to start Vivado in tcl mode to inspect an existing design,
rem ### therefore don't delete log files and setting. Else remove "rem" statements in the lines below.
rem set DesName=clbv3_wr_ref_top
rem set LogName=%DesName%-vivado
rem ### Cleanup old log files and stuff (
rem del vivado*.log
rem del vivado*.jou
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode tcl
hdl/syn/spec7_ref_design/proj_file_list.txt 0 → 100644
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hdl/syn/spec7_ref_design/proj_properties.tcl 0 → 100644
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#
# projetc_properties.tcl
# This file contains the general project properties such as the project name and
# the directory where Vivado is doing it's job
#
# ====================================================
# ====================================================
# SELECT DESIGN TO BUILD:
# ====================================================
# Reference Design (using fmc-dio-5chttla => https://ohwr.org/project/fmc-dio-5chttla/wikis/home)
# HPSEC Design (using Bulls-Eye connector)
set spec7_design spec7_ref_top
#set spec7_design spec7_hpsec_top
# ====================================================
# ====================================================
# SELECT DEVICE TO BUILD:
# ====================================================
# SPEC7 equipped with ZYNQ XC7Z035FBG676-1 (speed grade -1 has lowest performance)
set device xc7z035fbg676-1
#set device xc7z030fbg676-1
# ====================================================
# ====================================================
# SELECT PPS SINLGE / DIFFERENTIAL:
# ====================================================
# When Bulls-Eye connector is used as input (HPSEC).
# Differential: B01/B02 (LVDS)
# Single-ended: B11 (TTL, 5V tolerant)
set pps_in "single"
#set pps_in "diff"
# ====================================================
set proj_name spec7_wr_ref_top
set proj_dir work
set script_dir [pwd]/../../../sw/scripts
set lm32_wrpc_initf [pwd]/../../../sw/precompiled/wrps-sw-v5_spec7/wrc.bram
set lm32_wrpc_elf [pwd]/../../../sw/precompiled/wrps-sw-v5_spec7/wrc.elf
set lm32_wrpc_instpath "lm32_wrpc_memory"
# update revision except when argument "no_update_revison" is passed (as for example by viv_do_programm.tcl)
if {$argc == 0 || $argv != "no_update_revision"} {
source $script_dir/revisiondate.tcl
set generics "g_design=$spec7_design \
g_use_pps_in=$pps_in \
g_dpram_initf=$lm32_wrpc_initf"
}
hdl/top/spec7_golden_image/Manifest.py 0 → 100644
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files = [
"spec7_golden_image_top.vhd",
"spec7_golden_image_top.xdc",
]
hdl/top/spec7_golden_image/spec7_golden_image_top.vhd 0 → 100644
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hdl/top/spec7_golden_image/spec7_golden_image_top.xdc 0 → 100644
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hdl/top/spec7_ref_design/Manifest.py 0 → 100644
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fetchto = "../../wr-cores"
fetchto = "../../wr-cores/ip_cores"
files = [
"gen_10mhz.vhd",
"pll_62m5_500m.vhd",
"spec7_wr_ref_top.vhd",
"spec7_wr_ref_top.xdc",
"spec7_wr_ref_top.bmm",
]
modules = {
"local" : [
"../../board/",
"../../wr-cores/",
],
"git" : [
"git://ohwr.org/project/wr-cores.git",
],
"git" : [
"git://ohwr.org/hdl-core-lib/general-cores.git",
],
}
hdl/top/spec7_ref_design/gen_10mhz.vhd 0 → 100644
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-------------------------------------------------------------------------------
-- Title : Xilinx 10MHz output generator
-- Project : WR PTP Core and EMPIR 17IND14 WRITE
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-- : http://empir.npl.co.uk/write/
-------------------------------------------------------------------------------
-- File : gen_10mhz.vhd
-- Author(s) : Peter Jansweijer <peterj@nikhef.nl>
-- Company : Nikhef
-- Created : 2018-12-10
-- Last update: 2018-12-10
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Creates a 10 MHz output clock that is locked to the reference
-- clock and is PPS phase aligned.
-- To achieve this, a 500 MHz reference clock is necessary.
-- Note: 10 MHz = 50 ns '1', 50 ns '0'
-- 50 ns is divisible by 2 ns (not by 8 or 4 ns!) hence 500 MHz.
-------------------------------------------------------------------------------
-- Copyright (c) 2018 Nikhef
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.NUMERIC_STD.all;
library work;
use work.gencores_pkg.all;
use work.genram_pkg.all;
entity gen_10mhz is
port (
clk_500m_i : in std_logic;
rst_n_i : in std_logic;
pps_i : in std_logic;
-- generated 10 MHz synced with PPS
clk_10mhz_o : out std_logic := '0');
end gen_10mhz;
architecture rtl of gen_10mhz is
signal rst_n_synced : std_logic := '0';
signal pps_synced : std_logic := '0';
signal pps_delayed : std_logic := '0';
begin -- rtl
process (clk_500m_i)
begin
if rising_edge(clk_500m_i) then
-- clk_500m is locked to the reference clock domain
-- although clocks are phase locked, first synchronize pps_i
-- and rst_n_i to 500 MHz to ease timing closure.
rst_n_synced <= rst_n_i;
pps_synced <= pps_i;
pps_delayed <= pps_synced;
end if;
end process;
pr_10mhz_gen : process (clk_500m_i, rst_n_synced)
variable cntr: integer range 0 to 99;
begin -- process pr_10mhz_gen
if rst_n_synced = '0' then
cntr := 0;
elsif rising_edge(clk_500m_i) then
if ((pps_synced = '1' and pps_delayed = '0') or cntr = 49) then
cntr := 0;
elsif cntr < 49 then
cntr := cntr + 1;
end if;
if cntr < 25 then
clk_10mhz_o <= '1';
else
clk_10mhz_o <= '0';
end if;
end if;
end process pr_10mhz_gen;
end rtl;
hdl/top/spec7_ref_design/pll_62m5_500m.vhd 0 → 100644
View file @ 65913abe
-------------------------------------------------------------------------------
-- Title : Xilinx family-7 PLL
-- : based on MMCME2_ADV
-- Project : WR PTP Core and EMPIR 17IND14 WRITE
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-- : http://empir.npl.co.uk/write/
-------------------------------------------------------------------------------
-- File : pll_62m5_500m.vhd
-- Author(s) : Peter Jansweijer <peterj@nikhef.nl>
-- Company : Nikhef
-- Created : 2018-12-10
-- Last update: 2018-12-10
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: In order to create a 10 MHz output clock that is phase
-- aligned with the 125 MHz reference clock one needs 500 MHz.
--
-------------------------------------------------------------------------------
-- Copyright (c) 2018 Nikhef
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
library unisim;
use unisim.vcomponents.all;
entity pll_62m5_500m is
port (
---------------------------------------------------------------------------`
-- Clocks/resets
---------------------------------------------------------------------------
areset_n_i : in std_logic;
-- 125.000 MHz PLL reference (BUFG copy of GTP/GTX)
clk_62m5_pllref_i : in std_logic;
-- 500 MHz out
clk_500m_o : out std_logic;
-- PLL Status
pll_500m_locked_o : out std_logic
);
end entity pll_62m5_500m;
architecture rtl of pll_62m5_500m is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- clock and reset
signal clk_500m : std_logic;
signal clk_sys_fb : std_logic;
signal pll_arst : std_logic;
begin -- architecture rtl
-- active high async reset for PLL
pll_arst <= not areset_n_i;
-- System PLL (125 MHz -> 62.5 MHz)
cmp_sys_clk_pll : MMCME2_ADV
generic map (
BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => false,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => false,
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT_F => 16.000, -- 62.5 MHz x 16 = 1 GHz.
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => false,
CLKOUT0_DIVIDE_F => 2.000, -- 500 MHz clock
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => false,
CLKIN1_PERIOD => 8.000, -- 8 ns means 125 MHz
REF_JITTER1 => 0.010)
port map (
-- Output clocks
CLKFBOUT => clk_sys_fb,
CLKOUT0 => clk_500m,
-- Input clock control
CLKFBIN => clk_sys_fb,
CLKIN1 => clk_62m5_pllref_i,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => open,
DRDY => open,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => open,
-- Other control and status signals
LOCKED => pll_500m_locked_o,
CLKINSTOPPED => open,
CLKFBSTOPPED => open,
PWRDWN => '0',
RST => pll_arst);
-- System PLL output clock buffer
cmp_clk_500m_buf_o : BUFG
port map (
I => clk_500m,
O => clk_500m_o);
end architecture rtl;
hdl/top/spec7_ref_design/spec7_wr_hpsec_top.xdc 0 → 100644
View file @ 65913abe
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hdl/top/spec7_ref_design/spec7_wr_ref_top.bmm 0 → 100644
View file @ 65913abe
/* FILE : spec7_wr_ref_top.bmm
* Define a BRAM map for the LM32 memory.
* ISE: Run Translate -> "Floorplan Area/IO/Logic (PlanAhead)" once (without this BMM file
* attached to the ISE Project) to find out that there are 16 ramloops and each RAMB36E1
* VIVADO: find brams (see also viv_find_brams.tcl)
* set my_rams [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ BMEM.bram.* }]
* foreach ram_block $my_rams {
* puts $ram_block
* }
* Note: *THE RAMLOOP ORDER WITHIN A BUS BLOCK IS VERY IMPORTANT!!!*
* Define ramloop 15 downto 0 and databits 31 downto 0 !!! Otherwise the memory
* content will be swapped and the program fails to execute. Apparently the ramloop
* number and bit definitions are not read by data2mem.
*
* Address space LM32 memory
* g_dpram_size = 128 KB = 131072 bytes / 4 = 32768 32-bit words
*
* ATTENTION PARITY!
* Although the memory is implemented in RAMB36E1 the address same MUST be defined as
* RAMB32 (instead of RAMB36) since we are NOT using parity! If the address space is
* defined as RAMB36 then data2mem is expecting an extra nibble for each 32 bit instruction
* in the ".elf" file and since this nibble is not provided, the ramblocks will be filled
* such that a nibble shift is accumulating in the data.
* Note that this can be examined using the data2mem command
* "data2mem -bm spec7_wr_ref_top_bd.bmm -bt spec7_wr_ref_top_elf.bit -d > dump.txt"
*
****************************************************************************************/
ADDRESS_SPACE lm32_wrpc_memory COMBINED [0x00000000:0x0001FFFF]
ADDRESS_RANGE RAMB32
BUS_BLOCK
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_7 [31:31] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_6 [30:30] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_5 [29:29] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_4 [28:28] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_3 [27:27] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_2 [26:26] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_1 [25:25] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram3_reg_0_0 [24:24] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_7 [23:23] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_6 [22:22] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_5 [21:21] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_4 [20:20] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_3 [19:19] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_2 [18:18] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_1 [17:17] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram2_reg_0_0 [16:16] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_7 [15:15] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_6 [14:14] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_5 [13:13] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_4 [12:12] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_3 [11:11] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_2 [10:10] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_1 [9:9] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram1_reg_0_0 [8:8] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_7 [7:7] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_6 [6:6] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_5 [5:5] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_4 [4:4] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_3 [3:3] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_2 [2:2] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_1 [1:1] [0:32767];
cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/DPRAM/U_DPRAM/gen_splitram.U_RAM_SPLIT/ram0_reg_0_0 [0:0] [0:32767];
END_BUS_BLOCK;
END_ADDRESS_RANGE;
END_ADDRESS_SPACE;
\ No newline at end of file
hdl/top/spec7_ref_design/spec7_wr_ref_top.vhd 0 → 100644
View file @ 65913abe
This diff is collapsed.
hdl/top/spec7_ref_design/spec7_wr_ref_top.xdc 0 → 100644
View file @ 65913abe
This diff is collapsed.
wr-cores @ 909a4076
Subproject commit 6a0227ff199ac6df6b17b3336c14eff978965538
Subproject commit 909a40763bfe58d23826e8f5bea70935e3682629
sw/scripts/viv_do_all.tcl
View file @ 65913abe
......@@ -140,10 +140,10 @@ foreach line $content {
if {[info exists spec7_design]} {
if {$spec7_design == "spec7_ref_top"} {
puts "use spec7_wr_ref_top.xdc"
read_xdc -verbose ../../wr-cores/top/spec7_ref_design/spec7_wr_ref_top.xdc
read_xdc -verbose ../../top/spec7_ref_design/spec7_wr_ref_top.xdc
} elseif {$spec7_design == "spec7_hpsec_top"} {
puts "use spec7_wr_hpsec_top.xdc"
read_xdc -verbose ../../wr-cores/top/spec7_ref_design/spec7_wr_hpsec_top.xdc
read_xdc -verbose ../../top/spec7_ref_design/spec7_wr_hpsec_top.xdc
}
}
......
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