Commit 41012e4c authored by Peter Jansweijer's avatar Peter Jansweijer

update precompiled wrpc-sw for spec7 virgo demo

parent fe522567
Pipeline #4189 failed with stage
in 2 minutes and 7 seconds
......@@ -9,7 +9,7 @@
# CONFIG_TARGET_ERTM14 is not set
# CONFIG_TARGET_SIS8300KU is not set
CONFIG_TARGET_SPEC7=y
# CONFIG_TARGET_HPSEC is not set
CONFIG_TARGET_HPSEC=y
# CONFIG_TARGET_PXIE_FMC is not set
CONFIG_WR_NODE=y
CONFIG_PPSI_FORCE_CONFIG=y
......@@ -30,7 +30,7 @@ CONFIG_EMBEDDED_NODE=y
CONFIG_PPSI=y
CONFIG_W1=y
CONFIG_LATENCY_ETHTYPE=291
# CONFIG_IPMI_CONSOLE is not set
CONFIG_IPMI_CONSOLE=y
# CONFIG_P2P is not set
CONFIG_IP=y
CONFIG_CMD_CONFIG=y
......
wrpc-sw.git:
63ea1b04 (HEAD -> spec7_proposed_master, origin/spec7_proposed_master) TX Phase timing became critical after moving to Use ODIV2 instead of a separate div2 FF
1c12022f slightly wider tolerance avoids endless sampling and no link up
09798d30 (origin/spec7_master, origin/peter_210324_spec7_wrpc-v5, spec7_master) add safe tx phase offset for SPEC7
86db2a4e (HEAD -> spec7_virgo_demo, origin/spec7_virgo_demo) exchange link-up and time-valid front pannel leds
4ae1777c TEMP_FIX sys_siglist deprecated
00913064 slightly wider tolerance avoids endless sampling and no link up
80a6aa3e add safe tx phase offset for SPEC7. For ODIV2 use TX_PHASE_OFFSET = 0 (for separate div2 FF TX_PHASE_OFFSET = 2000)
ppsi.git:
58d7be56 (HEAD) implement pre- and post-pll_lock spec7 function call
4ea2853b incremented mode master lock timeout
dc1c7d26 (origin/tom-wrpc-v5.0) arch-wrpc: use new endpoint API
faf82346 wr-constants: increase PLL lock timeout to 60 seconds, it takes a while on the OCXO in eRTM15
1af0725b arch-wrpc: follow up wrpc-sw-v5 changes in the softpll API
This diff is collapsed.
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment