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SPEC7
Commit 36fe5fbd authored by Peter Jansweijer's avatar Peter Jansweijer
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repair vuart wr peripheral interconnect base address (spec7 g_ram_address_space_size_kb => 256)

parent 8d25772f
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sw/scripts/vuart/spec7_vuart.py
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......@@ -17,8 +17,8 @@ import time
import termios
import pdb
syscon_addr = 0x20400
vuart_addr = 0x20500
syscon_addr = 0x40400
vuart_addr = 0x40500
xmda_user_fd = 0;
parser = argparse.ArgumentParser(description='Terminal interface to the uart of the wr core on the SPEC card')
......
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