Initial commit on IRIG_B capable spec7. DIO LEMO 3 is now IRIG_B output.

2a91b945 · Pascal Bos · cbaff7e9 · 2a91b945 · 2a91b945 · 2a91b945
Commit 2a91b945 authored Oct 11, 2021 by Pascal Bos
5 changed files
--- a/hdl/ip/ip/bcd_divider/bcd_divider.xci
+++ b/hdl/ip/ip/bcd_divider/bcd_divider.xci
--- a/hdl/ip/ip/tai_divider/tai_divider.xci
+++ b/hdl/ip/ip/tai_divider/tai_divider.xci
--- a/hdl/syn/spec7_ref_design/proj_file_list.txt
+++ b/hdl/syn/spec7_ref_design/proj_file_list.txt
@@ -5,7 +5,7 @@
 # the XDC file selection is done in sw/scripts/viv_do_all.tcl, based on $spec7_design
 #../../top/spec7_ref_design/spec7_wr_ref_top.xdc
 #../../top/spec7_ref_design/spec7_wr_hpsec_top.xdc
-
+../../top/spec7_ref_design/wr_irigb_conv.vhd
 ../../top/spec7_ref_design/pll_62m5_500m.vhd
 ../../wr-cores/ip_cores/general-cores/modules/common/gc_dec_8b10b.vhd
 ../../wr-cores/ip_cores/general-cores/modules/common/gc_edge_detect.vhd
@@ -176,6 +176,8 @@

 # bmm not supported by hdlmake? Need to add it manually...
 ../../ip/ps_pcie.bd
+../../ip/ip/bcd_divider/bcd_divider.xci
+../../ip/ip/tai_divider/tai_divider.xci
 ../../top/spec7_ref_design/spec7_wr_ref_top.bmm

 # include hardware version ID un FPGA USER_ID register:

--- a/hdl/top/spec7_ref_design/spec7_wr_ref_top.vhd
+++ b/hdl/top/spec7_ref_design/spec7_wr_ref_top.vhd
@@ -404,6 +404,11 @@ architecture top of spec7_wr_ref_top is
  signal araddr   : std_logic_vector(31 downto 0);
  signal awaddr   : std_logic_vector(31 downto 0);
  
+  --TAI
+  signal tm_time_valid : std_logic;
+  signal tm_tai : std_logic_vector(39 downto 0);
+  signal irigb : std_logic;
+  
  --Wishbone
  signal wb_master_i : t_wishbone_master_in; 
  signal wb_master_o : t_wishbone_master_out;
@@ -532,7 +537,22 @@ AXI2WB : xwb_axi4lite_bridge
    wb_master_o  => wb_master_o,
    wb_master_i  => wb_master_i  
  );
-
+  -----------------------------------------------------------------------------
+  -- Tai to Irig_B converter
+  -----------------------------------------------------------------------------
+  
+TAI2IRIGB : entity work.wr_irigb_conv(Behavioral)
+  generic map(
+    clk_freq => 62500000
+  )
+  port map(
+    clk_i           => clk_sys_62m5,
+    rst_n_i         => reset_n_i,
+    pps_i           => wrc_pps_out,
+    irig_b_o        => irigb,
+    tm_time_valid_i => tm_time_valid,
+    tm_tai_i        => tm_tai
+  );
  -----------------------------------------------------------------------------
  -- The WR PTP core board package (WB Slave + WB Master)
  -----------------------------------------------------------------------------
@@ -606,6 +626,12 @@ AXI2WB : xwb_axi4lite_bridge
      abscal_txts_o       => wrc_abscal_txts_out,
      abscal_rxts_o       => wrc_abscal_rxts_out,

+      -- TAI
+      tm_link_up_o        => open,
+      tm_time_valid_o     => tm_time_valid,
+      tm_tai_o            => tm_tai,
+      tm_cycles_o         => open,
+      
      pps_ext_i           => wrc_pps_in,
      pps_p_o             => wrc_pps_out,
      pps_led_o           => wrc_pps_led,
@@ -736,7 +762,7 @@ AXI2WB : xwb_axi4lite_bridge

  U_obuf_dio_o_2 : OBUFDS
    port map (
-      I  => wrc_abscal_txts_out,
+      I  => irigb,--wrc_abscal_txts_out,
      O  => fmc_la08_p,  -- dio_p_o[2] <=> DIO Lemo 3
      OB => fmc_la08_n); -- dio_n_o[2] <=> DIO Lemo 3


--- a/hdl/top/spec7_ref_design/wr_irigb_conv.vhd
+++ b/hdl/top/spec7_ref_design/wr_irigb_conv.vhd