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Commit 2153ceb1 authored by Peter Jansweijer's avatar Peter Jansweijer
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Added license header to script files

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sw/scripts/VSim_Current_Revision.tcl
View file @ 2153ceb1
#-----------------------------------------------------------------------------
# Title : Set Current Revision
#-----------------------------------------------------------------------------
# File : VSim_Current_Revision.tcl
# Author : Peter Jansweijer <peterj@nikhef.nl>
# Company : Nikhef
# Created : 2018-01-24
# Last update: 2021-06-01
# Platform : FPGA-generics
# Standard : VHDL
#-----------------------------------------------------------------------------
# Description:
#
# Set and Get the current Date and Revision number
#-----------------------------------------------------------------------------
#
# Copyright (c) 2021 Nikhef, Peter Jansweijer
#
# This source file is free software; you can redistribute it
# and/or modify it under the terms of the GNU Lesser General
# Public License as published by the Free Software Foundation;
# either version 2.1 of the License, or (at your option) any
# later version.
#
# This source is distributed in the hope that it will be
# useful, but WITHOUT ANY WARRANTY; without even the implied
# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
# PURPOSE. See the GNU Lesser General Public License for more
# details.
#
# You should have received a copy of the GNU Lesser General
# Public License along with this source; if not, download it
# from http://www.gnu.org/licenses/lgpl-2.1.html
#
#-----------------------------------------------------------------------------
# VSim_Current_Revision.tcl
puts "current year = [set current_year [scan [clock format [clock seconds] -format %y] %d]]"
......
sw/scripts/conv_file_list_to_xilinx.py
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#!/usr/bin/python
"""
conv_file_list_to_xilinx.py:
Converts the file that lists al files needed in the project to Xilinx ".prj" and
".ise" files. The input file list is usually a concatenation of the file list that
is generated using: "hdlmake list-files > hdlmake_list" together with a list
of CLB project files.
-------------------------------------------------------------------------------
Copyright (C) 2017 Peter Jansweijer
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>
-------------------------------------------------------------------------------
#-----------------------------------------------------------------------------
# Title : Vidado Do All
#-----------------------------------------------------------------------------
# File : conv_file_list_to_xilinx.py
# Author : Peter Jansweijer <peterj@nikhef.nl>
# Company : Nikhef
# Created : 2018-01-24
# Last update: 2021-06-01
# Platform : FPGA-generics
# Standard : VHDL
#-----------------------------------------------------------------------------
# Description:
#
# Converts the file that lists al files needed in the project to Xilinx ".prj" and
# ".ise" files. The input file list is usually a concatenation of the file list that
# is generated using: "hdlmake list-files > hdlmake_list" together with a list
# of private project files.
#-----------------------------------------------------------------------------
#
# Copyright (c) 2021 Nikhef, Peter Jansweijer
#
# This source file is free software; you can redistribute it
# and/or modify it under the terms of the GNU Lesser General
# Public License as published by the Free Software Foundation;
# either version 2.1 of the License, or (at your option) any
# later version.
#
# This source is distributed in the hope that it will be
# useful, but WITHOUT ANY WARRANTY; without even the implied
# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
# PURPOSE. See the GNU Lesser General Public License for more
# details.
#
# You should have received a copy of the GNU Lesser General
# Public License along with this source; if not, download it
# from http://www.gnu.org/licenses/lgpl-2.1.html
#
#-----------------------------------------------------------------------------
Usage:
conv_file_list_to_xilinx.py
......
sw/scripts/do_vivado_mmi_elf.cmd
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rem prog.cmd PeterJ, 02-Jul-2020.
rem -----------------------------------------------------------------------------
rem Title : Do Vivado merge elf into bit using mmi
rem -----------------------------------------------------------------------------
rem File : do_vivado_mmi_elf.cmd
rem Author : Peter Jansweijer <peterj@nikhef.nl>
rem Company : Nikhef
rem Created : 2020-07-02
rem Last update: 2021-06-01
rem Platform : FPGA-generics
rem Standard : VHDL
rem -----------------------------------------------------------------------------
rem Description:
rem
rem This script merge elf into bit using mmi
rem -----------------------------------------------------------------------------
rem
rem Copyright (c) 2021 Nikhef, Peter Jansweijer
rem
rem This source file is free software; you can redistribute it
rem and/or modify it under the terms of the GNU Lesser General
rem Public License as published by the Free Software Foundation;
rem either version 2.1 of the License, or (at your option) any
rem later version.
rem
rem This source is distributed in the hope that it will be
rem useful, but WITHOUT ANY WARRANTY; without even the implied
rem warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
rem PURPOSE. See the GNU Lesser General Public License for more
rem details.
rem
rem You should have received a copy of the GNU Lesser General
rem Public License along with this source; if not, download it
rem from http://www.gnu.org/licenses/lgpl-2.1.html
rem
rem -----------------------------------------------------------------------------
@prompt $$$s
set proj_name=%~n1%
......
sw/scripts/do_vivado_mmi_elf.sh
View file @ 2153ceb1
#! /bin/bash
# do_vivado_mmi_elf.sh PascalB, 09-Jul-2020.
#-----------------------------------------------------------------------------
# Title : Do Vivado merge elf into bit using mmi
#-----------------------------------------------------------------------------
# File : do_vivado_mmi_elf.sh
# Author : Pascal Bos <bosp@nikhef.nl>
# Company : Nikhef
# Created : 2020-07-09
# Last update: 2021-06-01
# Platform : FPGA-generics
# Standard : VHDL
#-----------------------------------------------------------------------------
# Description:
#
# This script merge elf into bit using mmi
#-----------------------------------------------------------------------------
#
# Copyright (c) 2021 Nikhef, Peter Jansweijer
#
# This source file is free software; you can redistribute it
# and/or modify it under the terms of the GNU Lesser General
# Public License as published by the Free Software Foundation;
# either version 2.1 of the License, or (at your option) any
# later version.
#
# This source is distributed in the hope that it will be
# useful, but WITHOUT ANY WARRANTY; without even the implied
# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
# PURPOSE. See the GNU Lesser General Public License for more
# details.
#
# You should have received a copy of the GNU Lesser General
# Public License along with this source; if not, download it
# from http://www.gnu.org/licenses/lgpl-2.1.html
#
#-----------------------------------------------------------------------------
proj_name=$(basename $1 .bit)
lm32_wrpc_mmi=${proj_name}.mmi
......
sw/scripts/mem2bram.tcl
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###############################################################################
# mem2bram.tcl 25-Mar-2020
#-----------------------------------------------------------------------------
# Title : Convert Memory File to BRAM
#-----------------------------------------------------------------------------
# File : mem2bram.tcl
# Author : Peter Jansweijer <peterj@nikhef.nl>
# Company : Nikhef
# Created : 2020-03-25
# Last update: 2021-06-01
# Platform : FPGA-generics
# Standard : VHDL
#-----------------------------------------------------------------------------
# Description:
#
# $1 The first paramter is the filename to be used for input and output
# $2 Second parameter is the ramsize in bytes
#-----------------------------------------------------------------------------
#
# Copyright (c) 2021 Nikhef, Peter Jansweijer
#
# This source file is free software; you can redistribute it
# and/or modify it under the terms of the GNU Lesser General
# Public License as published by the Free Software Foundation;
# either version 2.1 of the License, or (at your option) any
# later version.
#
# This source is distributed in the hope that it will be
# useful, but WITHOUT ANY WARRANTY; without even the implied
# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
# PURPOSE. See the GNU Lesser General Public License for more
# details.
#
# You should have received a copy of the GNU Lesser General
# Public License along with this source; if not, download it
# from http://www.gnu.org/licenses/lgpl-2.1.html
#
#-----------------------------------------------------------------------------
# The names of the input MEM file and the output bram file:
puts "MEM input file name = [set mem_file "$1.mem"]"
......
sw/scripts/revisiondate.tcl
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###############################################################################
# revisiondate.tcl 08-Dec-2006
#-----------------------------------------------------------------------------
# Title : Get/Set Date and Revision Number
#-----------------------------------------------------------------------------
# File : revisiondate.tcl
# Author : Peter Jansweijer <peterj@nikhef.nl>
# Company : Nikhef
# Created : 2006-12-06
# Last update: 2021-06-01
# Platform : FPGA-generics
# Standard : VHDL
#-----------------------------------------------------------------------------
# Description:
#
# Set and Get the current Date and Revision number
#-----------------------------------------------------------------------------
#
# Copyright (c) 2021 Nikhef, Peter Jansweijer
#
# This source file is free software; you can redistribute it
# and/or modify it under the terms of the GNU Lesser General
# Public License as published by the Free Software Foundation;
# either version 2.1 of the License, or (at your option) any
# later version.
#
# This source is distributed in the hope that it will be
# useful, but WITHOUT ANY WARRANTY; without even the implied
# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
# PURPOSE. See the GNU Lesser General Public License for more
# details.
#
# You should have received a copy of the GNU Lesser General
# Public License along with this source; if not, download it
# from http://www.gnu.org/licenses/lgpl-2.1.html
#
#-----------------------------------------------------------------------------
# Calculate Current Date
set current_year [clock format [clock seconds] -format %y]
......
sw/scripts/viv_do_all.tcl
View file @ 2153ceb1
# viv_do_all.tcl PeterJ, 24-Jan-2018.
#-----------------------------------------------------------------------------
# Title : Vidado Do All
#-----------------------------------------------------------------------------
# File : viv_do_all.tcl
# Author : Peter Jansweijer <peterj@nikhef.nl>
# Company : Nikhef
# Created : 2018-01-24
# Last update: 2021-06-01
# Platform : FPGA-generics
# Standard : VHDL
#-----------------------------------------------------------------------------
# Description:
#
# This script does:
# set project name
......@@ -8,7 +19,27 @@
# launches synthesis
# launches implementation
# generates a bitfile
# ------------------------------------
#-----------------------------------------------------------------------------
#
# Copyright (c) 2021 Nikhef, Peter Jansweijer
#
# This source file is free software; you can redistribute it
# and/or modify it under the terms of the GNU Lesser General
# Public License as published by the Free Software Foundation;
# either version 2.1 of the License, or (at your option) any
# later version.
#
# This source is distributed in the hope that it will be
# useful, but WITHOUT ANY WARRANTY; without even the implied
# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
# PURPOSE. See the GNU Lesser General Public License for more
# details.
#
# You should have received a copy of the GNU Lesser General
# Public License along with this source; if not, download it
# from http://www.gnu.org/licenses/lgpl-2.1.html
#
#-----------------------------------------------------------------------------
# do more cores threads.....set the parameter to max threads of the machine.
set_param general.maxThreads 16
......
sw/scripts/viv_do_impl.tcl
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#-----------------------------------------------------------------------------
# Title : Vidado Do Implement
#-----------------------------------------------------------------------------
# File : viv_do_impl.tcl
# Author : Peter Jansweijer <peterj@nikhef.nl>
# Company : Nikhef
# Created : 2018-01-24
# Last update: 2021-06-01
# Platform : FPGA-generics
# Standard : VHDL
#-----------------------------------------------------------------------------
# Description:
#
# do_impl.tcl
# Implement the design
# Implement the design
#-----------------------------------------------------------------------------
#
# Copyright (c) 2021 Nikhef, Peter Jansweijer
#
# This source file is free software; you can redistribute it
# and/or modify it under the terms of the GNU Lesser General
# Public License as published by the Free Software Foundation;
# either version 2.1 of the License, or (at your option) any
# later version.
#
# This source is distributed in the hope that it will be
# useful, but WITHOUT ANY WARRANTY; without even the implied
# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
# PURPOSE. See the GNU Lesser General Public License for more
# details.
#
# You should have received a copy of the GNU Lesser General
# Public License along with this source; if not, download it
# from http://www.gnu.org/licenses/lgpl-2.1.html
#
#-----------------------------------------------------------------------------
set_property strategy Performance_ExtraTimingOpt [get_runs impl_1]
......
sw/scripts/viv_do_program.tcl
View file @ 2153ceb1
#-----------------------------------------------------------------------------
# Title : Vidado Do Program
#-----------------------------------------------------------------------------
# File : viv_do_program.tcl
# Author : Peter Jansweijer <peterj@nikhef.nl>
# Company : Nikhef
# Created : 2018-01-24
# Last update: 2021-06-01
# Platform : FPGA-generics
# Standard : VHDL
#-----------------------------------------------------------------------------
# Description:
#
# do_program.tcl
# Configure the fpga with bit file
# Configure the fpga with the bit file that resulted from the merged with the
# executable loader format (ELF).
#-----------------------------------------------------------------------------
#
# Copyright (c) 2021 Nikhef, Peter Jansweijer
#
# This source file is free software; you can redistribute it
# and/or modify it under the terms of the GNU Lesser General
# Public License as published by the Free Software Foundation;
# either version 2.1 of the License, or (at your option) any
# later version.
#
# This source is distributed in the hope that it will be
# useful, but WITHOUT ANY WARRANTY; without even the implied
# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
# PURPOSE. See the GNU Lesser General Public License for more
# details.
#
# You should have received a copy of the GNU Lesser General
# Public License along with this source; if not, download it
# from http://www.gnu.org/licenses/lgpl-2.1.html
#
#-----------------------------------------------------------------------------
# set proj_name and proj_dir (without updating the revision!):
set argv [list no_update_revision ]
......
sw/scripts/viv_do_synt.tcl
View file @ 2153ceb1
#-----------------------------------------------------------------------------
# Title : Vidado Do Synthesis
#-----------------------------------------------------------------------------
# File : viv_do_synt.tcl
# Author : Peter Jansweijer <peterj@nikhef.nl>
# Company : Nikhef
# Created : 2018-01-24
# Last update: 2021-06-01
# Platform : FPGA-generics
# Standard : VHDL
#-----------------------------------------------------------------------------
# Description:
#
# do_synt.tcl
# Synthesize the design
# Synthesize the design
#-----------------------------------------------------------------------------
#
# Copyright (c) 2021 Nikhef, Peter Jansweijer
#
# This source file is free software; you can redistribute it
# and/or modify it under the terms of the GNU Lesser General
# Public License as published by the Free Software Foundation;
# either version 2.1 of the License, or (at your option) any
# later version.
#
# This source is distributed in the hope that it will be
# useful, but WITHOUT ANY WARRANTY; without even the implied
# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
# PURPOSE. See the GNU Lesser General Public License for more
# details.
#
# You should have received a copy of the GNU Lesser General
# Public License along with this source; if not, download it
# from http://www.gnu.org/licenses/lgpl-2.1.html
#
#-----------------------------------------------------------------------------
puts "synthesizing the design"
......
sw/scripts/viv_find_brams.tcl
View file @ 2153ceb1
# viv_find_brams.tcl PeterJ, 24-Jan-2018.
#-----------------------------------------------------------------------------
# Title : Vidado Find BRAMS
#-----------------------------------------------------------------------------
# File : viv_find_brams.tcl
# Author : Peter Jansweijer <peterj@nikhef.nl>
# Company : Nikhef
# Created : 2018-01-24
# Last update: 2021-06-01
# Platform : FPGA-generics
# Standard : VHDL
#-----------------------------------------------------------------------------
# Description:
#
# This script does reports all BRAMs used in the design.
# It is intended to easily find the BRAM names that are needed for the creation
# of a bmm file.
# ------------------------------------
#-----------------------------------------------------------------------------
#
# Copyright (c) 2021 Nikhef, Peter Jansweijer
#
# This source file is free software; you can redistribute it
# and/or modify it under the terms of the GNU Lesser General
# Public License as published by the Free Software Foundation;
# either version 2.1 of the License, or (at your option) any
# later version.
#
# This source is distributed in the hope that it will be
# useful, but WITHOUT ANY WARRANTY; without even the implied
# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
# PURPOSE. See the GNU Lesser General Public License for more
# details.
#
# You should have received a copy of the GNU Lesser General
# Public License along with this source; if not, download it
# from http://www.gnu.org/licenses/lgpl-2.1.html
#
#-----------------------------------------------------------------------------
set my_rams [get_cells -hierarchical -filter { PRIMITIVE_TYPE =~ BMEM.bram.* }]
foreach ram_block $my_rams {
......
sw/scripts/viv_gen_bin_mcs.tcl
View file @ 2153ceb1
#-----------------------------------------------------------------------------
# Title : Vidado Generate BIN and MCS files
#-----------------------------------------------------------------------------
# File : viv_gen_bin_mcs.tcl
# Author : Peter Jansweijer <peterj@nikhef.nl>
# Company : Nikhef
# Created : 2018-01-24
# Last update: 2021-06-01
# Platform : FPGA-generics
# Standard : VHDL
#-----------------------------------------------------------------------------
# Description:
#
# viv_gen_bin_mcs.tcl
# Implement the design
# Generates BIN and MCS files
#-----------------------------------------------------------------------------
#
# Copyright (c) 2021 Nikhef, Peter Jansweijer
#
# This source file is free software; you can redistribute it
# and/or modify it under the terms of the GNU Lesser General
# Public License as published by the Free Software Foundation;
# either version 2.1 of the License, or (at your option) any
# later version.
#
# This source is distributed in the hope that it will be
# useful, but WITHOUT ANY WARRANTY; without even the implied
# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
# PURPOSE. See the GNU Lesser General Public License for more
# details.
#
# You should have received a copy of the GNU Lesser General
# Public License along with this source; if not, download it
# from http://www.gnu.org/licenses/lgpl-2.1.html
#
#-----------------------------------------------------------------------------
# set proj_name and proj_dir (without updating the revision!):
set argv [list no_update_revision ]
......
sw/scripts/viv_generate_bd_bmm.tcl
View file @ 2153ceb1
#-----------------------------------------------------------------------------
# Title : Vidado Generate _bd.bmm File
#-----------------------------------------------------------------------------
# File : viv_generate_bd_bmm.tcl
# Author : Peter Jansweijer <peterj@nikhef.nl>
# Company : Nikhef
# Created : 2018-01-24
# Last update: 2021-06-01
# Platform : FPGA-generics
# Standard : VHDL
#-----------------------------------------------------------------------------
# Description:
#
# Generates a Block Memory Mapping (BMM) file
#-----------------------------------------------------------------------------
#
# Copyright (c) 2021 Nikhef, Peter Jansweijer
#
# This source file is free software; you can redistribute it
# and/or modify it under the terms of the GNU Lesser General
# Public License as published by the Free Software Foundation;
# either version 2.1 of the License, or (at your option) any
# later version.
#
# This source is distributed in the hope that it will be
# useful, but WITHOUT ANY WARRANTY; without even the implied
# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
# PURPOSE. See the GNU Lesser General Public License for more
# details.
#
# You should have received a copy of the GNU Lesser General
# Public License along with this source; if not, download it
# from http://www.gnu.org/licenses/lgpl-2.1.html
#
#-----------------------------------------------------------------------------
#open_run impl_2
set project_bmm_files [get_files *.bmm]
set BB FALSE
......
sw/scripts/viv_generate_bd_mmi.tcl
View file @ 2153ceb1
#-----------------------------------------------------------------------------
# Title : Vidado Generate mmi File
#-----------------------------------------------------------------------------
# File : viv_generate_bd_mmi.tcl
# Author : Peter Jansweijer <peterj@nikhef.nl>
# Company : Nikhef
# Created : 2018-01-24
# Last update: 2021-06-01
# Platform : FPGA-generics
# Standard : VHDL
#-----------------------------------------------------------------------------
# Description:
#
# Generates a Memory Mapping Information (MMI) file
#-----------------------------------------------------------------------------
#
# Copyright (c) 2021 Nikhef, Peter Jansweijer
#
# This source file is free software; you can redistribute it
# and/or modify it under the terms of the GNU Lesser General
# Public License as published by the Free Software Foundation;
# either version 2.1 of the License, or (at your option) any
# later version.
#
# This source is distributed in the hope that it will be
# useful, but WITHOUT ANY WARRANTY; without even the implied
# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
# PURPOSE. See the GNU Lesser General Public License for more
# details.
#
# You should have received a copy of the GNU Lesser General
# Public License along with this source; if not, download it
# from http://www.gnu.org/licenses/lgpl-2.1.html
#
#-----------------------------------------------------------------------------
set project_bmm_files [get_files *.bmm]
set BB FALSE
......
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