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SPEC7
Commits
1d4cd7e3
Commit
1d4cd7e3
authored
Apr 12, 2022
by
Peter Jansweijer
Browse files
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Plain Diff
rebase onto wrpc-v5
parent
fa8c5124
Pipeline
#3580
failed with stage
in 6 seconds
Changes
14
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1
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14 changed files
with
150 additions
and
142 deletions
+150
-142
xwrc_board_spec7.vhd
hdl/board/xwrc_board_spec7.vhd
+1
-1
VCom_spec7_wr_ref_top_Functional.tcl
...sim/spec7_ref_design/VCom_spec7_wr_ref_top_Functional.tcl
+23
-21
VSim_Functional.tcl
hdl/sim/spec7_ref_design/VSim_Functional.tcl
+7
-7
spec7_wr_ref_top.smi
hdl/sim/spec7_ref_design/spec7_wr_ref_top.smi
+6
-6
wave.tcl
hdl/sim/spec7_ref_design/wave.tcl
+32
-11
proj_file_list.txt
hdl/syn/spec7_ref_design/proj_file_list.txt
+23
-22
proj_properties.tcl
hdl/syn/spec7_ref_design/proj_properties.tcl
+4
-4
Manifest.py
hdl/top/spec7_ref_design/Manifest.py
+3
-1
spec7_wr_ref_top.bmm
hdl/top/spec7_ref_design/spec7_wr_ref_top.bmm
+35
-53
wr-cores
hdl/wr-cores
+1
-1
do_vivado_mmi_elf.cmd
sw/scripts/do_vivado_mmi_elf.cmd
+7
-7
do_vivado_mmi_elf.sh
sw/scripts/do_vivado_mmi_elf.sh
+6
-6
mem2bram.tcl
sw/scripts/mem2bram.tcl
+1
-1
viv_do_all.tcl
sw/scripts/viv_do_all.tcl
+1
-1
No files found.
hdl/board/xwrc_board_spec7.vhd
View file @
1d4cd7e3
...
...
@@ -415,7 +415,7 @@ begin -- architecture struct
---------------------------------------------------------------------------
-- The PLL on the SPEC7 needs to be initialized before it outputs clk_125m_gtx_p/n_i.
-- Avoid a deadlock. The clk_dmtd is always present and is first used to bring alive
-- the
LM32
that exectutes a PLL initialisation before switching to clk_pll_62m5.
-- the
WRPC CPU
that exectutes a PLL initialisation before switching to clk_pll_62m5.
---------------------------------------------------------------------------
cmp_bufgmux
:
BUFGMUX
...
...
hdl/sim/spec7_ref_design/VCom_spec7_wr_ref_top_Functional.tcl
View file @
1d4cd7e3
This diff is collapsed.
Click to expand it.
hdl/sim/spec7_ref_design/VSim_Functional.tcl
View file @
1d4cd7e3
...
...
@@ -10,18 +10,18 @@ if {$Simulation} {
source
../../../sw/scripts/VSim_Current_Revision.tcl
puts
"elf file used for
lm32 in WRPC:
[
set
elf_file_lm32_wrpc
"..
\\
..
\\
..
\\
sw
\\
precompiled
\\
wrps-sw-v5_spec7
\\
wrc.elf"
]
"
set
lm32_wrpc_instpath
"lm32_wrpc
_memory"
puts
"elf file used for
CPU in WRPC:
[
set
elf_file_wrpc_cpu
"..
\\
..
\\
..
\\
sw
\\
precompiled
\\
wrps-sw-v5_spec7
\\
wrc.elf"
]
"
set
wrpc_cpu_instpath
"wrpc_cpu
_memory"
# !!! Note !!!: Don't forget to compile the software (elf file
)
for simulation
(
avoid printf etc. to speed up simulation time
)
# !!! Note !!!: The double \\ are there since the DOS command below needs backslashes and a single backslash is seen as a switch in tcl
# Generate a "
lm32
_memory.mem" file from the "elf" file content
exec
cmd.exe /c updatemem -meminfo spec7_wr_ref_top.smi -data
$elf
_file_
lm32_wrpc -proc
$lm32
_wrpc
_instpath -force
# Generate a "
wrpc_cpu
_memory.mem" file from the "elf" file content
exec
cmd.exe /c updatemem -meminfo spec7_wr_ref_top.smi -data
$elf
_file_
wrpc_cpu -proc
$wrpc
_cpu
_instpath -force
# Convert the "mem" to a "bram" (a format used by the White Rabbit "memory_loader_pkg.vhd"
)
do ../../../sw/scripts/mem2bram.tcl
lm32_wrpc
_memory 131072
# Now a fresh "
lm32_wrpc
_memory.bram" is in place for simulation and is loaded into xwb_dpram
do ../../../sw/scripts/mem2bram.tcl
wrpc_cpu
_memory 131072
# Now a fresh "
wrpc_cpu
_memory.bram" is in place for simulation and is loaded into xwb_dpram
# Note that -novopt causes No Optimization (some internal signals might get non-vivible by optimization
)
# Note that "-L unisim" is needed to find the primitive "BSCANE2" thta is instantiated in "$LM32_Sources/platform/kintex7/jtag_tap.v "
...
...
@@ -32,7 +32,7 @@ do ../../../sw/scripts/mem2bram.tcl lm32_wrpc_memory 131072
#vsim -voptargs="+acc" -novopt
vsim -voptargs=
"+acc=lnprv"
\
-G/spec7_wr_ref_top/g_simulation=$g_simulation
\
-G/spec7_wr_ref_top/g_dpram_initf=
lm32_wrpc
_memory.bram
\
-G/spec7_wr_ref_top/g_dpram_initf=
wrpc_cpu
_memory.bram
\
-t ps -L unisim -lib work work.spec7_wr_ref_top
# Depending on what needs to be simultated
...
...
hdl/sim/spec7_ref_design/spec7_wr_ref_top.smi
View file @
1d4cd7e3
<?xml version="1.0" encoding="UTF-8"?>
<MemInfoSimulation
Version=
"1"
Minor=
"1"
>
<Processor
Endianness=
"
Big"
InstPath=
"lm32_wrpc
_memory"
>
<AddressSpace
Name=
"
lm32_wrpc
_memory_dpram"
ECC=
"NONE"
Begin=
"0"
End=
"131071"
>
<BusBlock>
<BitLane
MemType=
"
lm32_wrpc
_memory_dpram"
MemType_DataWidth=
"32"
MemType_AddressDepth=
"131071"
>
<Processor
Endianness=
"
Little"
InstPath=
"wrpc_cpu
_memory"
>
<AddressSpace
Name=
"
wrpc_cpu
_memory_dpram"
ECC=
"NONE"
Begin=
"0"
End=
"131071"
>
<BusBlock>
<BitLane
MemType=
"
wrpc_cpu
_memory_dpram"
MemType_DataWidth=
"32"
MemType_AddressDepth=
"131071"
>
<DataWidth
MSB=
"31"
LSB=
"0"
/>
<AddressRange
Begin=
"0"
End=
"32767"
/>
<Parity
ON=
"false"
NumBits=
"0"
/>
<MemFile
Name=
"
lm32_wrpc
_memory.mem"
/>
<MemFile
Name=
"
wrpc_cpu
_memory.mem"
/>
</BitLane>
</BusBlock>
</AddressSpace>
</Processor>
<Config>
<Option
Name=
"Part"
Val=
"xc7
k160tfbg676-2
"
/>
<Option
Name=
"Part"
Val=
"xc7
z035fbg676-1
"
/>
</Config>
<DRC>
<Rule
Name=
"RDADDRCHANGE"
Val=
"false"
/>
...
...
hdl/sim/spec7_ref_design/wave.tcl
View file @
1d4cd7e3
...
...
@@ -10,17 +10,38 @@ add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/clk_sys_62m5
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/pll_clk_select
add wave -noupdate /spec7_wr_ref_top/uart_rxd_i
add wave -noupdate /spec7_wr_ref_top/uart_txd_o
add wave -noupdate -divider LM32
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/LM32_CORE/rst_n_i
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/LM32_CORE/clk_sys_i
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/LM32_CORE/dwb_i
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/LM32_CORE/dwb_o
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/LM32_CORE/iwb_i
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/LM32_CORE/iwb_o
add wave -noupdate -divider URV
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/U_CPU/g_CPU_ID
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/U_CPU/g_IRAM_INIT
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/U_CPU/g_IRAM_SIZE
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/U_CPU/clk_sys_i
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/U_CPU/rst_n_i
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/U_CPU/irq_i
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/U_CPU/dwb_i
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/U_CPU/dwb_o
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/U_CPU/host_slave_i
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/U_CPU/host_slave_o
add wave -noupdate -divider U_iram
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/U_CPU/U_iram/g_init_file
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/U_CPU/U_iram/rst_n_i
add wave -noupdate -divider U_iram_A
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/U_CPU/U_iram/clka_i
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/U_CPU/U_iram/bwea_i
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/U_CPU/U_iram/wea_i
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/U_CPU/U_iram/aa_i
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/U_CPU/U_iram/da_i
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/U_CPU/U_iram/qa_o
add wave -noupdate -divider U_iram_B
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/U_CPU/U_iram/clkb_i
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/U_CPU/U_iram/bweb_i
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/U_CPU/U_iram/web_i
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/U_CPU/U_iram/ab_i
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/U_CPU/U_iram/db_i
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/U_CPU/U_iram/qb_o
TreeUpdate
[
SetDefaultTree
]
WaveRestoreCursors
{{
Cursor 1
}
{
0
ps
}
0
}
quietly wave cursor active
0
configure wave -namecolwidth
150
WaveRestoreCursors
{{
Cursor 1
}
{
397897 ps
}
0
}
{{
Cursor 2
}
{
6454918 ps
}
0
}
{{
Cursor 3
}
{
18719262
ps
}
0
}
quietly wave cursor active
3
configure wave -namecolwidth
693
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
...
...
@@ -34,4 +55,4 @@ configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom
{
0 ps
}
{
315
us
}
WaveRestoreZoom
{
0 ps
}
{
630
us
}
hdl/syn/spec7_ref_design/proj_file_list.txt
View file @
1d4cd7e3
...
...
@@ -6,8 +6,8 @@
#../../top/spec7_ref_design/spec7_wr_ref_top.xdc
#../../top/spec7_ref_design/spec7_wr_hpsec_top.xdc
../../top/spec7_ref_design/wr_irigb_conv.vhd
../../top/spec7_ref_design/pll_62m5_500m.vhd
../../top/spec7_ref_design/wr_irigb_conv.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_dec_8b10b.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_edge_detect.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_enc_8b10b.vhd
...
...
@@ -16,11 +16,6 @@
../../wr-cores/ip_cores/general-cores/modules/common/gc_sync.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_sync_register.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gencores_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
...
...
@@ -28,11 +23,22 @@
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
../../wr-cores/ip_cores/urv-core/rtl/urv_csr.v
../../wr-cores/ip_cores/urv-core/rtl/urv_decode.v
../../wr-cores/ip_cores/urv-core/rtl/urv_divide.v
../../wr-cores/ip_cores/urv-core/rtl/urv_exceptions.v
../../wr-cores/ip_cores/urv-core/rtl/urv_fetch.v
../../wr-cores/ip_cores/urv-core/rtl/urv_multiply.v
../../wr-cores/ip_cores/urv-core/rtl/urv_regfile.v
../../wr-cores/ip_cores/urv-core/rtl/urv_shifter.v
../../wr-cores/ip_cores/urv-core/rtl/urv_timer.v
../../wr-cores/ip_cores/urv-core/rtl/urv_writeback.v
../../wr-cores/modules/fabric/xwrf_loopback/lbk_pkg.vhd
../../wr-cores/modules/timing/pulse_stamper.vhd
../../wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd
../../wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
../../wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd
../../wr-cores/modules/wr_endpoint/prbs/lfsr.v
../../wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd
../../wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd
../../wr-cores/modules/wr_streamers/escape_detector.vhd
...
...
@@ -40,7 +46,6 @@
../../wr-cores/modules/wr_streamers/fifo_showahead_adapter.vhd
../../wr-cores/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
../../wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd
../../wr-cores/modules/wrc_core/wrc_diags_pkg.vhd
../../wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd
../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx-lp/gtx_comma_detect_lp.vhd
../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx-lp/whiterabbit_gtxe2_channel_wrapper_gt_lp.vhd
...
...
@@ -51,21 +56,21 @@
../../wr-cores/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/genram_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
../../wr-cores/ip_cores/urv-core/rtl/urv_exec.v
../../wr-cores/modules/fabric/wr_fabric_pkg.vhd
../../wr-cores/modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd
../../wr-cores/modules/timing/dmtd_sampler.vhd
../../wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd
../../wr-cores/modules/wr_endpoint/prbs/lfsr_prbs_check.v
../../wr-cores/modules/wr_endpoint/prbs/lfsr_prbs_gen.v
../../wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd
../../wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
../../wr-cores/modules/wr_streamers/wr_streamers_wb.vhd
../../wr-cores/modules/wrc_core/wrc_
diags_wb
.vhd
../../wr-cores/modules/wrc_core/wrc_
cpu_csr_wbgen2_pkg
.vhd
../../wr-cores/modules/wrc_core/wrc_syscon_wb.vhd
../../board/even_odd_det.vhd
../../top/spec7_ref_design/gen_x_mhz.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_async_counter_diff.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
...
...
@@ -78,8 +83,9 @@
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
../../wr-cores/ip_cores/urv-core/rtl/urv_cpu.v
../../wr-cores/modules/fabric/xwrf_mux.vhd
../../wr-cores/modules/timing/dmtd_
sampl
er.vhd
../../wr-cores/modules/timing/dmtd_
with_deglitch
er.vhd
../../wr-cores/modules/timing/pulse_stamper_sync.vhd
../../wr-cores/modules/wr_endpoint/endpoint_pkg.vhd
../../wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd
...
...
@@ -88,7 +94,8 @@
../../wr-cores/modules/wr_streamers/dropping_buffer.vhd
../../wr-cores/modules/wr_streamers/fixed_latency_ts_match.vhd
../../wr-cores/modules/wr_streamers/ts_restore_tai.vhd
../../wr-cores/modules/wrc_core/xwrc_diags_wb.vhd
../../wr-cores/modules/wrc_core/wrc_cpu_csr_wb.vhd
../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx-lp/wr_gtx_phy_family7_lp.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
...
...
@@ -99,16 +106,14 @@
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
../../wr-cores/modules/timing/dmtd_
with_deglitcher
.vhd
../../wr-cores/modules/timing/dmtd_
phase_meas
.vhd
../../wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd
../../wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd
../../wr-cores/modules/wrc_core/wrcore_pkg.vhd
../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx-lp/wr_gtx_phy_family7_lp.vhd
../../wr-cores/platform/xilinx/wr_xilinx_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
../../wr-cores/modules/fabric/xwb_fabric_sink.vhd
../../wr-cores/modules/fabric/xwb_fabric_source.vhd
../../wr-cores/modules/timing/dmtd_phase_meas.vhd
../../wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd
../../wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd
../../wr-cores/modules/wr_endpoint/ep_leds_controller.vhd
...
...
@@ -131,8 +136,6 @@
../../wr-cores/modules/wr_streamers/streamers_pkg.vhd
../../wr-cores/board/common/wr_board_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd
../../wr-cores/modules/wr_endpoint/ep_packet_filter.vhd
../../wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd
../../wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd
...
...
@@ -141,15 +144,14 @@
../../wr-cores/modules/wr_streamers/streamers_priv_pkg.vhd
../../wr-cores/modules/wr_streamers/xrx_streamers_stats.vhd
../../wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd
../../wr-cores/modules/wrc_core/wrc_diags_dpram.vhd
../../wr-cores/modules/wrc_core/wrc_urv_wrapper.vhd
../../board/wr_spec7_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd
../../wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd
../../wr-cores/modules/wr_endpoint/ep_tx_path.vhd
../../wr-cores/modules/wr_streamers/fixed_latency_delay.vhd
../../wr-cores/modules/wr_streamers/xrtx_streamers_stats.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
../../wr-cores/modules/fabric/xwrf_loopback/xwrf_loopback.vhd
...
...
@@ -157,7 +159,6 @@
../../wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd
../../wr-cores/modules/wr_streamers/xrx_streamer.vhd
../../wr-cores/modules/wr_streamers/xtx_streamer.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd
../../wr-cores/modules/wr_endpoint/ep_rx_path.vhd
../../wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd
...
...
hdl/syn/spec7_ref_design/proj_properties.tcl
View file @
1d4cd7e3
...
...
@@ -66,9 +66,9 @@ if [info exists irig_b_enable] {
set
proj_name spec7_wr_ref_top
set
proj_dir work
set
script_dir
[
pwd
]
/../../../sw/scripts
set
lm32_wrpc
_initf
[
pwd
]
/../../../sw/precompiled/wrps-sw-v5_spec7/wrc.bram
set
lm32_wrpc
_elf
[
pwd
]
/../../../sw/precompiled/wrps-sw-v5_spec7/wrc.elf
set
lm32_wrpc_instpath
"lm32_wrpc
_memory"
set
wrpc_cpu
_initf
[
pwd
]
/../../../sw/precompiled/wrps-sw-v5_spec7/wrc.bram
set
wrpc_cpu
_elf
[
pwd
]
/../../../sw/precompiled/wrps-sw-v5_spec7/wrc.elf
set
wrpc_cpu_instpath
"wrpc_cpu
_memory"
# update revision except when argument "no_update_revison" is passed (as for example by viv_do_programm.tcl
)
if
{
$argc
== 0 ||
$argv
!=
"no_update_revision"
}
{
...
...
@@ -76,7 +76,7 @@ if {$argc == 0 || $argv != "no_update_revision"} {
set generics
"g_design=
$spec7
_design
\
g_use_pps_in=
$pps
_in
\
g_dpram_initf=
$
lm32
_wrpc
_initf
\
g_dpram_initf=
$
wrpc
_cpu
_initf
\
g_refclk_tune_pos_slope=
$vivbool
_refclk_tune_pos_slope
\
g_irig_b_enable=
$vivbool
_irig_b_enable"
}
hdl/top/spec7_ref_design/Manifest.py
View file @
1d4cd7e3
...
...
@@ -2,11 +2,12 @@ fetchto = "../../wr-cores"
fetchto
=
"../../wr-cores/ip_cores"
files
=
[
"gen_
10
mhz.vhd"
,
"gen_
x_
mhz.vhd"
,
"pll_62m5_500m.vhd"
,
"spec7_wr_ref_top.vhd"
,
"spec7_wr_ref_top.xdc"
,
"spec7_wr_ref_top.bmm"
,
"wr_irigb_conv.vhd"
,
]
modules
=
{
...
...
@@ -19,5 +20,6 @@ modules = {
],
"git"
:
[
"git://ohwr.org/hdl-core-lib/general-cores.git"
,
"git://ohwr.org/project/urv-core.git"
,
],
}
hdl/top/spec7_ref_design/spec7_wr_ref_top.bmm
View file @
1d4cd7e3
This diff is collapsed.
Click to expand it.
wr-cores
@
e621505c
Subproject commit
06448c066a65d2221c9eefeed22d45b300a0dc25
Subproject commit
e621505c33305c2a128de6f2a46e3aa72833c3c3
sw/scripts/do_vivado_mmi_elf.cmd
View file @
1d4cd7e3
...
...
@@ -5,7 +5,7 @@ rem File : do_vivado_mmi_elf.cmd
rem Author : Peter Jansweijer <peterj@nikhef.nl>
rem Company : Nikhef
rem Created : 2020-07-02
rem Last update: 202
1-06-01
rem Last update: 202
2-04-13
rem Platform : FPGA-generics
rem Standard : VHDL
rem -----------------------------------------------------------------------------
...
...
@@ -37,9 +37,9 @@ rem ----------------------------------------------------------------------------
@prompt $$$s
set proj_name=%~n1%
set
lm32_wrpc
_mmi=%proj_name%.mmi
set
lm32_wrpc
_elf=%2%
set
lm32_wrpc_instpath="lm32_wrpc
_memory"
set
wrpc_cpu
_mmi=%proj_name%.mmi
set
wrpc_cpu
_elf=%2%
set
wrpc_cpu_instpath="wrpc_cpu
_memory"
if not exist "%1%" (
@echo ### %1% ### bit file not found
...
...
@@ -63,8 +63,8 @@ if not "%~x2%"==".elf" (
exit /B
)
if not exist "%
lm32_wrpc
_mmi%" (
@echo ### %
lm32_wrpc
_mmi% ### mmi file not found, has it been generated?"
if not exist "%
wrpc_cpu
_mmi%" (
@echo ### %
wrpc_cpu
_mmi% ### mmi file not found, has it been generated?"
exit /B
)
rem ### Cleanup old log files and stuff
...
...
@@ -74,5 +74,5 @@ del updatemem*.log
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
%VIVADO%updatemem -meminfo %proj_name%.mmi -data %
lm32_wrpc_elf% -bit %proj_name%.bit -proc %lm32_wrpc
_instpath% -out %proj_name%_elf.bit -force >> vivado_mmi_elf.log
%VIVADO%updatemem -meminfo %proj_name%.mmi -data %
wrpc_cpu_elf% -bit %proj_name%.bit -proc %wrpc_cpu
_instpath% -out %proj_name%_elf.bit -force >> vivado_mmi_elf.log
sw/scripts/do_vivado_mmi_elf.sh
View file @
1d4cd7e3
...
...
@@ -7,7 +7,7 @@
# Author : Pascal Bos <bosp@nikhef.nl>
# Company : Nikhef
# Created : 2020-07-09
# Last update: 202
1-06-01
# Last update: 202
2-04-13
# Platform : FPGA-generics
# Standard : VHDL
#-----------------------------------------------------------------------------
...
...
@@ -37,9 +37,9 @@
#-----------------------------------------------------------------------------
proj_name
=
$(
basename
$1
.bit
)
lm32_wrpc
_mmi
=
${
proj_name
}
.mmi
lm32_wrpc
_elf
=
$2
lm32_wrpc_instpath
=
"lm32_wrpc
_memory"
wrpc_cpu
_mmi
=
${
proj_name
}
.mmi
wrpc_cpu
_elf
=
$2
wrpc_cpu_instpath
=
"wrpc_cpu
_memory"
if
not
[
-f
"
$1
"
]
;
then
echo
"
$1
bit file not found"
...
...
@@ -63,7 +63,7 @@ if not [ ${2: -4} == ".elf" ]; then
exit
fi
if
not
[
-f
"
$
lm32_wrpc
_mmi
"
]
;
then
if
not
[
-f
"
$
wrpc_cpu
_mmi
"
]
;
then
echo
"
$1
mmi file not found, has it been generated?"
exit
fi
...
...
@@ -73,4 +73,4 @@ rm vivado_mmi_elf.log 2>/dev/null
rm
updatemem
*
.jou 2>/dev/null
rm
updatemem
*
.log 2>/dev/null
updatemem
-meminfo
${
proj_name
}
.mmi
-data
$2
-bit
$1
-proc
$
lm32_wrpc
_instpath
-out
${
proj_name
}
_elf.bit
-force
>>
vivado_mmi_elf.log
updatemem
-meminfo
${
proj_name
}
.mmi
-data
$2
-bit
$1
-proc
$
wrpc_cpu
_instpath
-out
${
proj_name
}
_elf.bit
-force
>>
vivado_mmi_elf.log
sw/scripts/mem2bram.tcl
View file @
1d4cd7e3
...
...
@@ -81,7 +81,7 @@ if {[file exists $mem_file]} {
#
"IMPORTANT: Although Processor Endianness is defined in the MMI file, it is not supported by
# UpdateMEM at this time."
# updatemem acts by default
"Little"
endian! Swap necessairy for Big endian LM32!
set swap
tru
e
set swap
fals
e
while
{[
gets
$mem
_fileptr line
]
>= 0
}
{
set lineElements
[
llength
$line
]
...
...
sw/scripts/viv_do_all.tcl
View file @
1d4cd7e3
...
...
@@ -183,7 +183,7 @@ file copy ./work/${proj_name}.runs/impl_1/${proj_name}.bit ./work/${bitfile_name
if
[
file
exists ./$
{
proj_name
}
.mmi
]
{
file copy ./$
{
proj_name
}
.mmi ../$
{
bitfile_name
}
.mmi
file copy ./$
{
proj_name
}
.mmi ./work/$
{
bitfile_name
}
.mmi
exec updatemem -meminfo ./$
{
proj_name
}
.mmi -data
${
lm32_wrpc_elf}
-bit ./work/$
{
proj_name
}
.runs/impl_1/$
{
proj_name
}
.bit -proc
${lm32_wrpc
_instpath}
-out ../$
{
bitfile_name
}
_elf.bit -force
exec updatemem -meminfo ./$
{
proj_name
}
.mmi -data
${
wrpc_cpu_elf}
-bit ./work/$
{
proj_name
}
.runs/impl_1/$
{
proj_name
}
.bit -proc
${wrpc_cpu
_instpath}
-out ../$
{
bitfile_name
}
_elf.bit -force
file copy ../$
{
bitfile_name
}
_elf.bit ./work/$
{
bitfile_name
}
_elf.bit
}
if
[
file
exists ./$
{
proj_name
}
.xsa
]
{
...
...
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