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SPEC7
Commits
12c440cd
Commit
12c440cd
authored
Jun 28, 2021
by
Peter Jansweijer
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move spec7_ref_design simulation directory
parent
7ab6647e
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.gitignore
hdl/sim/spec7_ref_design/.gitignore
+10
-0
VCom_spec7_wr_ref_top_Functional.tcl
...sim/spec7_ref_design/VCom_spec7_wr_ref_top_Functional.tcl
+179
-0
VSim_Functional.tcl
hdl/sim/spec7_ref_design/VSim_Functional.tcl
+52
-0
modelsim.ini
hdl/sim/spec7_ref_design/modelsim.ini
+2125
-0
spec7_wr_ref_top.smi
hdl/sim/spec7_ref_design/spec7_wr_ref_top.smi
+21
-0
test.tcl
hdl/sim/spec7_ref_design/test.tcl
+11
-0
vlog.opt
hdl/sim/spec7_ref_design/vlog.opt
+3
-0
wave.tcl
hdl/sim/spec7_ref_design/wave.tcl
+37
-0
No files found.
hdl/sim/spec7_ref_design/.gitignore
0 → 100644
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12c440cd
/spec7.lib
/*.bram
/*.mem
/*.bak
/*.wlf
/*.vstf
/*.lnk
/*.jou
/*.log
/transcript
\ No newline at end of file
hdl/sim/spec7_ref_design/VCom_spec7_wr_ref_top_Functional.tcl
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12c440cd
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hdl/sim/spec7_ref_design/VSim_Functional.tcl
0 → 100644
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12c440cd
set
Simulation TRUE
if
{
$Simulation
}
{
puts
"Note: Simulation"
set g_simulation 1
}
else
{
puts
"Note: Synthesis"
set g_simulation 0
}
source
../../../sw/scripts/VSim_Current_Revision.tcl
puts
"elf file used for lm32 in WRPC:
[
set
elf_file_lm32_wrpc
"..
\\
..
\\
..
\\
sw
\\
precompiled
\\
wrps-sw-v5_spec7
\\
wrc.elf"
]
"
set
lm32_wrpc_instpath
"lm32_wrpc_memory"
# !!! Note !!!: Don't forget to compile the software (elf file
)
for simulation
(
avoid printf etc. to speed up simulation time
)
# !!! Note !!!: The double \\ are there since the DOS command below needs backslashes and a single backslash is seen as a switch in tcl
# Generate a "lm32_memory.mem" file from the "elf" file content
exec
cmd.exe /c updatemem -meminfo spec7_wr_ref_top.smi -data
$elf
_file_lm32_wrpc -proc
$lm32
_wrpc_instpath -force
# Convert the "mem" to a "bram" (a format used by the White Rabbit "memory_loader_pkg.vhd"
)
do ../../../sw/scripts/mem2bram.tcl lm32_wrpc_memory 131072
# Now a fresh "lm32_wrpc_memory.bram" is in place for simulation and is loaded into xwb_dpram
# Note that -novopt causes No Optimization (some internal signals might get non-vivible by optimization
)
# Note that "-L unisim" is needed to find the primitive "BSCANE2" thta is instantiated in "$LM32_Sources/platform/kintex7/jtag_tap.v "
#suppress warning Warning: (vsim-151
)
NUMERIC_STD.TO_INTEGER: Value <> is not in bounds of NATURAL.
#suppress warning Warning: (vsim-8684
)
No drivers exist on out port <blabla>
# -novopt is now deprecated
#vsim -voptargs="+acc" -novopt
vsim -voptargs=
"+acc=lnprv"
\
-G/spec7_wr_ref_top/g_simulation=$g_simulation
\
-G/spec7_wr_ref_top/g_dpram_initf=lm32_wrpc_memory.bram
\
-t ps -L unisim -lib work work.spec7_wr_ref_top
# Depending on what needs to be simultated
do wave.tcl
do test.tcl
view signals
#run 100 us
#stop
wave zoom full
#
# End
#
hdl/sim/spec7_ref_design/modelsim.ini
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hdl/sim/spec7_ref_design/spec7_wr_ref_top.smi
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12c440cd
<?xml version="1.0" encoding="UTF-8"?>
<MemInfoSimulation
Version=
"1"
Minor=
"1"
>
<Processor
Endianness=
"Big"
InstPath=
"lm32_wrpc_memory"
>
<AddressSpace
Name=
"lm32_wrpc_memory_dpram"
ECC=
"NONE"
Begin=
"0"
End=
"131071"
>
<BusBlock>
<BitLane
MemType=
"lm32_wrpc_memory_dpram"
MemType_DataWidth=
"32"
MemType_AddressDepth=
"131071"
>
<DataWidth
MSB=
"31"
LSB=
"0"
/>
<AddressRange
Begin=
"0"
End=
"32767"
/>
<Parity
ON=
"false"
NumBits=
"0"
/>
<MemFile
Name=
"lm32_wrpc_memory.mem"
/>
</BitLane>
</BusBlock>
</AddressSpace>
</Processor>
<Config>
<Option
Name=
"Part"
Val=
"xc7k160tfbg676-2"
/>
</Config>
<DRC>
<Rule
Name=
"RDADDRCHANGE"
Val=
"false"
/>
</DRC>
</MemInfoSimulation>
hdl/sim/spec7_ref_design/test.tcl
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12c440cd
force /spec7_wr_ref_top/reset_n_i 0,1 200 ns
force /spec7_wr_ref_top/uart_rxd_i 0
force /spec7_wr_ref_top/clk_125m_gtx_p_i 0, 1 4000 ps -rep 8000 ps
force /spec7_wr_ref_top/clk_125m_gtx_n_i 1, 0 4000 ps -rep 8000 ps
force /spec7_wr_ref_top/clk_125m_dmtd_p_i 0, 1 4001 ps -rep 8002 ps
force /spec7_wr_ref_top/clk_125m_dmtd_n_i 1, 0 4001 ps -rep 8002 ps
run 300 us
hdl/sim/spec7_ref_design/vlog.opt
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12c440cd
+incdir+../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src
+incdir+../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi
hdl/sim/spec7_ref_design/wave.tcl
0 → 100644
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12c440cd
onerror
{
resume
}
quietly WaveActivateNextPane
{}
0
add wave -noupdate /spec7_wr_ref_top/reset_n_i
add wave -noupdate /spec7_wr_ref_top/clk_125m_dmtd_p_i
add wave -noupdate /spec7_wr_ref_top/clk_125m_gtx_p_i
add wave -noupdate -divider BUFGMUX
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/clk_dmtd
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/clk_ref_62m5
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/clk_sys_62m5
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/pll_clk_select
add wave -noupdate /spec7_wr_ref_top/uart_rxd_i
add wave -noupdate /spec7_wr_ref_top/uart_txd_o
add wave -noupdate -divider LM32
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/LM32_CORE/rst_n_i
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/LM32_CORE/clk_sys_i
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/LM32_CORE/dwb_i
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/LM32_CORE/dwb_o
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/LM32_CORE/iwb_i
add wave -noupdate /spec7_wr_ref_top/cmp_xwrc_board_spec7/cmp_board_common/cmp_xwr_core/WRPC/LM32_CORE/iwb_o
TreeUpdate
[
SetDefaultTree
]
WaveRestoreCursors
{{
Cursor 1
}
{
0 ps
}
0
}
quietly wave cursor active 0
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ps
update
WaveRestoreZoom
{
0 ps
}
{
315 us
}
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