Commit 07ad4910 authored by kblantos's avatar kblantos Committed by Peter Jansweijer

.gitlab-ci.yml added to the project

parent af9cd38f
variables:
GIT_SUBMODULE_STRATEGY: normal
GIT_DEPTH: "1"
stages:
- build
SPEC7_REF_DESIGN build:
tags:
- vitis_vivado_2019.2
stage: build
script:
- /entrypoint.sh
- source ~/setup_vivado.sh
- git checkout spec7_golden
- git submodule init && git submodule update
- cd hdl/wr-cores && git submodule init && git submodule update
- cd ../../hdl/spec7_ref_design/syn
- source /opt/Xilinx/Vivado/2019.2/settings64.sh
- vivado -mode tcl -source ../../../sw/scripts/viv_do_all.tcl
artifacts:
when: always
paths:
- hdl/spec7_ref_design/syn/work/spec7_wr_ref_top.runs/impl_1/*.bit
- hdl/spec7_ref_design/syn/work/spec7_wr_ref_top.runs/impl_1/*.rpt
- hdl/spec7_ref_design/syn/work/spec7_wr_ref_top.runs/impl_1/*.csv
- dl/spec7_ref_design/syn/work/spec7_wr_ref_top.runs/synth_1/*.rpt
- hdl/spec7_ref_design/syn/work/spec7_wr_ref_top.runs/processing_system_pcie_xdma_0_0_synth_1/*.rpt
- hdl/spec7_ref_design/syn/work/spec7_wr_ref_top.runs/processing_system_pcie_processing_system7_0_0_synth_1/*.rpt
- hdl/spec7_ref_design/syn/work/spec7_wr_ref_top.runs/processing_system_pcie_smartconnect_0_0_synth_1/*.rpt
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