project_name=${_xil_proj_name_}
spec7_ddr_project_board_part=
spec7_ddr_project_compxlib.activehdl_compiled_library_dir=/home/spec7_boot/spec7_pcie/spec7_ddr/spec7_ddr.cache/compile_simlib/activehdl
spec7_ddr_project_compxlib.funcsim=1
spec7_ddr_project_compxlib.ies_compiled_library_dir=/home/spec7_boot/spec7_pcie/spec7_ddr/spec7_ddr.cache/compile_simlib/ies
spec7_ddr_project_compxlib.modelsim_compiled_library_dir=/home/spec7_boot/spec7_pcie/spec7_ddr/spec7_ddr.cache/compile_simlib/modelsim
spec7_ddr_project_compxlib.overwrite_libs=0
spec7_ddr_project_compxlib.questa_compiled_library_dir=/home/spec7_boot/spec7_pcie/spec7_ddr/spec7_ddr.cache/compile_simlib/questa
spec7_ddr_project_compxlib.riviera_compiled_library_dir=/home/spec7_boot/spec7_pcie/spec7_ddr/spec7_ddr.cache/compile_simlib/riviera
spec7_ddr_project_compxlib.timesim=1
spec7_ddr_project_compxlib.vcs_compiled_library_dir=/home/spec7_boot/spec7_pcie/spec7_ddr/spec7_ddr.cache/compile_simlib/vcs
spec7_ddr_project_compxlib.xsim_compiled_library_dir=
spec7_ddr_project_corecontainer.enable=0
spec7_ddr_project_default_lib=xil_defaultlib
spec7_ddr_project_enable_optional_runs_sta=0
spec7_ddr_project_enable_vhdl_2008=1
spec7_ddr_project_generate_ip_upgrade_log=1
spec7_ddr_project_ip_cache_permissions=read write
spec7_ddr_project_ip_interface_inference_priority=
spec7_ddr_project_ip_output_repo=/home/spec7_boot/spec7_pcie/spec7_ddr/spec7_ddr.cache/ip
spec7_ddr_project_is_readonly=0
spec7_ddr_project_legacy_ip_repo_paths=
spec7_ddr_project_mem.enable_memory_map_generation=1
spec7_ddr_project_part=xc7z030fbg676-1
spec7_ddr_project_platform.default_output_type=undefined
spec7_ddr_project_platform.design_intent.datacenter=undefined
spec7_ddr_project_platform.design_intent.embedded=undefined
spec7_ddr_project_platform.design_intent.external_host=undefined
spec7_ddr_project_platform.design_intent.server_managed=undefined
spec7_ddr_project_platform.rom.debug_type=0
spec7_ddr_project_platform.rom.prom_type=0
spec7_ddr_project_platform.slrconstraintmode=0
spec7_ddr_project_project_type=Default
spec7_ddr_project_pr_flow=0
spec7_ddr_project_sim.central_dir=/home/spec7_boot/spec7_pcie/spec7_ddr/spec7_ddr.ip_user_files
spec7_ddr_project_sim.ip.auto_export_scripts=1
spec7_ddr_project_sim.use_ip_compiled_libs=1
spec7_ddr_project_simulator_language=Mixed
spec7_ddr_project_source_mgmt_mode=All
spec7_ddr_project_target_language=VHDL
spec7_ddr_project_target_simulator=XSim
spec7_ddr_project_tool_flow=Vivado
spec7_ddr_project_xpm_libraries=
spec7_ddr_project_xsim.array_display_limit=1024
spec7_ddr_project_xsim.radix=hex
spec7_ddr_project_xsim.time_unit=ns
spec7_ddr_project_xsim.trace_limit=65536
sources_1_fileset_design_mode=RTL
sources_1_fileset_edif_extra_search_paths=
sources_1_fileset_elab_link_dcps=1
sources_1_fileset_elab_load_timing_constraints=1
sources_1_fileset_generic=
sources_1_fileset_include_dirs=
sources_1_fileset_lib_map_file=
sources_1_fileset_loop_count=1000
sources_1_fileset_name=sources_1
sources_1_fileset_top=
sources_1_fileset_verilog_define=
sources_1_fileset_verilog_uppercase=0
sources_1_fileset_verilog_version=verilog_2001
sources_1_fileset_vhdl_version=vhdl_2k
constrs_1_fileset_constrs_type=XDC
constrs_1_fileset_name=constrs_1
constrs_1_fileset_target_constrs_file=$PSRCDIR/
constrs_1_fileset_target_part=xc7z030fbg676-1
sim_1_fileset_32bit=0
sim_1_fileset_generic=
sim_1_fileset_include_dirs=
sim_1_fileset_incremental=1
sim_1_fileset_name=sim_1
sim_1_fileset_nl.cell=
sim_1_fileset_nl.incl_unisim_models=0
sim_1_fileset_nl.process_corner=slow
sim_1_fileset_nl.rename_top=
sim_1_fileset_nl.sdf_anno=1
sim_1_fileset_nl.write_all_overrides=0
sim_1_fileset_source_set=sources_1
sim_1_fileset_systemc_include_dirs=
sim_1_fileset_top=
sim_1_fileset_transport_int_delay=0
sim_1_fileset_transport_path_delay=0
sim_1_fileset_verilog_define=
sim_1_fileset_verilog_uppercase=0
sim_1_fileset_xelab.dll=0
sim_1_fileset_xsim.compile.tcl.pre=
sim_1_fileset_xsim.compile.xsc.more_options=
sim_1_fileset_xsim.compile.xvhdl.more_options=
sim_1_fileset_xsim.compile.xvhdl.nosort=1
sim_1_fileset_xsim.compile.xvhdl.relax=1
sim_1_fileset_xsim.compile.xvlog.more_options=
sim_1_fileset_xsim.compile.xvlog.nosort=1
sim_1_fileset_xsim.compile.xvlog.relax=1
sim_1_fileset_xsim.elaborate.debug_level=typical
sim_1_fileset_xsim.elaborate.load_glbl=1
sim_1_fileset_xsim.elaborate.mt_level=auto
sim_1_fileset_xsim.elaborate.rangecheck=0
sim_1_fileset_xsim.elaborate.relax=1
sim_1_fileset_xsim.elaborate.sdf_delay=sdfmax
sim_1_fileset_xsim.elaborate.snapshot=
sim_1_fileset_xsim.elaborate.xelab.more_options=
sim_1_fileset_xsim.elaborate.xsc.more_options=
sim_1_fileset_xsim.simulate.add_positional=0
sim_1_fileset_xsim.simulate.custom_tcl=
sim_1_fileset_xsim.simulate.log_all_signals=0
sim_1_fileset_xsim.simulate.no_quit=0
sim_1_fileset_xsim.simulate.runtime=1000ns
sim_1_fileset_xsim.simulate.saif=
sim_1_fileset_xsim.simulate.saif_all_signals=0
sim_1_fileset_xsim.simulate.saif_scope=
sim_1_fileset_xsim.simulate.tcl.post=
sim_1_fileset_xsim.simulate.wdb=
sim_1_fileset_xsim.simulate.xsim.more_options=
utils_1_fileset_name=utils_1
synth_1_run_constrset=constrs_1
synth_1_run_description=Vivado Synthesis Defaults
synth_1_run_flow=Vivado Synthesis 2019
synth_1_run_name=synth_1
synth_1_run_needs_refresh=0
synth_1_run_part=xc7z030fbg676-1
synth_1_run_srcset=sources_1
synth_1_run_auto_incremental_checkpoint=0
synth_1_run_incremental_checkpoint=
synth_1_run_rqs_files=
synth_1_run_incremental_checkpoint.more_options=
synth_1_run_include_in_archive=1
synth_1_run_gen_full_bitstream=1
synth_1_run_write_incremental_synth_checkpoint=0
synth_1_run_strategy=Vivado Synthesis Defaults
synth_1_run_steps.synth_design.tcl.pre=
synth_1_run_steps.synth_design.tcl.post=
synth_1_run_steps.synth_design.args.flatten_hierarchy=rebuilt
synth_1_run_steps.synth_design.args.gated_clock_conversion=off
synth_1_run_steps.synth_design.args.bufg=12
synth_1_run_steps.synth_design.args.fanout_limit=10000
synth_1_run_steps.synth_design.args.directive=Default
synth_1_run_steps.synth_design.args.retiming=0
synth_1_run_steps.synth_design.args.fsm_extraction=auto
synth_1_run_steps.synth_design.args.keep_equivalent_registers=0
synth_1_run_steps.synth_design.args.resource_sharing=auto
synth_1_run_steps.synth_design.args.control_set_opt_threshold=auto
synth_1_run_steps.synth_design.args.no_lc=0
synth_1_run_steps.synth_design.args.no_srlextract=0
synth_1_run_steps.synth_design.args.shreg_min_size=3
synth_1_run_steps.synth_design.args.max_bram=-1
synth_1_run_steps.synth_design.args.max_uram=-1
synth_1_run_steps.synth_design.args.max_dsp=-1
synth_1_run_steps.synth_design.args.max_bram_cascade_height=-1
synth_1_run_steps.synth_design.args.max_uram_cascade_height=-1
synth_1_run_steps.synth_design.args.cascade_dsp=auto
synth_1_run_steps.synth_design.args.assert=0
synth_1_run_steps.synth_design.args.more options=
impl_1_run_constrset=constrs_1
impl_1_run_description=Default settings for Implementation.
impl_1_run_flow=Vivado Implementation 2019
impl_1_run_name=impl_1
impl_1_run_needs_refresh=0
impl_1_run_part=xc7z030fbg676-1
impl_1_run_pr_configuration=
impl_1_run_srcset=sources_1
impl_1_run_auto_incremental_checkpoint=0
impl_1_run_incremental_checkpoint=
impl_1_run_rqs_files=
impl_1_run_incremental_checkpoint.more_options=
impl_1_run_include_in_archive=1
impl_1_run_gen_full_bitstream=1
impl_1_run_strategy=Vivado Implementation Defaults
impl_1_run_steps.init_design.tcl.pre=
impl_1_run_steps.init_design.tcl.post=
impl_1_run_steps.opt_design.is_enabled=1
impl_1_run_steps.opt_design.tcl.pre=
impl_1_run_steps.opt_design.tcl.post=
impl_1_run_steps.opt_design.args.verbose=0
impl_1_run_steps.opt_design.args.directive=Default
impl_1_run_steps.opt_design.args.more options=
impl_1_run_steps.power_opt_design.is_enabled=0
impl_1_run_steps.power_opt_design.tcl.pre=
impl_1_run_steps.power_opt_design.tcl.post=
impl_1_run_steps.power_opt_design.args.more options=
impl_1_run_steps.place_design.tcl.pre=
impl_1_run_steps.place_design.tcl.post=
impl_1_run_steps.place_design.args.directive=Default
impl_1_run_steps.place_design.args.more options=
impl_1_run_steps.post_place_power_opt_design.is_enabled=0
impl_1_run_steps.post_place_power_opt_design.tcl.pre=
impl_1_run_steps.post_place_power_opt_design.tcl.post=
impl_1_run_steps.post_place_power_opt_design.args.more options=
impl_1_run_steps.phys_opt_design.is_enabled=1
impl_1_run_steps.phys_opt_design.tcl.pre=
impl_1_run_steps.phys_opt_design.tcl.post=
impl_1_run_steps.phys_opt_design.args.directive=Default
impl_1_run_steps.phys_opt_design.args.more options=
impl_1_run_steps.route_design.tcl.pre=
impl_1_run_steps.route_design.tcl.post=
impl_1_run_steps.route_design.args.directive=Default
impl_1_run_steps.route_design.args.more options=
impl_1_run_steps.post_route_phys_opt_design.is_enabled=0
impl_1_run_steps.post_route_phys_opt_design.tcl.pre=
impl_1_run_steps.post_route_phys_opt_design.tcl.post=
impl_1_run_steps.post_route_phys_opt_design.args.directive=Default
impl_1_run_steps.post_route_phys_opt_design.args.more options=
impl_1_run_steps.write_bitstream.tcl.pre=
impl_1_run_steps.write_bitstream.tcl.post=
impl_1_run_steps.write_bitstream.args.raw_bitfile=0
impl_1_run_steps.write_bitstream.args.mask_file=0
impl_1_run_steps.write_bitstream.args.no_binary_bitfile=0
impl_1_run_steps.write_bitstream.args.bin_file=0
impl_1_run_steps.write_bitstream.args.readback_file=0
impl_1_run_steps.write_bitstream.args.logic_location_file=0
impl_1_run_steps.write_bitstream.args.verbose=0
impl_1_run_steps.write_bitstream.args.more options=
drc_1_gadget_active_reports=
drc_1_gadget_active_reports_invalid=
drc_1_gadget_active_run=0
drc_1_gadget_hide_unused_data=1
drc_1_gadget_incl_new_reports=0
drc_1_gadget_reports=impl_1#impl_1_route_report_drc_0
drc_1_gadget_run.step=route_design
drc_1_gadget_run.type=implementation
drc_1_gadget_statistics.critical_warning=1
drc_1_gadget_statistics.error=1
drc_1_gadget_statistics.info=1
drc_1_gadget_statistics.warning=1
drc_1_gadget_view.orientation=Horizontal
drc_1_gadget_view.type=Graph
methodology_1_gadget_active_reports=
methodology_1_gadget_active_reports_invalid=
methodology_1_gadget_active_run=0
methodology_1_gadget_hide_unused_data=1
methodology_1_gadget_incl_new_reports=0
methodology_1_gadget_reports=impl_1#impl_1_route_report_methodology_0
methodology_1_gadget_run.step=route_design
methodology_1_gadget_run.type=implementation
methodology_1_gadget_statistics.critical_warning=1
methodology_1_gadget_statistics.error=1
methodology_1_gadget_statistics.info=1
methodology_1_gadget_statistics.warning=1
methodology_1_gadget_view.orientation=Horizontal
methodology_1_gadget_view.type=Graph
power_1_gadget_active_reports=
power_1_gadget_active_reports_invalid=
power_1_gadget_active_run=0
power_1_gadget_hide_unused_data=1
power_1_gadget_incl_new_reports=0
power_1_gadget_reports=impl_1#impl_1_route_report_power_0
power_1_gadget_run.step=route_design
power_1_gadget_run.type=implementation
power_1_gadget_statistics.bram=1
power_1_gadget_statistics.clocks=1
power_1_gadget_statistics.dsp=1
power_1_gadget_statistics.gth=1
power_1_gadget_statistics.gtp=1
power_1_gadget_statistics.gtx=1
power_1_gadget_statistics.gtz=1
power_1_gadget_statistics.io=1
power_1_gadget_statistics.logic=1
power_1_gadget_statistics.mmcm=1
power_1_gadget_statistics.pcie=1
power_1_gadget_statistics.phaser=1
power_1_gadget_statistics.pll=1
power_1_gadget_statistics.pl_static=1
power_1_gadget_statistics.ps7=1
power_1_gadget_statistics.ps=1
power_1_gadget_statistics.ps_static=1
power_1_gadget_statistics.signals=1
power_1_gadget_statistics.total_power=1
power_1_gadget_statistics.transceiver=1
power_1_gadget_statistics.xadc=1
power_1_gadget_view.orientation=Horizontal
power_1_gadget_view.type=Graph
timing_1_gadget_active_reports=
timing_1_gadget_active_reports_invalid=
timing_1_gadget_active_run=0
timing_1_gadget_hide_unused_data=1
timing_1_gadget_incl_new_reports=0
timing_1_gadget_reports=impl_1#impl_1_route_report_timing_summary_0
timing_1_gadget_run.step=route_design
timing_1_gadget_run.type=implementation
timing_1_gadget_statistics.ths=1
timing_1_gadget_statistics.tns=1
timing_1_gadget_statistics.tpws=1
timing_1_gadget_statistics.whs=1
timing_1_gadget_statistics.wns=1
timing_1_gadget_view.orientation=Horizontal
timing_1_gadget_view.type=Table
utilization_1_gadget_active_reports=
utilization_1_gadget_active_reports_invalid=
utilization_1_gadget_active_run=0
utilization_1_gadget_hide_unused_data=1
utilization_1_gadget_incl_new_reports=0
utilization_1_gadget_reports=synth_1#synth_1_synth_report_utilization_0
utilization_1_gadget_run.step=synth_design
utilization_1_gadget_run.type=synthesis
utilization_1_gadget_statistics.bram=1
utilization_1_gadget_statistics.bufg=1
utilization_1_gadget_statistics.dsp=1
utilization_1_gadget_statistics.ff=1
utilization_1_gadget_statistics.gt=1
utilization_1_gadget_statistics.io=1
utilization_1_gadget_statistics.lut=1
utilization_1_gadget_statistics.lutram=1
utilization_1_gadget_statistics.mmcm=1
utilization_1_gadget_statistics.pcie=1
utilization_1_gadget_statistics.pll=1
utilization_1_gadget_statistics.uram=1
utilization_1_gadget_view.orientation=Horizontal
utilization_1_gadget_view.type=Graph
utilization_2_gadget_active_reports=
utilization_2_gadget_active_reports_invalid=
utilization_2_gadget_active_run=0
utilization_2_gadget_hide_unused_data=1
utilization_2_gadget_incl_new_reports=0
utilization_2_gadget_reports=impl_1#impl_1_place_report_utilization_0
utilization_2_gadget_run.step=place_design
utilization_2_gadget_run.type=implementation
utilization_2_gadget_statistics.bram=1
utilization_2_gadget_statistics.bufg=1
utilization_2_gadget_statistics.dsp=1
utilization_2_gadget_statistics.ff=1
utilization_2_gadget_statistics.gt=1
utilization_2_gadget_statistics.io=1
utilization_2_gadget_statistics.lut=1
utilization_2_gadget_statistics.lutram=1
utilization_2_gadget_statistics.mmcm=1
utilization_2_gadget_statistics.pcie=1
utilization_2_gadget_statistics.pll=1
utilization_2_gadget_statistics.uram=1
utilization_2_gadget_view.orientation=Horizontal
utilization_2_gadget_view.type=Graph
