-- Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2019.2 (lin64) Build 2708876 Wed Nov  6 21:39:14 MST 2019
-- Date        : Sat Oct  3 15:01:45 2020
-- Host        : pcbe16482.cern.ch running 64-bit CentOS Linux release 7.8.2003 (Core)
-- Command     : write_vhdl -force -mode funcsim
--               /home/spec7_trial/spec7_trial.srcs/sources_1/bd/spec7/ip/spec7_pcie_7x_0/spec7_pcie_7x_0_sim_netlist.vhdl
-- Design      : spec7_pcie_7x_0
-- Purpose     : This VHDL netlist is a functional simulation representation of the design and should not be modified or
--               synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device      : xc7z030fbg676-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_rx_null_gen is
  port (
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \reg_tkeep[7]_i_7_0\ : out STD_LOGIC;
    \reg_pkt_len_counter_reg[3]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    null_mux_sel_reg : out STD_LOGIC;
    null_mux_sel_reg_0 : out STD_LOGIC;
    null_mux_sel_reg_1 : out STD_LOGIC;
    in0 : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \reg_pkt_len_counter_reg[9]_0\ : in STD_LOGIC_VECTOR ( 4 downto 0 );
    \reg_pkt_len_counter_reg[0]_0\ : in STD_LOGIC;
    CLK : in STD_LOGIC;
    null_mux_sel : in STD_LOGIC;
    \m_axis_rx_tuser_xhdl1_reg[19]\ : in STD_LOGIC;
    m_axis_rx_tready : in STD_LOGIC;
    null_mux_sel_reg_2 : in STD_LOGIC;
    cur_state_reg_0 : in STD_LOGIC;
    m_axis_rx_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
    \m_axis_rx_tuser_xhdl1_reg[21]\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_rx_null_gen : entity is "spec7_pcie_7x_0_axi_basic_rx_null_gen";
end spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_rx_null_gen;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_rx_null_gen is
  signal cur_state : STD_LOGIC;
  signal \minusOp__0_carry__0_i_1_n_0\ : STD_LOGIC;
  signal \minusOp__0_carry__0_i_2_n_0\ : STD_LOGIC;
  signal \minusOp__0_carry__0_i_3_n_0\ : STD_LOGIC;
  signal \minusOp__0_carry__0_i_4_n_0\ : STD_LOGIC;
  signal \minusOp__0_carry__0_n_0\ : STD_LOGIC;
  signal \minusOp__0_carry__0_n_1\ : STD_LOGIC;
  signal \minusOp__0_carry__0_n_2\ : STD_LOGIC;
  signal \minusOp__0_carry__0_n_3\ : STD_LOGIC;
  signal \minusOp__0_carry__1_i_1_n_0\ : STD_LOGIC;
  signal \minusOp__0_carry__1_i_2_n_0\ : STD_LOGIC;
  signal \minusOp__0_carry__1_i_3_n_0\ : STD_LOGIC;
  signal \minusOp__0_carry__1_n_2\ : STD_LOGIC;
  signal \minusOp__0_carry__1_n_3\ : STD_LOGIC;
  signal \minusOp__0_carry_i_1_n_0\ : STD_LOGIC;
  signal \minusOp__0_carry_i_2_n_0\ : STD_LOGIC;
  signal \minusOp__0_carry_i_3_n_0\ : STD_LOGIC;
  signal \minusOp__0_carry_i_4_n_0\ : STD_LOGIC;
  signal \minusOp__0_carry_i_5_n_0\ : STD_LOGIC;
  signal \minusOp__0_carry_n_0\ : STD_LOGIC;
  signal \minusOp__0_carry_n_1\ : STD_LOGIC;
  signal \minusOp__0_carry_n_2\ : STD_LOGIC;
  signal \minusOp__0_carry_n_3\ : STD_LOGIC;
  signal new_pkt_len : STD_LOGIC_VECTOR ( 11 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of new_pkt_len : signal is "true";
  signal new_pkt_len_1 : STD_LOGIC_VECTOR ( 4 downto 0 );
  attribute RTL_KEEP of new_pkt_len_1 : signal is "true";
  signal next_state : STD_LOGIC;
  signal pkt_len_counter : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \pkt_len_counter__0\ : STD_LOGIC_VECTOR ( 11 downto 1 );
  signal reg_pkt_len_counter : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \reg_pkt_len_counter[10]_i_1_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[11]_i_1_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[11]_i_2_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[11]_i_3_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[11]_i_4_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[2]_i_1_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[3]_i_1_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[4]_i_1_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[5]_i_1_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[6]_i_1_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[7]_i_1_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[8]_i_1_n_0\ : STD_LOGIC;
  signal \reg_pkt_len_counter[9]_i_1_n_0\ : STD_LOGIC;
  signal \^reg_pkt_len_counter_reg[3]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \reg_tkeep[7]_i_3_n_0\ : STD_LOGIC;
  signal \reg_tkeep[7]_i_4_n_0\ : STD_LOGIC;
  signal \reg_tkeep[7]_i_5_n_0\ : STD_LOGIC;
  signal \reg_tkeep[7]_i_6_n_0\ : STD_LOGIC;
  signal \^reg_tkeep[7]_i_7_0\ : STD_LOGIC;
  signal \reg_tkeep[7]_i_7_n_0\ : STD_LOGIC;
  signal \NLW_minusOp__0_carry__1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_minusOp__0_carry__1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
  new_pkt_len(9 downto 5) <= \reg_pkt_len_counter_reg[9]_0\(4 downto 0);
  new_pkt_len_1(4 downto 0) <= in0(4 downto 0);
  \reg_pkt_len_counter_reg[3]_0\(0) <= \^reg_pkt_len_counter_reg[3]_0\(0);
  \reg_tkeep[7]_i_7_0\ <= \^reg_tkeep[7]_i_7_0\;
cur_state_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAAAAEA"
    )
        port map (
      I0 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I1 => m_axis_rx_tready,
      I2 => cur_state_reg_0,
      I3 => cur_state,
      I4 => m_axis_rx_tuser(0),
      O => next_state
    );
cur_state_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => next_state,
      Q => cur_state,
      R => \reg_pkt_len_counter_reg[0]_0\
    );
i_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => new_pkt_len(11)
    );
i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => '0',
      O => new_pkt_len(10)
    );
\m_axis_rx_tuser_xhdl1[19]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5555555500004000"
    )
        port map (
      I0 => \reg_pkt_len_counter_reg[0]_0\,
      I1 => \^reg_tkeep[7]_i_7_0\,
      I2 => null_mux_sel,
      I3 => \^reg_pkt_len_counter_reg[3]_0\(0),
      I4 => pkt_len_counter(0),
      I5 => \m_axis_rx_tuser_xhdl1_reg[19]\,
      O => D(0)
    );
\m_axis_rx_tuser_xhdl1[21]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000F0F8F8F0"
    )
        port map (
      I0 => \^reg_tkeep[7]_i_7_0\,
      I1 => null_mux_sel,
      I2 => \m_axis_rx_tuser_xhdl1_reg[21]\,
      I3 => \^reg_pkt_len_counter_reg[3]_0\(0),
      I4 => pkt_len_counter(0),
      I5 => \reg_pkt_len_counter_reg[0]_0\,
      O => D(1)
    );
\minusOp__0_carry\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \minusOp__0_carry_n_0\,
      CO(2) => \minusOp__0_carry_n_1\,
      CO(1) => \minusOp__0_carry_n_2\,
      CO(0) => \minusOp__0_carry_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => reg_pkt_len_counter(3 downto 2),
      DI(1) => \minusOp__0_carry_i_1_n_0\,
      DI(0) => '0',
      O(3 downto 0) => \pkt_len_counter__0\(4 downto 1),
      S(3) => \minusOp__0_carry_i_2_n_0\,
      S(2) => \minusOp__0_carry_i_3_n_0\,
      S(1) => \minusOp__0_carry_i_4_n_0\,
      S(0) => \minusOp__0_carry_i_5_n_0\
    );
\minusOp__0_carry__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \minusOp__0_carry_n_0\,
      CO(3) => \minusOp__0_carry__0_n_0\,
      CO(2) => \minusOp__0_carry__0_n_1\,
      CO(1) => \minusOp__0_carry__0_n_2\,
      CO(0) => \minusOp__0_carry__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => reg_pkt_len_counter(7 downto 4),
      O(3 downto 0) => \pkt_len_counter__0\(8 downto 5),
      S(3) => \minusOp__0_carry__0_i_1_n_0\,
      S(2) => \minusOp__0_carry__0_i_2_n_0\,
      S(1) => \minusOp__0_carry__0_i_3_n_0\,
      S(0) => \minusOp__0_carry__0_i_4_n_0\
    );
\minusOp__0_carry__0_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => reg_pkt_len_counter(7),
      I1 => reg_pkt_len_counter(8),
      O => \minusOp__0_carry__0_i_1_n_0\
    );
\minusOp__0_carry__0_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => reg_pkt_len_counter(6),
      I1 => reg_pkt_len_counter(7),
      O => \minusOp__0_carry__0_i_2_n_0\
    );
\minusOp__0_carry__0_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => reg_pkt_len_counter(5),
      I1 => reg_pkt_len_counter(6),
      O => \minusOp__0_carry__0_i_3_n_0\
    );
\minusOp__0_carry__0_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => reg_pkt_len_counter(4),
      I1 => reg_pkt_len_counter(5),
      O => \minusOp__0_carry__0_i_4_n_0\
    );
\minusOp__0_carry__1\: unisim.vcomponents.CARRY4
     port map (
      CI => \minusOp__0_carry__0_n_0\,
      CO(3 downto 2) => \NLW_minusOp__0_carry__1_CO_UNCONNECTED\(3 downto 2),
      CO(1) => \minusOp__0_carry__1_n_2\,
      CO(0) => \minusOp__0_carry__1_n_3\,
      CYINIT => '0',
      DI(3 downto 2) => B"00",
      DI(1 downto 0) => reg_pkt_len_counter(9 downto 8),
      O(3) => \NLW_minusOp__0_carry__1_O_UNCONNECTED\(3),
      O(2 downto 0) => \pkt_len_counter__0\(11 downto 9),
      S(3) => '0',
      S(2) => \minusOp__0_carry__1_i_1_n_0\,
      S(1) => \minusOp__0_carry__1_i_2_n_0\,
      S(0) => \minusOp__0_carry__1_i_3_n_0\
    );
\minusOp__0_carry__1_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => reg_pkt_len_counter(10),
      I1 => reg_pkt_len_counter(11),
      O => \minusOp__0_carry__1_i_1_n_0\
    );
\minusOp__0_carry__1_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => reg_pkt_len_counter(9),
      I1 => reg_pkt_len_counter(10),
      O => \minusOp__0_carry__1_i_2_n_0\
    );
\minusOp__0_carry__1_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => reg_pkt_len_counter(8),
      I1 => reg_pkt_len_counter(9),
      O => \minusOp__0_carry__1_i_3_n_0\
    );
\minusOp__0_carry_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => reg_pkt_len_counter(1),
      I1 => m_axis_rx_tready,
      O => \minusOp__0_carry_i_1_n_0\
    );
\minusOp__0_carry_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => reg_pkt_len_counter(3),
      I1 => reg_pkt_len_counter(4),
      O => \minusOp__0_carry_i_2_n_0\
    );
\minusOp__0_carry_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"9"
    )
        port map (
      I0 => reg_pkt_len_counter(2),
      I1 => reg_pkt_len_counter(3),
      O => \minusOp__0_carry_i_3_n_0\
    );
\minusOp__0_carry_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"D2"
    )
        port map (
      I0 => m_axis_rx_tready,
      I1 => reg_pkt_len_counter(1),
      I2 => reg_pkt_len_counter(2),
      O => \minusOp__0_carry_i_4_n_0\
    );
\minusOp__0_carry_i_5\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => reg_pkt_len_counter(1),
      I1 => m_axis_rx_tready,
      O => \minusOp__0_carry_i_5_n_0\
    );
new_pkt_len_1_inst: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => new_pkt_len_1(4),
      O => new_pkt_len(4)
    );
\new_pkt_len_1_inst__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => new_pkt_len_1(3),
      O => new_pkt_len(3)
    );
\new_pkt_len_1_inst__1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => new_pkt_len_1(2),
      O => new_pkt_len(2)
    );
\new_pkt_len_1_inst__2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => new_pkt_len_1(1),
      O => new_pkt_len(1)
    );
\new_pkt_len_1_inst__3\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => new_pkt_len_1(0),
      O => new_pkt_len(0)
    );
null_mux_sel_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000D5FFFFFF"
    )
        port map (
      I0 => \^reg_tkeep[7]_i_7_0\,
      I1 => pkt_len_counter(0),
      I2 => \^reg_pkt_len_counter_reg[3]_0\(0),
      I3 => null_mux_sel,
      I4 => m_axis_rx_tready,
      I5 => null_mux_sel_reg_2,
      O => null_mux_sel_reg
    );
\reg_pkt_len_counter[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => reg_pkt_len_counter(0),
      I1 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I2 => new_pkt_len(0),
      O => pkt_len_counter(0)
    );
\reg_pkt_len_counter[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E2"
    )
        port map (
      I0 => new_pkt_len(10),
      I1 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I2 => \pkt_len_counter__0\(10),
      O => \reg_pkt_len_counter[10]_i_1_n_0\
    );
\reg_pkt_len_counter[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \pkt_len_counter__0\(11),
      I1 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I2 => new_pkt_len(11),
      O => \reg_pkt_len_counter[11]_i_1_n_0\
    );
\reg_pkt_len_counter[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAA8AAAAAAAA"
    )
        port map (
      I0 => cur_state,
      I1 => reg_pkt_len_counter(4),
      I2 => reg_pkt_len_counter(6),
      I3 => reg_pkt_len_counter(7),
      I4 => \reg_pkt_len_counter[11]_i_3_n_0\,
      I5 => \reg_pkt_len_counter[11]_i_4_n_0\,
      O => \reg_pkt_len_counter[11]_i_2_n_0\
    );
\reg_pkt_len_counter[11]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => reg_pkt_len_counter(8),
      I1 => reg_pkt_len_counter(5),
      I2 => reg_pkt_len_counter(9),
      I3 => reg_pkt_len_counter(2),
      O => \reg_pkt_len_counter[11]_i_3_n_0\
    );
\reg_pkt_len_counter[11]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000700"
    )
        port map (
      I0 => reg_pkt_len_counter(0),
      I1 => reg_pkt_len_counter(1),
      I2 => reg_pkt_len_counter(3),
      I3 => m_axis_rx_tready,
      I4 => reg_pkt_len_counter(10),
      I5 => reg_pkt_len_counter(11),
      O => \reg_pkt_len_counter[11]_i_4_n_0\
    );
\reg_pkt_len_counter[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \pkt_len_counter__0\(1),
      I1 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I2 => new_pkt_len(1),
      O => \^reg_pkt_len_counter_reg[3]_0\(0)
    );
\reg_pkt_len_counter[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \pkt_len_counter__0\(2),
      I1 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I2 => new_pkt_len(2),
      O => \reg_pkt_len_counter[2]_i_1_n_0\
    );
\reg_pkt_len_counter[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \pkt_len_counter__0\(3),
      I1 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I2 => new_pkt_len(3),
      O => \reg_pkt_len_counter[3]_i_1_n_0\
    );
\reg_pkt_len_counter[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \pkt_len_counter__0\(4),
      I1 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I2 => new_pkt_len(4),
      O => \reg_pkt_len_counter[4]_i_1_n_0\
    );
\reg_pkt_len_counter[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \pkt_len_counter__0\(5),
      I1 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I2 => new_pkt_len(5),
      O => \reg_pkt_len_counter[5]_i_1_n_0\
    );
\reg_pkt_len_counter[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \pkt_len_counter__0\(6),
      I1 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I2 => new_pkt_len(6),
      O => \reg_pkt_len_counter[6]_i_1_n_0\
    );
\reg_pkt_len_counter[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \pkt_len_counter__0\(7),
      I1 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I2 => new_pkt_len(7),
      O => \reg_pkt_len_counter[7]_i_1_n_0\
    );
\reg_pkt_len_counter[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \pkt_len_counter__0\(8),
      I1 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I2 => new_pkt_len(8),
      O => \reg_pkt_len_counter[8]_i_1_n_0\
    );
\reg_pkt_len_counter[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => \pkt_len_counter__0\(9),
      I1 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I2 => new_pkt_len(9),
      O => \reg_pkt_len_counter[9]_i_1_n_0\
    );
\reg_pkt_len_counter_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => pkt_len_counter(0),
      Q => reg_pkt_len_counter(0),
      R => \reg_pkt_len_counter_reg[0]_0\
    );
\reg_pkt_len_counter_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \reg_pkt_len_counter[10]_i_1_n_0\,
      Q => reg_pkt_len_counter(10),
      R => \reg_pkt_len_counter_reg[0]_0\
    );
\reg_pkt_len_counter_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \reg_pkt_len_counter[11]_i_1_n_0\,
      Q => reg_pkt_len_counter(11),
      R => \reg_pkt_len_counter_reg[0]_0\
    );
\reg_pkt_len_counter_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \^reg_pkt_len_counter_reg[3]_0\(0),
      Q => reg_pkt_len_counter(1),
      R => \reg_pkt_len_counter_reg[0]_0\
    );
\reg_pkt_len_counter_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \reg_pkt_len_counter[2]_i_1_n_0\,
      Q => reg_pkt_len_counter(2),
      R => \reg_pkt_len_counter_reg[0]_0\
    );
\reg_pkt_len_counter_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \reg_pkt_len_counter[3]_i_1_n_0\,
      Q => reg_pkt_len_counter(3),
      R => \reg_pkt_len_counter_reg[0]_0\
    );
\reg_pkt_len_counter_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \reg_pkt_len_counter[4]_i_1_n_0\,
      Q => reg_pkt_len_counter(4),
      R => \reg_pkt_len_counter_reg[0]_0\
    );
\reg_pkt_len_counter_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \reg_pkt_len_counter[5]_i_1_n_0\,
      Q => reg_pkt_len_counter(5),
      R => \reg_pkt_len_counter_reg[0]_0\
    );
\reg_pkt_len_counter_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \reg_pkt_len_counter[6]_i_1_n_0\,
      Q => reg_pkt_len_counter(6),
      R => \reg_pkt_len_counter_reg[0]_0\
    );
\reg_pkt_len_counter_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \reg_pkt_len_counter[7]_i_1_n_0\,
      Q => reg_pkt_len_counter(7),
      R => \reg_pkt_len_counter_reg[0]_0\
    );
\reg_pkt_len_counter_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \reg_pkt_len_counter[8]_i_1_n_0\,
      Q => reg_pkt_len_counter(8),
      R => \reg_pkt_len_counter_reg[0]_0\
    );
\reg_pkt_len_counter_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \reg_pkt_len_counter[9]_i_1_n_0\,
      Q => reg_pkt_len_counter(9),
      R => \reg_pkt_len_counter_reg[0]_0\
    );
\reg_tkeep[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000004"
    )
        port map (
      I0 => \reg_pkt_len_counter[11]_i_1_n_0\,
      I1 => \reg_tkeep[7]_i_3_n_0\,
      I2 => \reg_tkeep[7]_i_4_n_0\,
      I3 => \reg_tkeep[7]_i_5_n_0\,
      I4 => \reg_tkeep[7]_i_6_n_0\,
      I5 => \reg_tkeep[7]_i_7_n_0\,
      O => \^reg_tkeep[7]_i_7_0\
    );
\reg_tkeep[7]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"47"
    )
        port map (
      I0 => \pkt_len_counter__0\(10),
      I1 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I2 => new_pkt_len(10),
      O => \reg_tkeep[7]_i_3_n_0\
    );
\reg_tkeep[7]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFACCFA"
    )
        port map (
      I0 => new_pkt_len(2),
      I1 => \pkt_len_counter__0\(2),
      I2 => new_pkt_len(3),
      I3 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I4 => \pkt_len_counter__0\(3),
      O => \reg_tkeep[7]_i_4_n_0\
    );
\reg_tkeep[7]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFACCFA"
    )
        port map (
      I0 => new_pkt_len(4),
      I1 => \pkt_len_counter__0\(4),
      I2 => new_pkt_len(5),
      I3 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I4 => \pkt_len_counter__0\(5),
      O => \reg_tkeep[7]_i_5_n_0\
    );
\reg_tkeep[7]_i_6\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFACCFA"
    )
        port map (
      I0 => new_pkt_len(9),
      I1 => \pkt_len_counter__0\(9),
      I2 => new_pkt_len(8),
      I3 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I4 => \pkt_len_counter__0\(8),
      O => \reg_tkeep[7]_i_6_n_0\
    );
\reg_tkeep[7]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFACCFA"
    )
        port map (
      I0 => new_pkt_len(7),
      I1 => \pkt_len_counter__0\(7),
      I2 => new_pkt_len(6),
      I3 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I4 => \pkt_len_counter__0\(6),
      O => \reg_tkeep[7]_i_7_n_0\
    );
reg_tlast_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF2A00"
    )
        port map (
      I0 => null_mux_sel,
      I1 => \^reg_pkt_len_counter_reg[3]_0\(0),
      I2 => pkt_len_counter(0),
      I3 => \^reg_tkeep[7]_i_7_0\,
      I4 => \m_axis_rx_tuser_xhdl1_reg[21]\,
      O => null_mux_sel_reg_0
    );
trn_rdst_rdy_xhdl4_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DFD55F55D5D55555"
    )
        port map (
      I0 => null_mux_sel,
      I1 => \pkt_len_counter__0\(1),
      I2 => \reg_pkt_len_counter[11]_i_2_n_0\,
      I3 => new_pkt_len(1),
      I4 => reg_pkt_len_counter(0),
      I5 => new_pkt_len(0),
      O => null_mux_sel_reg_1
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_rx_pipeline is
  port (
    trn_rsrc_dsc_d : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axis_rx_tvalid_xhdl2_reg_0 : out STD_LOGIC;
    m_axis_rx_tlast : out STD_LOGIC;
    null_mux_sel : out STD_LOGIC;
    trn_in_packet : out STD_LOGIC;
    reg_dsc_detect_reg_0 : out STD_LOGIC;
    user_reset_out_reg : out STD_LOGIC;
    data_prev_reg_0 : out STD_LOGIC;
    data_prev_reg_1 : out STD_LOGIC;
    m_axis_rx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_rx_tkeep : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axis_rx_tuser : out STD_LOGIC_VECTOR ( 12 downto 0 );
    in0 : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \m_axis_rx_tdata_xhdl0_reg[30]_0\ : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \trn_rbar_hit_prev_reg[0]_0\ : in STD_LOGIC;
    CLK : in STD_LOGIC;
    trn_rsrc_dsc : in STD_LOGIC;
    rsrc_rdy_filtered6_out : in STD_LOGIC;
    trn_rrem : in STD_LOGIC_VECTOR ( 0 to 0 );
    trn_reof : in STD_LOGIC;
    reg_tlast_reg_0 : in STD_LOGIC;
    trn_rsrc_dsc_prev0 : in STD_LOGIC;
    trn_rsof : in STD_LOGIC;
    trn_recrc_err : in STD_LOGIC;
    trn_rerrfwd : in STD_LOGIC;
    null_mux_sel_reg_0 : in STD_LOGIC;
    trn_in_packet_reg_0 : in STD_LOGIC;
    m_axis_rx_tready : in STD_LOGIC;
    dsc_detect : in STD_LOGIC;
    trn_rdst_rdy_xhdl4_reg_0 : in STD_LOGIC;
    trn_rdst_rdy_xhdl4_reg_1 : in STD_LOGIC;
    \reg_tkeep_reg[7]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
    D : in STD_LOGIC_VECTOR ( 1 downto 0 );
    trn_rd : in STD_LOGIC_VECTOR ( 63 downto 0 );
    trn_rbar_hit : in STD_LOGIC_VECTOR ( 6 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_rx_pipeline : entity is "spec7_pcie_7x_0_axi_basic_rx_pipeline";
end spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_rx_pipeline;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_rx_pipeline is
  signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal data_hold : STD_LOGIC;
  signal data_prev : STD_LOGIC;
  signal is_eof_prev : STD_LOGIC_VECTOR ( 4 downto 2 );
  signal \^m_axis_rx_tdata\ : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\ : STD_LOGIC;
  signal m_axis_rx_tuser_xhdl1 : STD_LOGIC_VECTOR ( 18 downto 0 );
  signal \m_axis_rx_tuser_xhdl1[14]_i_2_n_0\ : STD_LOGIC;
  signal \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\ : STD_LOGIC;
  signal m_axis_rx_tvalid_xhdl2_i_1_n_0 : STD_LOGIC;
  signal \^m_axis_rx_tvalid_xhdl2_reg_0\ : STD_LOGIC;
  signal new_pkt_len_1_inferred_i_6_n_0 : STD_LOGIC;
  signal \^null_mux_sel\ : STD_LOGIC;
  signal p_1_in : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal reg_dsc_detect_i_1_n_0 : STD_LOGIC;
  signal \^reg_dsc_detect_reg_0\ : STD_LOGIC;
  signal \reg_tkeep[7]_i_1_n_0\ : STD_LOGIC;
  signal trn_rbar_hit_prev : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal trn_rd_prev : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal trn_rdst_rdy_xhdl4_i_1_n_0 : STD_LOGIC;
  signal trn_rdst_rdy_xhdl4_i_2_n_0 : STD_LOGIC;
  signal trn_recrc_err_prev : STD_LOGIC;
  signal trn_rerrfwd_prev : STD_LOGIC;
  signal trn_rsof_prev : STD_LOGIC;
  signal trn_rsrc_dsc_prev : STD_LOGIC;
  signal trn_rsrc_rdy_prev : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[0]_i_1\ : label is "soft_lutpair113";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[10]_i_1\ : label is "soft_lutpair117";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[11]_i_1\ : label is "soft_lutpair115";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[12]_i_1\ : label is "soft_lutpair111";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[13]_i_1\ : label is "soft_lutpair110";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[14]_i_1\ : label is "soft_lutpair120";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[15]_i_1\ : label is "soft_lutpair112";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[16]_i_1\ : label is "soft_lutpair109";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[17]_i_1\ : label is "soft_lutpair105";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[18]_i_1\ : label is "soft_lutpair103";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[19]_i_1\ : label is "soft_lutpair117";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[1]_i_1\ : label is "soft_lutpair120";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[20]_i_1\ : label is "soft_lutpair114";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[21]_i_1\ : label is "soft_lutpair108";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[22]_i_1\ : label is "soft_lutpair116";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[23]_i_1\ : label is "soft_lutpair118";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[24]_i_1\ : label is "soft_lutpair112";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[25]_i_1\ : label is "soft_lutpair102";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[26]_i_1\ : label is "soft_lutpair100";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[27]_i_1\ : label is "soft_lutpair103";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[28]_i_1\ : label is "soft_lutpair107";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[29]_i_1\ : label is "soft_lutpair100";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[2]_i_1\ : label is "soft_lutpair113";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[30]_i_1\ : label is "soft_lutpair99";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[31]_i_1\ : label is "soft_lutpair93";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[32]_i_1\ : label is "soft_lutpair97";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[33]_i_1\ : label is "soft_lutpair89";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[34]_i_1\ : label is "soft_lutpair97";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[35]_i_1\ : label is "soft_lutpair90";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[36]_i_1\ : label is "soft_lutpair98";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[37]_i_1\ : label is "soft_lutpair91";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[38]_i_1\ : label is "soft_lutpair96";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[39]_i_1\ : label is "soft_lutpair91";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[3]_i_1\ : label is "soft_lutpair119";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[40]_i_1\ : label is "soft_lutpair94";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[41]_i_1\ : label is "soft_lutpair89";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[42]_i_1\ : label is "soft_lutpair95";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[43]_i_1\ : label is "soft_lutpair90";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[44]_i_1\ : label is "soft_lutpair99";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[45]_i_1\ : label is "soft_lutpair98";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[46]_i_1\ : label is "soft_lutpair94";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[47]_i_1\ : label is "soft_lutpair102";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[48]_i_1\ : label is "soft_lutpair93";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[49]_i_1\ : label is "soft_lutpair106";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[4]_i_1\ : label is "soft_lutpair119";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[50]_i_1\ : label is "soft_lutpair104";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[51]_i_1\ : label is "soft_lutpair101";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[52]_i_1\ : label is "soft_lutpair92";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[53]_i_1\ : label is "soft_lutpair95";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[54]_i_1\ : label is "soft_lutpair96";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[55]_i_1\ : label is "soft_lutpair92";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[56]_i_1\ : label is "soft_lutpair110";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[57]_i_1\ : label is "soft_lutpair107";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[58]_i_1\ : label is "soft_lutpair109";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[59]_i_1\ : label is "soft_lutpair101";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[5]_i_1\ : label is "soft_lutpair108";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[60]_i_1\ : label is "soft_lutpair104";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[61]_i_1\ : label is "soft_lutpair114";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[62]_i_1\ : label is "soft_lutpair105";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[63]_i_2\ : label is "soft_lutpair118";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[6]_i_1\ : label is "soft_lutpair106";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[7]_i_1\ : label is "soft_lutpair116";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[8]_i_1\ : label is "soft_lutpair115";
  attribute SOFT_HLUTNM of \m_axis_rx_tdata_xhdl0[9]_i_1\ : label is "soft_lutpair111";
  attribute SOFT_HLUTNM of \m_axis_rx_tuser_xhdl1[14]_i_2\ : label is "soft_lutpair85";
  attribute SOFT_HLUTNM of \m_axis_rx_tuser_xhdl1[18]_i_1\ : label is "soft_lutpair86";
  attribute SOFT_HLUTNM of \m_axis_rx_tuser_xhdl1[3]_i_1\ : label is "soft_lutpair86";
  attribute SOFT_HLUTNM of \m_axis_rx_tuser_xhdl1[6]_i_1\ : label is "soft_lutpair85";
  attribute SOFT_HLUTNM of new_pkt_len_1_inferred_i_1 : label is "soft_lutpair88";
  attribute SOFT_HLUTNM of new_pkt_len_1_inferred_i_2 : label is "soft_lutpair88";
  attribute SOFT_HLUTNM of new_pkt_len_1_inferred_i_4 : label is "soft_lutpair87";
  attribute SOFT_HLUTNM of new_pkt_len_1_inferred_i_5 : label is "soft_lutpair87";
  attribute SOFT_HLUTNM of new_pkt_len_inferred_i_2 : label is "soft_lutpair123";
  attribute SOFT_HLUTNM of new_pkt_len_inferred_i_3 : label is "soft_lutpair123";
  attribute SOFT_HLUTNM of new_pkt_len_inferred_i_4 : label is "soft_lutpair122";
  attribute SOFT_HLUTNM of new_pkt_len_inferred_i_5 : label is "soft_lutpair122";
  attribute SOFT_HLUTNM of reg_dsc_detect_i_1 : label is "soft_lutpair121";
  attribute SOFT_HLUTNM of trn_rdst_rdy_xhdl4_i_2 : label is "soft_lutpair121";
begin
  E(0) <= \^e\(0);
  m_axis_rx_tdata(63 downto 0) <= \^m_axis_rx_tdata\(63 downto 0);
  m_axis_rx_tvalid_xhdl2_reg_0 <= \^m_axis_rx_tvalid_xhdl2_reg_0\;
  null_mux_sel <= \^null_mux_sel\;
  reg_dsc_detect_reg_0 <= \^reg_dsc_detect_reg_0\;
data_prev_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \^m_axis_rx_tvalid_xhdl2_reg_0\,
      I1 => m_axis_rx_tready,
      O => data_hold
    );
data_prev_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => data_hold,
      Q => data_prev,
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(0),
      I1 => data_prev,
      I2 => trn_rd(32),
      O => p_1_in(0)
    );
\m_axis_rx_tdata_xhdl0[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(10),
      I1 => data_prev,
      I2 => trn_rd(42),
      O => p_1_in(10)
    );
\m_axis_rx_tdata_xhdl0[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(11),
      I1 => data_prev,
      I2 => trn_rd(43),
      O => p_1_in(11)
    );
\m_axis_rx_tdata_xhdl0[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(12),
      I1 => data_prev,
      I2 => trn_rd(44),
      O => p_1_in(12)
    );
\m_axis_rx_tdata_xhdl0[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(13),
      I1 => data_prev,
      I2 => trn_rd(45),
      O => p_1_in(13)
    );
\m_axis_rx_tdata_xhdl0[14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(14),
      I1 => data_prev,
      I2 => trn_rd(46),
      O => p_1_in(14)
    );
\m_axis_rx_tdata_xhdl0[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(15),
      I1 => data_prev,
      I2 => trn_rd(47),
      O => p_1_in(15)
    );
\m_axis_rx_tdata_xhdl0[16]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(16),
      I1 => data_prev,
      I2 => trn_rd(48),
      O => p_1_in(16)
    );
\m_axis_rx_tdata_xhdl0[17]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(17),
      I1 => data_prev,
      I2 => trn_rd(49),
      O => p_1_in(17)
    );
\m_axis_rx_tdata_xhdl0[18]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(18),
      I1 => data_prev,
      I2 => trn_rd(50),
      O => p_1_in(18)
    );
\m_axis_rx_tdata_xhdl0[19]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(19),
      I1 => data_prev,
      I2 => trn_rd(51),
      O => p_1_in(19)
    );
\m_axis_rx_tdata_xhdl0[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(1),
      I1 => data_prev,
      I2 => trn_rd(33),
      O => p_1_in(1)
    );
\m_axis_rx_tdata_xhdl0[20]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(20),
      I1 => data_prev,
      I2 => trn_rd(52),
      O => p_1_in(20)
    );
\m_axis_rx_tdata_xhdl0[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(21),
      I1 => data_prev,
      I2 => trn_rd(53),
      O => p_1_in(21)
    );
\m_axis_rx_tdata_xhdl0[22]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(22),
      I1 => data_prev,
      I2 => trn_rd(54),
      O => p_1_in(22)
    );
\m_axis_rx_tdata_xhdl0[23]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(23),
      I1 => data_prev,
      I2 => trn_rd(55),
      O => p_1_in(23)
    );
\m_axis_rx_tdata_xhdl0[24]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(24),
      I1 => data_prev,
      I2 => trn_rd(56),
      O => p_1_in(24)
    );
\m_axis_rx_tdata_xhdl0[25]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(25),
      I1 => data_prev,
      I2 => trn_rd(57),
      O => p_1_in(25)
    );
\m_axis_rx_tdata_xhdl0[26]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(26),
      I1 => data_prev,
      I2 => trn_rd(58),
      O => p_1_in(26)
    );
\m_axis_rx_tdata_xhdl0[27]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(27),
      I1 => data_prev,
      I2 => trn_rd(59),
      O => p_1_in(27)
    );
\m_axis_rx_tdata_xhdl0[28]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(28),
      I1 => data_prev,
      I2 => trn_rd(60),
      O => p_1_in(28)
    );
\m_axis_rx_tdata_xhdl0[29]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(29),
      I1 => data_prev,
      I2 => trn_rd(61),
      O => p_1_in(29)
    );
\m_axis_rx_tdata_xhdl0[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(2),
      I1 => data_prev,
      I2 => trn_rd(34),
      O => p_1_in(2)
    );
\m_axis_rx_tdata_xhdl0[30]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(30),
      I1 => data_prev,
      I2 => trn_rd(62),
      O => p_1_in(30)
    );
\m_axis_rx_tdata_xhdl0[31]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(31),
      I1 => data_prev,
      I2 => trn_rd(63),
      O => p_1_in(31)
    );
\m_axis_rx_tdata_xhdl0[32]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(32),
      I1 => data_prev,
      I2 => trn_rd(0),
      O => p_1_in(32)
    );
\m_axis_rx_tdata_xhdl0[33]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(33),
      I1 => data_prev,
      I2 => trn_rd(1),
      O => p_1_in(33)
    );
\m_axis_rx_tdata_xhdl0[34]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(34),
      I1 => data_prev,
      I2 => trn_rd(2),
      O => p_1_in(34)
    );
\m_axis_rx_tdata_xhdl0[35]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(35),
      I1 => data_prev,
      I2 => trn_rd(3),
      O => p_1_in(35)
    );
\m_axis_rx_tdata_xhdl0[36]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(36),
      I1 => data_prev,
      I2 => trn_rd(4),
      O => p_1_in(36)
    );
\m_axis_rx_tdata_xhdl0[37]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(37),
      I1 => data_prev,
      I2 => trn_rd(5),
      O => p_1_in(37)
    );
\m_axis_rx_tdata_xhdl0[38]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(38),
      I1 => data_prev,
      I2 => trn_rd(6),
      O => p_1_in(38)
    );
\m_axis_rx_tdata_xhdl0[39]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(39),
      I1 => data_prev,
      I2 => trn_rd(7),
      O => p_1_in(39)
    );
\m_axis_rx_tdata_xhdl0[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(3),
      I1 => data_prev,
      I2 => trn_rd(35),
      O => p_1_in(3)
    );
\m_axis_rx_tdata_xhdl0[40]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(40),
      I1 => data_prev,
      I2 => trn_rd(8),
      O => p_1_in(40)
    );
\m_axis_rx_tdata_xhdl0[41]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(41),
      I1 => data_prev,
      I2 => trn_rd(9),
      O => p_1_in(41)
    );
\m_axis_rx_tdata_xhdl0[42]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(42),
      I1 => data_prev,
      I2 => trn_rd(10),
      O => p_1_in(42)
    );
\m_axis_rx_tdata_xhdl0[43]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(43),
      I1 => data_prev,
      I2 => trn_rd(11),
      O => p_1_in(43)
    );
\m_axis_rx_tdata_xhdl0[44]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(44),
      I1 => data_prev,
      I2 => trn_rd(12),
      O => p_1_in(44)
    );
\m_axis_rx_tdata_xhdl0[45]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(45),
      I1 => data_prev,
      I2 => trn_rd(13),
      O => p_1_in(45)
    );
\m_axis_rx_tdata_xhdl0[46]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(46),
      I1 => data_prev,
      I2 => trn_rd(14),
      O => p_1_in(46)
    );
\m_axis_rx_tdata_xhdl0[47]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(47),
      I1 => data_prev,
      I2 => trn_rd(15),
      O => p_1_in(47)
    );
\m_axis_rx_tdata_xhdl0[48]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(48),
      I1 => data_prev,
      I2 => trn_rd(16),
      O => p_1_in(48)
    );
\m_axis_rx_tdata_xhdl0[49]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(49),
      I1 => data_prev,
      I2 => trn_rd(17),
      O => p_1_in(49)
    );
\m_axis_rx_tdata_xhdl0[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(4),
      I1 => data_prev,
      I2 => trn_rd(36),
      O => p_1_in(4)
    );
\m_axis_rx_tdata_xhdl0[50]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(50),
      I1 => data_prev,
      I2 => trn_rd(18),
      O => p_1_in(50)
    );
\m_axis_rx_tdata_xhdl0[51]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(51),
      I1 => data_prev,
      I2 => trn_rd(19),
      O => p_1_in(51)
    );
\m_axis_rx_tdata_xhdl0[52]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(52),
      I1 => data_prev,
      I2 => trn_rd(20),
      O => p_1_in(52)
    );
\m_axis_rx_tdata_xhdl0[53]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(53),
      I1 => data_prev,
      I2 => trn_rd(21),
      O => p_1_in(53)
    );
\m_axis_rx_tdata_xhdl0[54]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(54),
      I1 => data_prev,
      I2 => trn_rd(22),
      O => p_1_in(54)
    );
\m_axis_rx_tdata_xhdl0[55]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(55),
      I1 => data_prev,
      I2 => trn_rd(23),
      O => p_1_in(55)
    );
\m_axis_rx_tdata_xhdl0[56]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(56),
      I1 => data_prev,
      I2 => trn_rd(24),
      O => p_1_in(56)
    );
\m_axis_rx_tdata_xhdl0[57]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(57),
      I1 => data_prev,
      I2 => trn_rd(25),
      O => p_1_in(57)
    );
\m_axis_rx_tdata_xhdl0[58]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(58),
      I1 => data_prev,
      I2 => trn_rd(26),
      O => p_1_in(58)
    );
\m_axis_rx_tdata_xhdl0[59]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(59),
      I1 => data_prev,
      I2 => trn_rd(27),
      O => p_1_in(59)
    );
\m_axis_rx_tdata_xhdl0[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(5),
      I1 => data_prev,
      I2 => trn_rd(37),
      O => p_1_in(5)
    );
\m_axis_rx_tdata_xhdl0[60]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(60),
      I1 => data_prev,
      I2 => trn_rd(28),
      O => p_1_in(60)
    );
\m_axis_rx_tdata_xhdl0[61]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(61),
      I1 => data_prev,
      I2 => trn_rd(29),
      O => p_1_in(61)
    );
\m_axis_rx_tdata_xhdl0[62]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(62),
      I1 => data_prev,
      I2 => trn_rd(30),
      O => p_1_in(62)
    );
\m_axis_rx_tdata_xhdl0[63]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => m_axis_rx_tready,
      I1 => \^m_axis_rx_tvalid_xhdl2_reg_0\,
      O => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\
    );
\m_axis_rx_tdata_xhdl0[63]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(63),
      I1 => data_prev,
      I2 => trn_rd(31),
      O => p_1_in(63)
    );
\m_axis_rx_tdata_xhdl0[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(6),
      I1 => data_prev,
      I2 => trn_rd(38),
      O => p_1_in(6)
    );
\m_axis_rx_tdata_xhdl0[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(7),
      I1 => data_prev,
      I2 => trn_rd(39),
      O => p_1_in(7)
    );
\m_axis_rx_tdata_xhdl0[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(8),
      I1 => data_prev,
      I2 => trn_rd(40),
      O => p_1_in(8)
    );
\m_axis_rx_tdata_xhdl0[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => trn_rd_prev(9),
      I1 => data_prev,
      I2 => trn_rd(41),
      O => p_1_in(9)
    );
\m_axis_rx_tdata_xhdl0_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(0),
      Q => \^m_axis_rx_tdata\(0),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(10),
      Q => \^m_axis_rx_tdata\(10),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(11),
      Q => \^m_axis_rx_tdata\(11),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(12),
      Q => \^m_axis_rx_tdata\(12),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(13),
      Q => \^m_axis_rx_tdata\(13),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(14),
      Q => \^m_axis_rx_tdata\(14),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(15),
      Q => \^m_axis_rx_tdata\(15),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(16),
      Q => \^m_axis_rx_tdata\(16),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(17),
      Q => \^m_axis_rx_tdata\(17),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(18),
      Q => \^m_axis_rx_tdata\(18),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(19),
      Q => \^m_axis_rx_tdata\(19),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(1),
      Q => \^m_axis_rx_tdata\(1),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(20),
      Q => \^m_axis_rx_tdata\(20),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(21),
      Q => \^m_axis_rx_tdata\(21),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(22),
      Q => \^m_axis_rx_tdata\(22),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(23),
      Q => \^m_axis_rx_tdata\(23),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(24),
      Q => \^m_axis_rx_tdata\(24),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(25),
      Q => \^m_axis_rx_tdata\(25),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(26),
      Q => \^m_axis_rx_tdata\(26),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(27),
      Q => \^m_axis_rx_tdata\(27),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(28),
      Q => \^m_axis_rx_tdata\(28),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(29),
      Q => \^m_axis_rx_tdata\(29),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(2),
      Q => \^m_axis_rx_tdata\(2),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(30),
      Q => \^m_axis_rx_tdata\(30),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(31),
      Q => \^m_axis_rx_tdata\(31),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[32]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(32),
      Q => \^m_axis_rx_tdata\(32),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[33]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(33),
      Q => \^m_axis_rx_tdata\(33),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[34]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(34),
      Q => \^m_axis_rx_tdata\(34),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[35]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(35),
      Q => \^m_axis_rx_tdata\(35),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[36]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(36),
      Q => \^m_axis_rx_tdata\(36),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[37]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(37),
      Q => \^m_axis_rx_tdata\(37),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[38]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(38),
      Q => \^m_axis_rx_tdata\(38),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[39]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(39),
      Q => \^m_axis_rx_tdata\(39),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(3),
      Q => \^m_axis_rx_tdata\(3),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[40]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(40),
      Q => \^m_axis_rx_tdata\(40),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[41]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(41),
      Q => \^m_axis_rx_tdata\(41),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[42]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(42),
      Q => \^m_axis_rx_tdata\(42),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[43]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(43),
      Q => \^m_axis_rx_tdata\(43),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[44]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(44),
      Q => \^m_axis_rx_tdata\(44),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[45]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(45),
      Q => \^m_axis_rx_tdata\(45),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[46]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(46),
      Q => \^m_axis_rx_tdata\(46),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[47]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(47),
      Q => \^m_axis_rx_tdata\(47),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[48]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(48),
      Q => \^m_axis_rx_tdata\(48),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[49]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(49),
      Q => \^m_axis_rx_tdata\(49),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(4),
      Q => \^m_axis_rx_tdata\(4),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[50]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(50),
      Q => \^m_axis_rx_tdata\(50),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[51]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(51),
      Q => \^m_axis_rx_tdata\(51),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[52]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(52),
      Q => \^m_axis_rx_tdata\(52),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[53]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(53),
      Q => \^m_axis_rx_tdata\(53),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[54]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(54),
      Q => \^m_axis_rx_tdata\(54),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[55]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(55),
      Q => \^m_axis_rx_tdata\(55),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[56]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(56),
      Q => \^m_axis_rx_tdata\(56),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[57]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(57),
      Q => \^m_axis_rx_tdata\(57),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[58]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(58),
      Q => \^m_axis_rx_tdata\(58),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[59]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(59),
      Q => \^m_axis_rx_tdata\(59),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(5),
      Q => \^m_axis_rx_tdata\(5),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[60]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(60),
      Q => \^m_axis_rx_tdata\(60),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[61]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(61),
      Q => \^m_axis_rx_tdata\(61),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[62]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(62),
      Q => \^m_axis_rx_tdata\(62),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[63]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(63),
      Q => \^m_axis_rx_tdata\(63),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(6),
      Q => \^m_axis_rx_tdata\(6),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(7),
      Q => \^m_axis_rx_tdata\(7),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(8),
      Q => \^m_axis_rx_tdata\(8),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tdata_xhdl0_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => p_1_in(9),
      Q => \^m_axis_rx_tdata\(9),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\m_axis_rx_tuser_xhdl1[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000E2"
    )
        port map (
      I0 => trn_recrc_err,
      I1 => data_prev,
      I2 => trn_recrc_err_prev,
      I3 => \trn_rbar_hit_prev_reg[0]_0\,
      I4 => \^null_mux_sel\,
      O => m_axis_rx_tuser_xhdl1(0)
    );
\m_axis_rx_tuser_xhdl1[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000004F40404"
    )
        port map (
      I0 => trn_rsrc_dsc,
      I1 => trn_rsof,
      I2 => data_prev,
      I3 => trn_rsrc_dsc_prev,
      I4 => trn_rsof_prev,
      I5 => \m_axis_rx_tuser_xhdl1[14]_i_2_n_0\,
      O => m_axis_rx_tuser_xhdl1(14)
    );
\m_axis_rx_tuser_xhdl1[14]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \trn_rbar_hit_prev_reg[0]_0\,
      I1 => \^null_mux_sel\,
      O => \m_axis_rx_tuser_xhdl1[14]_i_2_n_0\
    );
\m_axis_rx_tuser_xhdl1[18]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \trn_rbar_hit_prev_reg[0]_0\,
      O => m_axis_rx_tuser_xhdl1(18)
    );
\m_axis_rx_tuser_xhdl1[19]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => trn_rrem(0),
      I1 => data_prev,
      I2 => is_eof_prev(2),
      I3 => \^null_mux_sel\,
      O => data_prev_reg_1
    );
\m_axis_rx_tuser_xhdl1[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000E2"
    )
        port map (
      I0 => trn_rerrfwd,
      I1 => data_prev,
      I2 => trn_rerrfwd_prev,
      I3 => \trn_rbar_hit_prev_reg[0]_0\,
      I4 => \^null_mux_sel\,
      O => m_axis_rx_tuser_xhdl1(1)
    );
\m_axis_rx_tuser_xhdl1[21]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EF"
    )
        port map (
      I0 => \trn_rbar_hit_prev_reg[0]_0\,
      I1 => m_axis_rx_tready,
      I2 => \^m_axis_rx_tvalid_xhdl2_reg_0\,
      O => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\
    );
\m_axis_rx_tuser_xhdl1[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000B8"
    )
        port map (
      I0 => trn_rbar_hit_prev(0),
      I1 => data_prev,
      I2 => trn_rbar_hit(0),
      I3 => \trn_rbar_hit_prev_reg[0]_0\,
      I4 => \^null_mux_sel\,
      O => m_axis_rx_tuser_xhdl1(2)
    );
\m_axis_rx_tuser_xhdl1[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000E2"
    )
        port map (
      I0 => trn_rbar_hit(1),
      I1 => data_prev,
      I2 => trn_rbar_hit_prev(1),
      I3 => \trn_rbar_hit_prev_reg[0]_0\,
      I4 => \^null_mux_sel\,
      O => m_axis_rx_tuser_xhdl1(3)
    );
\m_axis_rx_tuser_xhdl1[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000B8"
    )
        port map (
      I0 => trn_rbar_hit_prev(2),
      I1 => data_prev,
      I2 => trn_rbar_hit(2),
      I3 => \trn_rbar_hit_prev_reg[0]_0\,
      I4 => \^null_mux_sel\,
      O => m_axis_rx_tuser_xhdl1(4)
    );
\m_axis_rx_tuser_xhdl1[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000E2"
    )
        port map (
      I0 => trn_rbar_hit(3),
      I1 => data_prev,
      I2 => trn_rbar_hit_prev(3),
      I3 => \trn_rbar_hit_prev_reg[0]_0\,
      I4 => \^null_mux_sel\,
      O => m_axis_rx_tuser_xhdl1(5)
    );
\m_axis_rx_tuser_xhdl1[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000E2"
    )
        port map (
      I0 => trn_rbar_hit(4),
      I1 => data_prev,
      I2 => trn_rbar_hit_prev(4),
      I3 => \trn_rbar_hit_prev_reg[0]_0\,
      I4 => \^null_mux_sel\,
      O => m_axis_rx_tuser_xhdl1(6)
    );
\m_axis_rx_tuser_xhdl1[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000B8"
    )
        port map (
      I0 => trn_rbar_hit_prev(5),
      I1 => data_prev,
      I2 => trn_rbar_hit(5),
      I3 => \trn_rbar_hit_prev_reg[0]_0\,
      I4 => \^null_mux_sel\,
      O => m_axis_rx_tuser_xhdl1(7)
    );
\m_axis_rx_tuser_xhdl1[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000000B8"
    )
        port map (
      I0 => trn_rbar_hit_prev(6),
      I1 => data_prev,
      I2 => trn_rbar_hit(6),
      I3 => \trn_rbar_hit_prev_reg[0]_0\,
      I4 => \^null_mux_sel\,
      O => m_axis_rx_tuser_xhdl1(8)
    );
\m_axis_rx_tuser_xhdl1_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => m_axis_rx_tuser_xhdl1(0),
      Q => m_axis_rx_tuser(0),
      R => '0'
    );
\m_axis_rx_tuser_xhdl1_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => m_axis_rx_tuser_xhdl1(14),
      Q => m_axis_rx_tuser(9),
      R => '0'
    );
\m_axis_rx_tuser_xhdl1_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => m_axis_rx_tuser_xhdl1(18),
      Q => m_axis_rx_tuser(10),
      R => '0'
    );
\m_axis_rx_tuser_xhdl1_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => D(0),
      Q => m_axis_rx_tuser(11),
      R => '0'
    );
\m_axis_rx_tuser_xhdl1_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => m_axis_rx_tuser_xhdl1(1),
      Q => m_axis_rx_tuser(1),
      R => '0'
    );
\m_axis_rx_tuser_xhdl1_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => D(1),
      Q => m_axis_rx_tuser(12),
      R => '0'
    );
\m_axis_rx_tuser_xhdl1_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => m_axis_rx_tuser_xhdl1(2),
      Q => m_axis_rx_tuser(2),
      R => '0'
    );
\m_axis_rx_tuser_xhdl1_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => m_axis_rx_tuser_xhdl1(3),
      Q => m_axis_rx_tuser(3),
      R => '0'
    );
\m_axis_rx_tuser_xhdl1_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => m_axis_rx_tuser_xhdl1(4),
      Q => m_axis_rx_tuser(4),
      R => '0'
    );
\m_axis_rx_tuser_xhdl1_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => m_axis_rx_tuser_xhdl1(5),
      Q => m_axis_rx_tuser(5),
      R => '0'
    );
\m_axis_rx_tuser_xhdl1_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => m_axis_rx_tuser_xhdl1(6),
      Q => m_axis_rx_tuser(6),
      R => '0'
    );
\m_axis_rx_tuser_xhdl1_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => m_axis_rx_tuser_xhdl1(7),
      Q => m_axis_rx_tuser(7),
      R => '0'
    );
\m_axis_rx_tuser_xhdl1_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tuser_xhdl1[21]_i_1_n_0\,
      D => m_axis_rx_tuser_xhdl1(8),
      Q => m_axis_rx_tuser(8),
      R => '0'
    );
m_axis_rx_tvalid_xhdl2_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFE2"
    )
        port map (
      I0 => rsrc_rdy_filtered6_out,
      I1 => data_prev,
      I2 => trn_rsrc_rdy_prev,
      I3 => \^null_mux_sel\,
      I4 => dsc_detect,
      I5 => \^reg_dsc_detect_reg_0\,
      O => m_axis_rx_tvalid_xhdl2_i_1_n_0
    );
m_axis_rx_tvalid_xhdl2_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => m_axis_rx_tvalid_xhdl2_i_1_n_0,
      Q => \^m_axis_rx_tvalid_xhdl2_reg_0\,
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
new_pkt_len_1_inferred_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7800"
    )
        port map (
      I0 => new_pkt_len_1_inferred_i_6_n_0,
      I1 => \^m_axis_rx_tdata\(3),
      I2 => \^m_axis_rx_tdata\(4),
      I3 => \^m_axis_rx_tdata\(30),
      O => in0(4)
    );
new_pkt_len_1_inferred_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"6A"
    )
        port map (
      I0 => new_pkt_len_1_inferred_i_6_n_0,
      I1 => \^m_axis_rx_tdata\(3),
      I2 => \^m_axis_rx_tdata\(30),
      O => in0(3)
    );
new_pkt_len_1_inferred_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"017FFE8000000000"
    )
        port map (
      I0 => \^m_axis_rx_tdata\(0),
      I1 => \^m_axis_rx_tdata\(15),
      I2 => \^m_axis_rx_tdata\(29),
      I3 => \^m_axis_rx_tdata\(1),
      I4 => \^m_axis_rx_tdata\(2),
      I5 => \^m_axis_rx_tdata\(30),
      O => in0(2)
    );
new_pkt_len_1_inferred_i_4: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B73F3F48"
    )
        port map (
      I0 => \^m_axis_rx_tdata\(0),
      I1 => \^m_axis_rx_tdata\(30),
      I2 => \^m_axis_rx_tdata\(1),
      I3 => \^m_axis_rx_tdata\(15),
      I4 => \^m_axis_rx_tdata\(29),
      O => in0(1)
    );
new_pkt_len_1_inferred_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6999"
    )
        port map (
      I0 => \^m_axis_rx_tdata\(29),
      I1 => \^m_axis_rx_tdata\(15),
      I2 => \^m_axis_rx_tdata\(0),
      I3 => \^m_axis_rx_tdata\(30),
      O => in0(0)
    );
new_pkt_len_1_inferred_i_6: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAA8000080000000"
    )
        port map (
      I0 => \^m_axis_rx_tdata\(2),
      I1 => \^m_axis_rx_tdata\(0),
      I2 => \^m_axis_rx_tdata\(15),
      I3 => \^m_axis_rx_tdata\(29),
      I4 => \^m_axis_rx_tdata\(30),
      I5 => \^m_axis_rx_tdata\(1),
      O => new_pkt_len_1_inferred_i_6_n_0
    );
new_pkt_len_inferred_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^m_axis_rx_tdata\(30),
      I1 => \^m_axis_rx_tdata\(9),
      O => \m_axis_rx_tdata_xhdl0_reg[30]_0\(4)
    );
new_pkt_len_inferred_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^m_axis_rx_tdata\(30),
      I1 => \^m_axis_rx_tdata\(8),
      O => \m_axis_rx_tdata_xhdl0_reg[30]_0\(3)
    );
new_pkt_len_inferred_i_3: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^m_axis_rx_tdata\(30),
      I1 => \^m_axis_rx_tdata\(7),
      O => \m_axis_rx_tdata_xhdl0_reg[30]_0\(2)
    );
new_pkt_len_inferred_i_4: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^m_axis_rx_tdata\(30),
      I1 => \^m_axis_rx_tdata\(6),
      O => \m_axis_rx_tdata_xhdl0_reg[30]_0\(1)
    );
new_pkt_len_inferred_i_5: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^m_axis_rx_tdata\(30),
      I1 => \^m_axis_rx_tdata\(5),
      O => \m_axis_rx_tdata_xhdl0_reg[30]_0\(0)
    );
null_mux_sel_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"ABAAABAAABAABBBB"
    )
        port map (
      I0 => \trn_rbar_hit_prev_reg[0]_0\,
      I1 => \^null_mux_sel\,
      I2 => m_axis_rx_tready,
      I3 => \^m_axis_rx_tvalid_xhdl2_reg_0\,
      I4 => dsc_detect,
      I5 => \^reg_dsc_detect_reg_0\,
      O => user_reset_out_reg
    );
null_mux_sel_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => null_mux_sel_reg_0,
      Q => \^null_mux_sel\,
      R => '0'
    );
reg_dsc_detect_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DC"
    )
        port map (
      I0 => \^null_mux_sel\,
      I1 => dsc_detect,
      I2 => \^reg_dsc_detect_reg_0\,
      O => reg_dsc_detect_i_1_n_0
    );
reg_dsc_detect_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => reg_dsc_detect_i_1_n_0,
      Q => \^reg_dsc_detect_reg_0\,
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\reg_tkeep[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F7F7F7C4C4C4F7C4"
    )
        port map (
      I0 => trn_rdst_rdy_xhdl4_reg_0,
      I1 => \^null_mux_sel\,
      I2 => \reg_tkeep_reg[7]_0\(0),
      I3 => trn_rrem(0),
      I4 => data_prev,
      I5 => is_eof_prev(2),
      O => \reg_tkeep[7]_i_1_n_0\
    );
\reg_tkeep_reg[3]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => '1',
      Q => m_axis_rx_tkeep(0),
      S => \trn_rbar_hit_prev_reg[0]_0\
    );
\reg_tkeep_reg[7]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => \reg_tkeep[7]_i_1_n_0\,
      Q => m_axis_rx_tkeep(1),
      S => \trn_rbar_hit_prev_reg[0]_0\
    );
reg_tlast_i_2: unisim.vcomponents.LUT4
    generic map(
      INIT => X"00E2"
    )
        port map (
      I0 => trn_reof,
      I1 => data_prev,
      I2 => is_eof_prev(4),
      I3 => \^null_mux_sel\,
      O => data_prev_reg_0
    );
reg_tlast_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \m_axis_rx_tdata_xhdl0[63]_i_1_n_0\,
      D => reg_tlast_reg_0,
      Q => m_axis_rx_tlast,
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
trn_in_packet_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => trn_in_packet_reg_0,
      Q => trn_in_packet,
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rbar_hit_prev_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rbar_hit(0),
      Q => trn_rbar_hit_prev(0),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rbar_hit_prev_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rbar_hit(1),
      Q => trn_rbar_hit_prev(1),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rbar_hit_prev_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rbar_hit(2),
      Q => trn_rbar_hit_prev(2),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rbar_hit_prev_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rbar_hit(3),
      Q => trn_rbar_hit_prev(3),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rbar_hit_prev_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rbar_hit(4),
      Q => trn_rbar_hit_prev(4),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rbar_hit_prev_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rbar_hit(5),
      Q => trn_rbar_hit_prev(5),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rbar_hit_prev_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rbar_hit(6),
      Q => trn_rbar_hit_prev(6),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(32),
      Q => trn_rd_prev(0),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(42),
      Q => trn_rd_prev(10),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(43),
      Q => trn_rd_prev(11),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(44),
      Q => trn_rd_prev(12),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(45),
      Q => trn_rd_prev(13),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(46),
      Q => trn_rd_prev(14),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(47),
      Q => trn_rd_prev(15),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(48),
      Q => trn_rd_prev(16),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(49),
      Q => trn_rd_prev(17),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(50),
      Q => trn_rd_prev(18),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(51),
      Q => trn_rd_prev(19),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(33),
      Q => trn_rd_prev(1),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(52),
      Q => trn_rd_prev(20),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(53),
      Q => trn_rd_prev(21),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(54),
      Q => trn_rd_prev(22),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(55),
      Q => trn_rd_prev(23),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(56),
      Q => trn_rd_prev(24),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(57),
      Q => trn_rd_prev(25),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(58),
      Q => trn_rd_prev(26),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(59),
      Q => trn_rd_prev(27),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(60),
      Q => trn_rd_prev(28),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(61),
      Q => trn_rd_prev(29),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(34),
      Q => trn_rd_prev(2),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(62),
      Q => trn_rd_prev(30),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(63),
      Q => trn_rd_prev(31),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[32]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(0),
      Q => trn_rd_prev(32),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[33]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(1),
      Q => trn_rd_prev(33),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[34]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(2),
      Q => trn_rd_prev(34),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[35]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(3),
      Q => trn_rd_prev(35),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[36]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(4),
      Q => trn_rd_prev(36),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[37]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(5),
      Q => trn_rd_prev(37),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[38]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(6),
      Q => trn_rd_prev(38),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[39]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(7),
      Q => trn_rd_prev(39),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(35),
      Q => trn_rd_prev(3),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[40]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(8),
      Q => trn_rd_prev(40),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[41]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(9),
      Q => trn_rd_prev(41),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[42]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(10),
      Q => trn_rd_prev(42),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[43]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(11),
      Q => trn_rd_prev(43),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[44]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(12),
      Q => trn_rd_prev(44),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[45]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(13),
      Q => trn_rd_prev(45),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[46]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(14),
      Q => trn_rd_prev(46),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[47]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(15),
      Q => trn_rd_prev(47),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[48]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(16),
      Q => trn_rd_prev(48),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[49]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(17),
      Q => trn_rd_prev(49),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(36),
      Q => trn_rd_prev(4),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[50]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(18),
      Q => trn_rd_prev(50),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[51]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(19),
      Q => trn_rd_prev(51),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[52]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(20),
      Q => trn_rd_prev(52),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[53]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(21),
      Q => trn_rd_prev(53),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[54]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(22),
      Q => trn_rd_prev(54),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[55]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(23),
      Q => trn_rd_prev(55),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[56]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(24),
      Q => trn_rd_prev(56),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[57]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(25),
      Q => trn_rd_prev(57),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[58]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(26),
      Q => trn_rd_prev(58),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[59]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(27),
      Q => trn_rd_prev(59),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(37),
      Q => trn_rd_prev(5),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[60]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(28),
      Q => trn_rd_prev(60),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[61]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(29),
      Q => trn_rd_prev(61),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[62]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(30),
      Q => trn_rd_prev(62),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[63]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(31),
      Q => trn_rd_prev(63),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(38),
      Q => trn_rd_prev(6),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(39),
      Q => trn_rd_prev(7),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(40),
      Q => trn_rd_prev(8),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rd_prev_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rd(41),
      Q => trn_rd_prev(9),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
trn_rdst_rdy_xhdl4_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3030FF3050505050"
    )
        port map (
      I0 => \^m_axis_rx_tvalid_xhdl2_reg_0\,
      I1 => \^null_mux_sel\,
      I2 => trn_rdst_rdy_xhdl4_i_2_n_0,
      I3 => trn_rdst_rdy_xhdl4_reg_0,
      I4 => trn_rdst_rdy_xhdl4_reg_1,
      I5 => m_axis_rx_tready,
      O => trn_rdst_rdy_xhdl4_i_1_n_0
    );
trn_rdst_rdy_xhdl4_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^reg_dsc_detect_reg_0\,
      I1 => dsc_detect,
      O => trn_rdst_rdy_xhdl4_i_2_n_0
    );
trn_rdst_rdy_xhdl4_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => trn_rdst_rdy_xhdl4_i_1_n_0,
      Q => \^e\(0),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
trn_recrc_err_prev_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_recrc_err,
      Q => trn_recrc_err_prev,
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
trn_reof_prev_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_reof,
      Q => is_eof_prev(4),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
trn_rerrfwd_prev_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rerrfwd,
      Q => trn_rerrfwd_prev,
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
\trn_rrem_prev_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rrem(0),
      Q => is_eof_prev(2),
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
trn_rsof_prev_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rsof,
      Q => trn_rsof_prev,
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
trn_rsrc_dsc_d_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => trn_rsrc_dsc,
      Q => trn_rsrc_dsc_d,
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
trn_rsrc_dsc_prev_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => trn_rsrc_dsc_prev0,
      Q => trn_rsrc_dsc_prev,
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
trn_rsrc_rdy_prev_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \^e\(0),
      D => rsrc_rdy_filtered6_out,
      Q => trn_rsrc_rdy_prev,
      R => \trn_rbar_hit_prev_reg[0]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_tx_pipeline is
  port (
    trn_teof : out STD_LOGIC;
    trn_tsrc_rdy : out STD_LOGIC;
    trn_trem : out STD_LOGIC_VECTOR ( 0 to 0 );
    axi_in_packet : out STD_LOGIC;
    reg_disable_trn : out STD_LOGIC;
    trn_tsof : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \xhdl12.reg_tuser_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \xhdl12.reg_tuser_reg[0]_0\ : in STD_LOGIC;
    s_axis_tx_tlast : in STD_LOGIC;
    CLK : in STD_LOGIC;
    reg_tsrc_rdy0 : in STD_LOGIC;
    s_axis_tx_tvalid : in STD_LOGIC;
    s_axis_tx_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
    axi_in_packet_reg_0 : in STD_LOGIC;
    \TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg_0\ : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    trn_tdst_rdy : in STD_LOGIC;
    s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axis_tx_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_tx_pipeline : entity is "spec7_pcie_7x_0_axi_basic_tx_pipeline";
end spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_tx_pipeline;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_tx_pipeline is
  signal \TNRTL_CTL_TRN_FLUSH.reg_disable_trn_i_1_n_0\ : STD_LOGIC;
  signal \^axi_in_packet\ : STD_LOGIC;
  signal \^reg_disable_trn\ : STD_LOGIC;
  signal reg_tvalid : STD_LOGIC;
  signal trn_in_packet : STD_LOGIC;
  signal \trn_in_packet_i_1__0_n_0\ : STD_LOGIC;
  signal \^trn_teof\ : STD_LOGIC;
  signal \^trn_tsrc_rdy\ : STD_LOGIC;
begin
  axi_in_packet <= \^axi_in_packet\;
  reg_disable_trn <= \^reg_disable_trn\;
  trn_teof <= \^trn_teof\;
  trn_tsrc_rdy <= \^trn_tsrc_rdy\;
\TNRTL_CTL_TRN_FLUSH.reg_disable_trn_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F7F7F7F007F0000"
    )
        port map (
      I0 => s_axis_tx_tlast,
      I1 => s_axis_tx_tvalid,
      I2 => \TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg_0\,
      I3 => \out\,
      I4 => \^axi_in_packet\,
      I5 => \^reg_disable_trn\,
      O => \TNRTL_CTL_TRN_FLUSH.reg_disable_trn_i_1_n_0\
    );
\TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \TNRTL_CTL_TRN_FLUSH.reg_disable_trn_i_1_n_0\,
      Q => \^reg_disable_trn\,
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
axi_in_packet_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => axi_in_packet_reg_0,
      Q => \^axi_in_packet\,
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
pcie_block_i_i_31: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => reg_tvalid,
      I1 => trn_in_packet,
      O => trn_tsof
    );
\trn_in_packet_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000F088F000F000"
    )
        port map (
      I0 => trn_tdst_rdy,
      I1 => reg_tvalid,
      I2 => \out\,
      I3 => trn_in_packet,
      I4 => \^trn_teof\,
      I5 => \^trn_tsrc_rdy\,
      O => \trn_in_packet_i_1__0_n_0\
    );
trn_in_packet_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \trn_in_packet_i_1__0_n_0\,
      Q => trn_in_packet,
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(0),
      Q => Q(0),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(10),
      Q => Q(10),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(11),
      Q => Q(11),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(12),
      Q => Q(12),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(13),
      Q => Q(13),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(14),
      Q => Q(14),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(15),
      Q => Q(15),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(16),
      Q => Q(16),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(17),
      Q => Q(17),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(18),
      Q => Q(18),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(19),
      Q => Q(19),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(1),
      Q => Q(1),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(20),
      Q => Q(20),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(21),
      Q => Q(21),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[22]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(22),
      Q => Q(22),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(23),
      Q => Q(23),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(24),
      Q => Q(24),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(25),
      Q => Q(25),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(26),
      Q => Q(26),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(27),
      Q => Q(27),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(28),
      Q => Q(28),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(29),
      Q => Q(29),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(2),
      Q => Q(2),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[30]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(30),
      Q => Q(30),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[31]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(31),
      Q => Q(31),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[32]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(32),
      Q => Q(32),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[33]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(33),
      Q => Q(33),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[34]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(34),
      Q => Q(34),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[35]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(35),
      Q => Q(35),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[36]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(36),
      Q => Q(36),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[37]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(37),
      Q => Q(37),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[38]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(38),
      Q => Q(38),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[39]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(39),
      Q => Q(39),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(3),
      Q => Q(3),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[40]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(40),
      Q => Q(40),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[41]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(41),
      Q => Q(41),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[42]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(42),
      Q => Q(42),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[43]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(43),
      Q => Q(43),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[44]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(44),
      Q => Q(44),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[45]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(45),
      Q => Q(45),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[46]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(46),
      Q => Q(46),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[47]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(47),
      Q => Q(47),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[48]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(48),
      Q => Q(48),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[49]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(49),
      Q => Q(49),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(4),
      Q => Q(4),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[50]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(50),
      Q => Q(50),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[51]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(51),
      Q => Q(51),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[52]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(52),
      Q => Q(52),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[53]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(53),
      Q => Q(53),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[54]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(54),
      Q => Q(54),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[55]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(55),
      Q => Q(55),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[56]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(56),
      Q => Q(56),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[57]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(57),
      Q => Q(57),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[58]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(58),
      Q => Q(58),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[59]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(59),
      Q => Q(59),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(5),
      Q => Q(5),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[60]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(60),
      Q => Q(60),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[61]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(61),
      Q => Q(61),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[62]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(62),
      Q => Q(62),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[63]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(63),
      Q => Q(63),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(6),
      Q => Q(6),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(7),
      Q => Q(7),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(8),
      Q => Q(8),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tdata_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tdata(9),
      Q => Q(9),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tkeep_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tkeep(0),
      Q => trn_trem(0),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tlast_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tlast,
      Q => \^trn_teof\,
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tsrc_rdy_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => reg_tsrc_rdy0,
      Q => \^trn_tsrc_rdy\,
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tuser_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tuser(0),
      Q => \xhdl12.reg_tuser_reg[3]_0\(0),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tuser_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tuser(1),
      Q => \xhdl12.reg_tuser_reg[3]_0\(1),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tuser_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tuser(2),
      Q => \xhdl12.reg_tuser_reg[3]_0\(2),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tuser_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tuser(3),
      Q => \xhdl12.reg_tuser_reg[3]_0\(3),
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
\xhdl12.reg_tvalid_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => s_axis_tx_tvalid,
      Q => reg_tvalid,
      R => \xhdl12.reg_tuser_reg[0]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_tx_thrtl_ctl is
  port (
    reg_tcfg_gnt : out STD_LOGIC;
    tready_thrtl_xhdl1_reg_0 : out STD_LOGIC;
    ppm_L1_thrtl : out STD_LOGIC;
    \xhdl12.xhdl14.xhdl15.reg_to_turnoff_reg_0\ : out STD_LOGIC;
    lnk_up_thrtl : out STD_LOGIC;
    s_axis_tx_tlast_0 : out STD_LOGIC;
    reg_tsrc_rdy0 : out STD_LOGIC;
    cfg_pm_turnoff_ok_n : out STD_LOGIC;
    trn_tcfg_gnt : out STD_LOGIC;
    ppm_L1_trig : out STD_LOGIC;
    \tbuf_gap_cnt_reg[0]_0\ : in STD_LOGIC;
    tx_cfg_gnt : in STD_LOGIC;
    CLK : in STD_LOGIC;
    trn_tdst_rdy : in STD_LOGIC;
    trn_tcfg_req : in STD_LOGIC;
    cfg_turnoff_ok : in STD_LOGIC;
    tbuf_av_min_trig : in STD_LOGIC;
    ppm_L1_thrtl_reg_0 : in STD_LOGIC;
    \xhdl12.xhdl14.xhdl15.reg_to_turnoff_reg_1\ : in STD_LOGIC;
    lnk_up_thrtl_reg_0 : in STD_LOGIC;
    s_axis_tx_tlast : in STD_LOGIC;
    s_axis_tx_tvalid : in STD_LOGIC;
    axi_in_packet : in STD_LOGIC;
    s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axis_tx_tuser : in STD_LOGIC_VECTOR ( 0 to 0 );
    \out\ : in STD_LOGIC;
    reg_disable_trn : in STD_LOGIC;
    tready_thrtl_xhdl1_i_4_0 : in STD_LOGIC;
    trn_tbuf_av : in STD_LOGIC_VECTOR ( 5 downto 0 );
    tcfg_req_trig : in STD_LOGIC;
    cfg_pcie_link_state : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_tx_thrtl_ctl : entity is "spec7_pcie_7x_0_axi_basic_tx_thrtl_ctl";
end spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_tx_thrtl_ctl;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_tx_thrtl_ctl is
  signal CUR_STATE_A : STD_LOGIC;
  signal CUR_STATE_A_i_2_n_0 : STD_LOGIC;
  signal NEXT_STATE_A : STD_LOGIC;
  signal cfg_pcie_link_state_d : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^cfg_pm_turnoff_ok_n\ : STD_LOGIC;
  signal cfg_turnoff_ok_pending : STD_LOGIC;
  signal cfg_turnoff_ok_pending_i_1_n_0 : STD_LOGIC;
  signal gtOp : STD_LOGIC;
  signal \^lnk_up_thrtl\ : STD_LOGIC;
  signal pcie_block_i_i_40_n_0 : STD_LOGIC;
  signal \^ppm_l1_thrtl\ : STD_LOGIC;
  signal \^ppm_l1_trig\ : STD_LOGIC;
  signal ppm_L23_thrtl : STD_LOGIC;
  signal ppm_L23_thrtl_i_1_n_0 : STD_LOGIC;
  signal ppm_L23_trig16_out : STD_LOGIC;
  signal reg_axi_in_pkt : STD_LOGIC;
  signal reg_axi_in_pkt_i_1_n_0 : STD_LOGIC;
  signal \^reg_tcfg_gnt\ : STD_LOGIC;
  signal reg_turnoff_ok : STD_LOGIC;
  signal reg_tx_ecrc_pkt : STD_LOGIC;
  signal reg_tx_ecrc_pkt08_out : STD_LOGIC;
  signal tbuf_av_d : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal tbuf_av_gap_thrtl : STD_LOGIC;
  signal tbuf_av_gap_thrtl_i_1_n_0 : STD_LOGIC;
  signal tbuf_av_min_thrtl : STD_LOGIC;
  signal \tbuf_gap_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \tbuf_gap_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \tbuf_gap_cnt[2]_i_1_n_0\ : STD_LOGIC;
  signal \tbuf_gap_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \tbuf_gap_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \tbuf_gap_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal tcfg_gnt_pending : STD_LOGIC;
  signal tcfg_gnt_pending_i_1_n_0 : STD_LOGIC;
  signal tcfg_req_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \tcfg_req_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \tcfg_req_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal tcfg_req_thrtl : STD_LOGIC;
  signal tcfg_req_thrtl_i_1_n_0 : STD_LOGIC;
  signal tready_thrtl_xhdl10 : STD_LOGIC;
  signal tready_thrtl_xhdl1_i_12_n_0 : STD_LOGIC;
  signal tready_thrtl_xhdl1_i_2_n_0 : STD_LOGIC;
  signal tready_thrtl_xhdl1_i_3_n_0 : STD_LOGIC;
  signal tready_thrtl_xhdl1_i_4_n_0 : STD_LOGIC;
  signal tready_thrtl_xhdl1_i_5_n_0 : STD_LOGIC;
  signal tready_thrtl_xhdl1_i_6_n_0 : STD_LOGIC;
  signal tready_thrtl_xhdl1_i_7_n_0 : STD_LOGIC;
  signal tready_thrtl_xhdl1_i_8_n_0 : STD_LOGIC;
  signal \^tready_thrtl_xhdl1_reg_0\ : STD_LOGIC;
  signal trn_tcfg_req_d : STD_LOGIC;
  signal trn_tdst_rdy_d : STD_LOGIC;
  signal \^xhdl12.xhdl14.xhdl15.reg_to_turnoff_reg_0\ : STD_LOGIC;
  signal \xhdl17.reg_tx_ecrc_pkt_i_1_n_0\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of cfg_turnoff_ok_pending_i_1 : label is "soft_lutpair125";
  attribute SOFT_HLUTNM of pcie_block_i_i_40 : label is "soft_lutpair126";
  attribute SOFT_HLUTNM of ppm_L23_thrtl_i_1 : label is "soft_lutpair125";
  attribute SOFT_HLUTNM of \tcfg_req_cnt[1]_i_1\ : label is "soft_lutpair124";
  attribute SOFT_HLUTNM of tcfg_req_thrtl_i_2 : label is "soft_lutpair124";
  attribute SOFT_HLUTNM of tready_thrtl_xhdl1_i_2 : label is "soft_lutpair126";
  attribute SOFT_HLUTNM of tready_thrtl_xhdl1_i_3 : label is "soft_lutpair127";
  attribute SOFT_HLUTNM of \xhdl17.reg_tx_ecrc_pkt_i_2\ : label is "soft_lutpair127";
begin
  cfg_pm_turnoff_ok_n <= \^cfg_pm_turnoff_ok_n\;
  lnk_up_thrtl <= \^lnk_up_thrtl\;
  ppm_L1_thrtl <= \^ppm_l1_thrtl\;
  ppm_L1_trig <= \^ppm_l1_trig\;
  reg_tcfg_gnt <= \^reg_tcfg_gnt\;
  tready_thrtl_xhdl1_reg_0 <= \^tready_thrtl_xhdl1_reg_0\;
  \xhdl12.xhdl14.xhdl15.reg_to_turnoff_reg_0\ <= \^xhdl12.xhdl14.xhdl15.reg_to_turnoff_reg_0\;
CUR_STATE_A_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5444545555555555"
    )
        port map (
      I0 => CUR_STATE_A_i_2_n_0,
      I1 => CUR_STATE_A,
      I2 => s_axis_tx_tlast,
      I3 => s_axis_tx_tvalid,
      I4 => reg_axi_in_pkt,
      I5 => \^tready_thrtl_xhdl1_reg_0\,
      O => NEXT_STATE_A
    );
CUR_STATE_A_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => tbuf_av_min_thrtl,
      I1 => \^ppm_l1_thrtl\,
      I2 => tbuf_av_gap_thrtl,
      I3 => tcfg_req_thrtl,
      I4 => ppm_L23_thrtl,
      I5 => \^lnk_up_thrtl\,
      O => CUR_STATE_A_i_2_n_0
    );
CUR_STATE_A_reg: unisim.vcomponents.FDSE
     port map (
      C => CLK,
      CE => '1',
      D => NEXT_STATE_A,
      Q => CUR_STATE_A,
      S => \tbuf_gap_cnt_reg[0]_0\
    );
axi_in_packet_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7F40"
    )
        port map (
      I0 => s_axis_tx_tlast,
      I1 => s_axis_tx_tvalid,
      I2 => \^tready_thrtl_xhdl1_reg_0\,
      I3 => axi_in_packet,
      O => s_axis_tx_tlast_0
    );
\cfg_pcie_link_state_d_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => cfg_pcie_link_state(0),
      Q => cfg_pcie_link_state_d(0),
      R => \tbuf_gap_cnt_reg[0]_0\
    );
\cfg_pcie_link_state_d_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => cfg_pcie_link_state(1),
      Q => cfg_pcie_link_state_d(1),
      R => \tbuf_gap_cnt_reg[0]_0\
    );
\cfg_pcie_link_state_d_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => cfg_pcie_link_state(2),
      Q => cfg_pcie_link_state_d(2),
      R => \tbuf_gap_cnt_reg[0]_0\
    );
cfg_turnoff_ok_pending_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF404040"
    )
        port map (
      I0 => ppm_L23_thrtl,
      I1 => reg_turnoff_ok,
      I2 => \^xhdl12.xhdl14.xhdl15.reg_to_turnoff_reg_0\,
      I3 => \^cfg_pm_turnoff_ok_n\,
      I4 => cfg_turnoff_ok_pending,
      O => cfg_turnoff_ok_pending_i_1_n_0
    );
cfg_turnoff_ok_pending_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => cfg_turnoff_ok_pending_i_1_n_0,
      Q => cfg_turnoff_ok_pending,
      R => \tbuf_gap_cnt_reg[0]_0\
    );
lnk_up_thrtl_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => lnk_up_thrtl_reg_0,
      Q => \^lnk_up_thrtl\,
      S => \tbuf_gap_cnt_reg[0]_0\
    );
pcie_block_i_i_26: unisim.vcomponents.LUT6
    generic map(
      INIT => X"DFDFDFDF5F505F5F"
    )
        port map (
      I0 => cfg_turnoff_ok_pending,
      I1 => tcfg_gnt_pending,
      I2 => CUR_STATE_A,
      I3 => pcie_block_i_i_40_n_0,
      I4 => ppm_L23_thrtl,
      I5 => tcfg_req_thrtl,
      O => \^cfg_pm_turnoff_ok_n\
    );
pcie_block_i_i_30: unisim.vcomponents.LUT4
    generic map(
      INIT => X"A202"
    )
        port map (
      I0 => tcfg_req_thrtl,
      I1 => pcie_block_i_i_40_n_0,
      I2 => CUR_STATE_A,
      I3 => tcfg_gnt_pending,
      O => trn_tcfg_gnt
    );
pcie_block_i_i_40: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF08A8"
    )
        port map (
      I0 => \^tready_thrtl_xhdl1_reg_0\,
      I1 => reg_axi_in_pkt,
      I2 => s_axis_tx_tvalid,
      I3 => s_axis_tx_tlast,
      I4 => CUR_STATE_A_i_2_n_0,
      O => pcie_block_i_i_40_n_0
    );
ppm_L1_thrtl_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000010000000000"
    )
        port map (
      I0 => cfg_pcie_link_state_d(1),
      I1 => cfg_pcie_link_state_d(2),
      I2 => cfg_pcie_link_state_d(0),
      I3 => cfg_pcie_link_state(0),
      I4 => cfg_pcie_link_state(1),
      I5 => cfg_pcie_link_state(2),
      O => \^ppm_l1_trig\
    );
ppm_L1_thrtl_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => ppm_L1_thrtl_reg_0,
      Q => \^ppm_l1_thrtl\,
      R => \tbuf_gap_cnt_reg[0]_0\
    );
ppm_L23_thrtl_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => \^xhdl12.xhdl14.xhdl15.reg_to_turnoff_reg_0\,
      I1 => reg_turnoff_ok,
      I2 => ppm_L23_thrtl,
      O => ppm_L23_thrtl_i_1_n_0
    );
ppm_L23_thrtl_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => ppm_L23_thrtl_i_1_n_0,
      Q => ppm_L23_thrtl,
      R => \tbuf_gap_cnt_reg[0]_0\
    );
reg_axi_in_pkt_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00005F40"
    )
        port map (
      I0 => s_axis_tx_tlast,
      I1 => \^tready_thrtl_xhdl1_reg_0\,
      I2 => s_axis_tx_tvalid,
      I3 => reg_axi_in_pkt,
      I4 => \tbuf_gap_cnt_reg[0]_0\,
      O => reg_axi_in_pkt_i_1_n_0
    );
reg_axi_in_pkt_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => reg_axi_in_pkt_i_1_n_0,
      Q => reg_axi_in_pkt,
      R => '0'
    );
reg_tcfg_gnt_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => tx_cfg_gnt,
      Q => \^reg_tcfg_gnt\,
      R => \tbuf_gap_cnt_reg[0]_0\
    );
\tbuf_av_d_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => trn_tbuf_av(0),
      Q => tbuf_av_d(0),
      R => \tbuf_gap_cnt_reg[0]_0\
    );
\tbuf_av_d_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => trn_tbuf_av(1),
      Q => tbuf_av_d(1),
      R => \tbuf_gap_cnt_reg[0]_0\
    );
\tbuf_av_d_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => trn_tbuf_av(2),
      Q => tbuf_av_d(2),
      R => \tbuf_gap_cnt_reg[0]_0\
    );
\tbuf_av_d_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => trn_tbuf_av(3),
      Q => tbuf_av_d(3),
      R => \tbuf_gap_cnt_reg[0]_0\
    );
\tbuf_av_d_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => trn_tbuf_av(4),
      Q => tbuf_av_d(4),
      R => \tbuf_gap_cnt_reg[0]_0\
    );
\tbuf_av_d_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => trn_tbuf_av(5),
      Q => tbuf_av_d(5),
      R => \tbuf_gap_cnt_reg[0]_0\
    );
tbuf_av_gap_thrtl_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FEFF00FF"
    )
        port map (
      I0 => \tbuf_gap_cnt_reg_n_0_[2]\,
      I1 => \tbuf_gap_cnt_reg_n_0_[0]\,
      I2 => \tbuf_gap_cnt_reg_n_0_[1]\,
      I3 => tready_thrtl_xhdl1_i_4_n_0,
      I4 => tbuf_av_gap_thrtl,
      O => tbuf_av_gap_thrtl_i_1_n_0
    );
tbuf_av_gap_thrtl_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => tbuf_av_gap_thrtl_i_1_n_0,
      Q => tbuf_av_gap_thrtl,
      R => \tbuf_gap_cnt_reg[0]_0\
    );
tbuf_av_min_thrtl_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => tbuf_av_min_trig,
      Q => tbuf_av_min_thrtl,
      R => \tbuf_gap_cnt_reg[0]_0\
    );
\tbuf_gap_cnt[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"32FFFFFF"
    )
        port map (
      I0 => \tbuf_gap_cnt_reg_n_0_[1]\,
      I1 => \tbuf_gap_cnt_reg_n_0_[0]\,
      I2 => \tbuf_gap_cnt_reg_n_0_[2]\,
      I3 => tbuf_av_gap_thrtl,
      I4 => CUR_STATE_A,
      O => \tbuf_gap_cnt[0]_i_1_n_0\
    );
\tbuf_gap_cnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000098000000"
    )
        port map (
      I0 => \tbuf_gap_cnt_reg_n_0_[1]\,
      I1 => \tbuf_gap_cnt_reg_n_0_[0]\,
      I2 => \tbuf_gap_cnt_reg_n_0_[2]\,
      I3 => CUR_STATE_A,
      I4 => tbuf_av_gap_thrtl,
      I5 => \tbuf_gap_cnt_reg[0]_0\,
      O => \tbuf_gap_cnt[1]_i_1_n_0\
    );
\tbuf_gap_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000E0000000"
    )
        port map (
      I0 => \tbuf_gap_cnt_reg_n_0_[1]\,
      I1 => \tbuf_gap_cnt_reg_n_0_[0]\,
      I2 => \tbuf_gap_cnt_reg_n_0_[2]\,
      I3 => CUR_STATE_A,
      I4 => tbuf_av_gap_thrtl,
      I5 => \tbuf_gap_cnt_reg[0]_0\,
      O => \tbuf_gap_cnt[2]_i_1_n_0\
    );
\tbuf_gap_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \tbuf_gap_cnt[0]_i_1_n_0\,
      Q => \tbuf_gap_cnt_reg_n_0_[0]\,
      R => \tbuf_gap_cnt_reg[0]_0\
    );
\tbuf_gap_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \tbuf_gap_cnt[1]_i_1_n_0\,
      Q => \tbuf_gap_cnt_reg_n_0_[1]\,
      R => '0'
    );
\tbuf_gap_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \tbuf_gap_cnt[2]_i_1_n_0\,
      Q => \tbuf_gap_cnt_reg_n_0_[2]\,
      R => '0'
    );
tcfg_gnt_pending_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"44F44444F4F4F4F4"
    )
        port map (
      I0 => trn_tcfg_req_d,
      I1 => trn_tcfg_req,
      I2 => tcfg_gnt_pending,
      I3 => CUR_STATE_A,
      I4 => pcie_block_i_i_40_n_0,
      I5 => tcfg_req_thrtl,
      O => tcfg_gnt_pending_i_1_n_0
    );
tcfg_gnt_pending_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => tcfg_gnt_pending_i_1_n_0,
      Q => tcfg_gnt_pending,
      R => \tbuf_gap_cnt_reg[0]_0\
    );
\tcfg_req_cnt[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000D00"
    )
        port map (
      I0 => trn_tcfg_req,
      I1 => trn_tcfg_req_d,
      I2 => tcfg_gnt_pending,
      I3 => tcfg_req_cnt(1),
      I4 => tcfg_req_cnt(0),
      I5 => \tbuf_gap_cnt_reg[0]_0\,
      O => \tcfg_req_cnt[0]_i_1_n_0\
    );
\tcfg_req_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF88F8"
    )
        port map (
      I0 => tcfg_req_cnt(0),
      I1 => tcfg_req_cnt(1),
      I2 => trn_tcfg_req,
      I3 => trn_tcfg_req_d,
      I4 => tcfg_gnt_pending,
      O => \tcfg_req_cnt[1]_i_1_n_0\
    );
\tcfg_req_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \tcfg_req_cnt[0]_i_1_n_0\,
      Q => tcfg_req_cnt(0),
      R => '0'
    );
\tcfg_req_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \tcfg_req_cnt[1]_i_1_n_0\,
      Q => tcfg_req_cnt(1),
      R => \tbuf_gap_cnt_reg[0]_0\
    );
tcfg_req_thrtl_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF8FF88888888"
    )
        port map (
      I0 => \^reg_tcfg_gnt\,
      I1 => trn_tcfg_req,
      I2 => trn_tdst_rdy_d,
      I3 => trn_tdst_rdy,
      I4 => gtOp,
      I5 => tcfg_req_thrtl,
      O => tcfg_req_thrtl_i_1_n_0
    );
tcfg_req_thrtl_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => tcfg_req_cnt(1),
      I1 => tcfg_req_cnt(0),
      O => gtOp
    );
tcfg_req_thrtl_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => tcfg_req_thrtl_i_1_n_0,
      Q => tcfg_req_thrtl,
      R => \tbuf_gap_cnt_reg[0]_0\
    );
tready_thrtl_xhdl1_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5757575700005700"
    )
        port map (
      I0 => tready_thrtl_xhdl1_i_2_n_0,
      I1 => reg_tx_ecrc_pkt,
      I2 => tready_thrtl_xhdl1_i_3_n_0,
      I3 => tready_thrtl_xhdl1_i_4_n_0,
      I4 => tready_thrtl_xhdl1_i_5_n_0,
      I5 => tready_thrtl_xhdl1_i_6_n_0,
      O => tready_thrtl_xhdl10
    );
tready_thrtl_xhdl1_i_12: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => tbuf_av_d(0),
      I1 => tbuf_av_d(2),
      I2 => tbuf_av_d(5),
      I3 => tbuf_av_d(3),
      O => tready_thrtl_xhdl1_i_12_n_0
    );
tready_thrtl_xhdl1_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \^tready_thrtl_xhdl1_reg_0\,
      I1 => s_axis_tx_tvalid,
      I2 => s_axis_tx_tlast,
      O => tready_thrtl_xhdl1_i_2_n_0
    );
tready_thrtl_xhdl1_i_3: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0078"
    )
        port map (
      I0 => s_axis_tx_tdata(0),
      I1 => s_axis_tx_tdata(3),
      I2 => s_axis_tx_tdata(2),
      I3 => tready_thrtl_xhdl1_i_7_n_0,
      O => tready_thrtl_xhdl1_i_3_n_0
    );
tready_thrtl_xhdl1_i_4: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FFEFFFFF"
    )
        port map (
      I0 => tcfg_req_cnt(0),
      I1 => tcfg_req_cnt(1),
      I2 => trn_tdst_rdy,
      I3 => trn_tdst_rdy_d,
      I4 => tcfg_req_thrtl,
      I5 => tready_thrtl_xhdl1_i_8_n_0,
      O => tready_thrtl_xhdl1_i_4_n_0
    );
tready_thrtl_xhdl1_i_5: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFEFFFFF"
    )
        port map (
      I0 => tbuf_av_min_trig,
      I1 => \^ppm_l1_trig\,
      I2 => CUR_STATE_A_i_2_n_0,
      I3 => ppm_L23_trig16_out,
      I4 => \out\,
      I5 => tcfg_req_trig,
      O => tready_thrtl_xhdl1_i_5_n_0
    );
tready_thrtl_xhdl1_i_6: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000008A8"
    )
        port map (
      I0 => \^tready_thrtl_xhdl1_reg_0\,
      I1 => reg_axi_in_pkt,
      I2 => s_axis_tx_tvalid,
      I3 => s_axis_tx_tlast,
      I4 => CUR_STATE_A,
      O => tready_thrtl_xhdl1_i_6_n_0
    );
tready_thrtl_xhdl1_i_7: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFDFFF"
    )
        port map (
      I0 => s_axis_tx_tuser(0),
      I1 => reg_axi_in_pkt,
      I2 => s_axis_tx_tvalid,
      I3 => \^tready_thrtl_xhdl1_reg_0\,
      I4 => s_axis_tx_tdata(1),
      O => tready_thrtl_xhdl1_i_7_n_0
    );
tready_thrtl_xhdl1_i_8: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAA00002000"
    )
        port map (
      I0 => tready_thrtl_xhdl1_i_4_0,
      I1 => tbuf_av_d(4),
      I2 => trn_tbuf_av(1),
      I3 => tbuf_av_d(1),
      I4 => tready_thrtl_xhdl1_i_12_n_0,
      I5 => tready_thrtl_xhdl1_i_2_n_0,
      O => tready_thrtl_xhdl1_i_8_n_0
    );
tready_thrtl_xhdl1_i_9: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => reg_turnoff_ok,
      I1 => \^xhdl12.xhdl14.xhdl15.reg_to_turnoff_reg_0\,
      O => ppm_L23_trig16_out
    );
tready_thrtl_xhdl1_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => tready_thrtl_xhdl10,
      Q => \^tready_thrtl_xhdl1_reg_0\,
      R => \tbuf_gap_cnt_reg[0]_0\
    );
trn_tcfg_req_d_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => trn_tcfg_req,
      Q => trn_tcfg_req_d,
      R => \tbuf_gap_cnt_reg[0]_0\
    );
trn_tdst_rdy_d_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => trn_tdst_rdy,
      Q => trn_tdst_rdy_d,
      S => \tbuf_gap_cnt_reg[0]_0\
    );
\xhdl12.reg_tsrc_rdy_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0080"
    )
        port map (
      I0 => \^tready_thrtl_xhdl1_reg_0\,
      I1 => s_axis_tx_tvalid,
      I2 => \out\,
      I3 => reg_disable_trn,
      O => reg_tsrc_rdy0
    );
\xhdl12.xhdl14.reg_turnoff_ok_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => cfg_turnoff_ok,
      Q => reg_turnoff_ok,
      R => \tbuf_gap_cnt_reg[0]_0\
    );
\xhdl12.xhdl14.xhdl15.reg_to_turnoff_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \xhdl12.xhdl14.xhdl15.reg_to_turnoff_reg_1\,
      Q => \^xhdl12.xhdl14.xhdl15.reg_to_turnoff_reg_0\,
      R => \tbuf_gap_cnt_reg[0]_0\
    );
\xhdl17.reg_tx_ecrc_pkt_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF7FFF00"
    )
        port map (
      I0 => s_axis_tx_tlast,
      I1 => s_axis_tx_tvalid,
      I2 => \^tready_thrtl_xhdl1_reg_0\,
      I3 => reg_tx_ecrc_pkt08_out,
      I4 => reg_tx_ecrc_pkt,
      O => \xhdl17.reg_tx_ecrc_pkt_i_1_n_0\
    );
\xhdl17.reg_tx_ecrc_pkt_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001444"
    )
        port map (
      I0 => tready_thrtl_xhdl1_i_7_n_0,
      I1 => s_axis_tx_tdata(2),
      I2 => s_axis_tx_tdata(3),
      I3 => s_axis_tx_tdata(0),
      I4 => s_axis_tx_tlast,
      O => reg_tx_ecrc_pkt08_out
    );
\xhdl17.reg_tx_ecrc_pkt_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \xhdl17.reg_tx_ecrc_pkt_i_1_n_0\,
      Q => reg_tx_ecrc_pkt,
      R => \tbuf_gap_cnt_reg[0]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_gt_rx_valid_filter_7x is
  port (
    gt_rxvalid_q_reg_0 : out STD_LOGIC;
    pipe_rx0_elec_idle : out STD_LOGIC;
    pipe_rx0_phy_status : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \FSM_onehot_reg_state_eios_det_reg[5]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    \FSM_onehot_reg_state_eios_det_reg[3]_0\ : out STD_LOGIC;
    \pl_ltssm_state_q_reg[5]\ : out STD_LOGIC;
    pipe_rx0_char_is_k : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rx_status_q_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxvalid_q : in STD_LOGIC;
    gt_rx_phy_status_q_reg_0 : in STD_LOGIC;
    SYNC_RXELECIDLE : in STD_LOGIC;
    PIPE_PHYSTATUS : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gt_rx_status_q_reg[2]_1\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    D : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rxcharisk_q_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rx_status_q_reg[2]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_gt_rx_valid_filter_7x : entity is "spec7_pcie_7x_0_gt_rx_valid_filter_7x";
end spec7_pcie_7x_0_spec7_pcie_7x_0_gt_rx_valid_filter_7x;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_gt_rx_valid_filter_7x is
  signal \FSM_onehot_reg_state_eios_det[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_reg_state_eios_det[1]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_reg_state_eios_det[1]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_reg_state_eios_det[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_reg_state_eios_det[2]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_reg_state_eios_det[2]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_reg_state_eios_det[2]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_reg_state_eios_det[3]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_reg_state_eios_det[3]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_reg_state_eios_det[3]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_reg_state_eios_det[5]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_reg_state_eios_det[5]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_reg_state_eios_det[5]_i_3_n_0\ : STD_LOGIC;
  signal \^fsm_onehot_reg_state_eios_det_reg[5]_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \FSM_onehot_reg_state_eios_det_reg_n_0_[1]\ : STD_LOGIC;
  signal \FSM_onehot_reg_state_eios_det_reg_n_0_[2]\ : STD_LOGIC;
  signal \FSM_onehot_reg_state_eios_det_reg_n_0_[3]\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \gt_rxcharisk_q_reg_n_0_[0]\ : STD_LOGIC;
  signal \^gt_rxvalid_q_reg_0\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal reg_symbol_after_eios_i_1_n_0 : STD_LOGIC;
  signal symbol_after_eios : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_reg_state_eios_det[1]_i_3\ : label is "soft_lutpair2";
  attribute SOFT_HLUTNM of \FSM_onehot_reg_state_eios_det[2]_i_1\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \FSM_onehot_reg_state_eios_det[2]_i_4\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \FSM_onehot_reg_state_eios_det[3]_i_1\ : label is "soft_lutpair0";
  attribute SOFT_HLUTNM of \FSM_onehot_reg_state_eios_det[3]_i_3\ : label is "soft_lutpair3";
  attribute SOFT_HLUTNM of \FSM_onehot_reg_state_eios_det[5]_i_1\ : label is "soft_lutpair2";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_reg_state_eios_det_reg[1]\ : label is "eios_det_no_str0:000100,eios_det_str0:001000,eios_det_str1:010000,eios_det_idl:000010,eios_det_done:100000,iSTATE:000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_reg_state_eios_det_reg[2]\ : label is "eios_det_no_str0:000100,eios_det_str0:001000,eios_det_str1:010000,eios_det_idl:000010,eios_det_done:100000,iSTATE:000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_reg_state_eios_det_reg[3]\ : label is "eios_det_no_str0:000100,eios_det_str0:001000,eios_det_str1:010000,eios_det_idl:000010,eios_det_done:100000,iSTATE:000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_reg_state_eios_det_reg[5]\ : label is "eios_det_no_str0:000100,eios_det_str0:001000,eios_det_str1:010000,eios_det_idl:000010,eios_det_done:100000,iSTATE:000001";
  attribute SOFT_HLUTNM of pcie_block_i_i_32 : label is "soft_lutpair1";
  attribute SOFT_HLUTNM of pcie_block_i_i_33 : label is "soft_lutpair1";
begin
  \FSM_onehot_reg_state_eios_det_reg[5]_0\(0) <= \^fsm_onehot_reg_state_eios_det_reg[5]_0\(0);
  Q(15 downto 0) <= \^q\(15 downto 0);
  gt_rxvalid_q_reg_0 <= \^gt_rxvalid_q_reg_0\;
\FSM_onehot_reg_state_eios_det[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF55555455"
    )
        port map (
      I0 => \FSM_onehot_reg_state_eios_det[3]_i_3_n_0\,
      I1 => \FSM_onehot_reg_state_eios_det[3]_i_2_n_0\,
      I2 => \^q\(9),
      I3 => \^q\(15),
      I4 => \^q\(14),
      I5 => \FSM_onehot_reg_state_eios_det[1]_i_2_n_0\,
      O => \FSM_onehot_reg_state_eios_det[1]_i_1_n_0\
    );
\FSM_onehot_reg_state_eios_det[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFC5CCFFFFF5FC"
    )
        port map (
      I0 => \FSM_onehot_reg_state_eios_det_reg_n_0_[1]\,
      I1 => \FSM_onehot_reg_state_eios_det[5]_i_2_n_0\,
      I2 => \FSM_onehot_reg_state_eios_det_reg_n_0_[3]\,
      I3 => \FSM_onehot_reg_state_eios_det[1]_i_3_n_0\,
      I4 => \^fsm_onehot_reg_state_eios_det_reg[5]_0\(0),
      I5 => \FSM_onehot_reg_state_eios_det[2]_i_4_n_0\,
      O => \FSM_onehot_reg_state_eios_det[1]_i_2_n_0\
    );
\FSM_onehot_reg_state_eios_det[1]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => symbol_after_eios,
      I1 => \FSM_onehot_reg_state_eios_det_reg_n_0_[2]\,
      O => \FSM_onehot_reg_state_eios_det[1]_i_3_n_0\
    );
\FSM_onehot_reg_state_eios_det[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \FSM_onehot_reg_state_eios_det_reg_n_0_[1]\,
      I1 => \FSM_onehot_reg_state_eios_det[2]_i_2_n_0\,
      O => \FSM_onehot_reg_state_eios_det[2]_i_1_n_0\
    );
\FSM_onehot_reg_state_eios_det[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \FSM_onehot_reg_state_eios_det[2]_i_3_n_0\,
      I1 => \^q\(3),
      I2 => \^q\(5),
      I3 => \^q\(2),
      I4 => \^q\(4),
      I5 => \FSM_onehot_reg_state_eios_det[2]_i_4_n_0\,
      O => \FSM_onehot_reg_state_eios_det[2]_i_2_n_0\
    );
\FSM_onehot_reg_state_eios_det[2]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFDFFFF"
    )
        port map (
      I0 => \gt_rxcharisk_q_reg_n_0_[0]\,
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \^q\(6),
      I4 => \^q\(7),
      O => \FSM_onehot_reg_state_eios_det[2]_i_3_n_0\
    );
\FSM_onehot_reg_state_eios_det[2]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0004"
    )
        port map (
      I0 => \^q\(15),
      I1 => \^q\(14),
      I2 => \^q\(9),
      I3 => \FSM_onehot_reg_state_eios_det[3]_i_2_n_0\,
      O => \FSM_onehot_reg_state_eios_det[2]_i_4_n_0\
    );
\FSM_onehot_reg_state_eios_det[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000004"
    )
        port map (
      I0 => \^q\(14),
      I1 => \^q\(15),
      I2 => \^q\(9),
      I3 => \FSM_onehot_reg_state_eios_det[3]_i_2_n_0\,
      I4 => \FSM_onehot_reg_state_eios_det[3]_i_3_n_0\,
      O => \FSM_onehot_reg_state_eios_det[3]_i_1_n_0\
    );
\FSM_onehot_reg_state_eios_det[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \^q\(8),
      I1 => p_0_in,
      I2 => \^q\(13),
      I3 => \^q\(12),
      I4 => \^q\(11),
      I5 => \^q\(10),
      O => \FSM_onehot_reg_state_eios_det[3]_i_2_n_0\
    );
\FSM_onehot_reg_state_eios_det[3]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \FSM_onehot_reg_state_eios_det_reg_n_0_[1]\,
      I1 => \FSM_onehot_reg_state_eios_det[2]_i_2_n_0\,
      O => \FSM_onehot_reg_state_eios_det[3]_i_3_n_0\
    );
\FSM_onehot_reg_state_eios_det[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"54"
    )
        port map (
      I0 => \FSM_onehot_reg_state_eios_det[5]_i_2_n_0\,
      I1 => \FSM_onehot_reg_state_eios_det_reg_n_0_[2]\,
      I2 => symbol_after_eios,
      O => \FSM_onehot_reg_state_eios_det[5]_i_1_n_0\
    );
\FSM_onehot_reg_state_eios_det[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFEFFFFFFFFF"
    )
        port map (
      I0 => \FSM_onehot_reg_state_eios_det[5]_i_3_n_0\,
      I1 => \^q\(7),
      I2 => \^q\(6),
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => \gt_rxcharisk_q_reg_n_0_[0]\,
      O => \FSM_onehot_reg_state_eios_det[5]_i_2_n_0\
    );
\FSM_onehot_reg_state_eios_det[5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(5),
      I2 => \^q\(2),
      I3 => \^q\(4),
      O => \FSM_onehot_reg_state_eios_det[5]_i_3_n_0\
    );
\FSM_onehot_reg_state_eios_det_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_rx_phy_status_q_reg_0,
      CE => '1',
      D => \FSM_onehot_reg_state_eios_det[1]_i_1_n_0\,
      Q => \FSM_onehot_reg_state_eios_det_reg_n_0_[1]\,
      S => SR(0)
    );
\FSM_onehot_reg_state_eios_det_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_rx_phy_status_q_reg_0,
      CE => '1',
      D => \FSM_onehot_reg_state_eios_det[2]_i_1_n_0\,
      Q => \FSM_onehot_reg_state_eios_det_reg_n_0_[2]\,
      R => SR(0)
    );
\FSM_onehot_reg_state_eios_det_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_rx_phy_status_q_reg_0,
      CE => '1',
      D => \FSM_onehot_reg_state_eios_det[3]_i_1_n_0\,
      Q => \FSM_onehot_reg_state_eios_det_reg_n_0_[3]\,
      R => SR(0)
    );
\FSM_onehot_reg_state_eios_det_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_rx_phy_status_q_reg_0,
      CE => '1',
      D => \FSM_onehot_reg_state_eios_det[5]_i_1_n_0\,
      Q => \^fsm_onehot_reg_state_eios_det_reg[5]_0\(0),
      R => SR(0)
    );
gt_rx_phy_status_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_rx_phy_status_q_reg_0,
      CE => '1',
      D => PIPE_PHYSTATUS(0),
      Q => pipe_rx0_phy_status,
      R => SR(0)
    );
\gt_rx_status_q_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_rx_phy_status_q_reg_0,
      CE => '1',
      D => \gt_rx_status_q_reg[2]_2\(0),
      Q => \gt_rx_status_q_reg[2]_0\(0),
      R => SR(0)
    );
\gt_rx_status_q_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_rx_phy_status_q_reg_0,
      CE => '1',
      D => \gt_rx_status_q_reg[2]_2\(1),
      Q => \gt_rx_status_q_reg[2]_0\(1),
      R => SR(0)
    );
\gt_rx_status_q_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_rx_phy_status_q_reg_0,
      CE => '1',
      D => \gt_rx_status_q_reg[2]_2\(2),
      Q => \gt_rx_status_q_reg[2]_0\(2),
      R => SR(0)
    );
\gt_rxcharisk_q_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_rx_phy_status_q_reg_0,
      CE => '1',
      D => \gt_rxcharisk_q_reg[1]_0\(0),
      Q => \gt_rxcharisk_q_reg_n_0_[0]\,
      R => SR(0)
    );
\gt_rxcharisk_q_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_rx_phy_status_q_reg_0,
      CE => '1',
      D => \gt_rxcharisk_q_reg[1]_0\(1),
      Q => p_0_in,
      R => SR(0)
    );
\gt_rxdata_q_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_rx_phy_status_q_reg_0,
      CE => '1',
      D => D(0),
      Q => \^q\(0),
      R => SR(0)
    );
\gt_rxdata_q_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_rx_phy_status_q_reg_0,
      CE => '1',
      D => D(10),
      Q => \^q\(10),
      R => SR(0)
    );
\gt_rxdata_q_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_rx_phy_status_q_reg_0,
      CE => '1',
      D => D(11),
      Q => \^q\(11),
      R => SR(0)
    );
\gt_rxdata_q_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_rx_phy_status_q_reg_0,
      CE => '1',
      D => D(12),
      Q => \^q\(12),
      R => SR(0)
    );
\gt_rxdata_q_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_rx_phy_status_q_reg_0,
      CE => '1',
      D => D(13),
      Q => \^q\(13),
      R => SR(0)
    );
\gt_rxdata_q_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_rx_phy_status_q_reg_0,
      CE => '1',
      D => D(14),
      Q => \^q\(14),
      R => SR(0)
    );
\gt_rxdata_q_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_rx_phy_status_q_reg_0,
      CE => '1',
      D => D(15),
      Q => \^q\(15),
      R => SR(0)
    );
\gt_rxdata_q_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_rx_phy_status_q_reg_0,
      CE => '1',
      D => D(1),
      Q => \^q\(1),
      R => SR(0)
    );
\gt_rxdata_q_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_rx_phy_status_q_reg_0,
      CE => '1',
      D => D(2),
      Q => \^q\(2),
      R => SR(0)
    );
\gt_rxdata_q_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_rx_phy_status_q_reg_0,
      CE => '1',
      D => D(3),
      Q => \^q\(3),
      R => SR(0)
    );
\gt_rxdata_q_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_rx_phy_status_q_reg_0,
      CE => '1',
      D => D(4),
      Q => \^q\(4),
      R => SR(0)
    );
\gt_rxdata_q_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_rx_phy_status_q_reg_0,
      CE => '1',
      D => D(5),
      Q => \^q\(5),
      R => SR(0)
    );
\gt_rxdata_q_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_rx_phy_status_q_reg_0,
      CE => '1',
      D => D(6),
      Q => \^q\(6),
      R => SR(0)
    );
\gt_rxdata_q_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_rx_phy_status_q_reg_0,
      CE => '1',
      D => D(7),
      Q => \^q\(7),
      R => SR(0)
    );
\gt_rxdata_q_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_rx_phy_status_q_reg_0,
      CE => '1',
      D => D(8),
      Q => \^q\(8),
      R => SR(0)
    );
\gt_rxdata_q_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_rx_phy_status_q_reg_0,
      CE => '1',
      D => D(9),
      Q => \^q\(9),
      R => SR(0)
    );
gt_rxelecidle_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_rx_phy_status_q_reg_0,
      CE => '1',
      D => SYNC_RXELECIDLE,
      Q => pipe_rx0_elec_idle,
      R => SR(0)
    );
gt_rxvalid_q_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFF74"
    )
        port map (
      I0 => \FSM_onehot_reg_state_eios_det[2]_i_4_n_0\,
      I1 => \FSM_onehot_reg_state_eios_det_reg_n_0_[3]\,
      I2 => \FSM_onehot_reg_state_eios_det[1]_i_3_n_0\,
      I3 => \FSM_onehot_reg_state_eios_det_reg_n_0_[1]\,
      I4 => \^fsm_onehot_reg_state_eios_det_reg[5]_0\(0),
      I5 => \FSM_onehot_reg_state_eios_det[5]_i_2_n_0\,
      O => \FSM_onehot_reg_state_eios_det_reg[3]_0\
    );
\gt_rxvalid_q_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \gt_rx_status_q_reg[2]_1\(5),
      I1 => \gt_rx_status_q_reg[2]_1\(0),
      I2 => \gt_rx_status_q_reg[2]_1\(3),
      I3 => \gt_rx_status_q_reg[2]_1\(2),
      I4 => \gt_rx_status_q_reg[2]_1\(1),
      I5 => \gt_rx_status_q_reg[2]_1\(4),
      O => \pl_ltssm_state_q_reg[5]\
    );
gt_rxvalid_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_rx_phy_status_q_reg_0,
      CE => '1',
      D => gt_rxvalid_q,
      Q => \^gt_rxvalid_q_reg_0\,
      R => SR(0)
    );
pcie_block_i_i_32: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => p_0_in,
      I1 => \^gt_rxvalid_q_reg_0\,
      I2 => symbol_after_eios,
      O => pipe_rx0_char_is_k(1)
    );
pcie_block_i_i_33: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^gt_rxvalid_q_reg_0\,
      I1 => \gt_rxcharisk_q_reg_n_0_[0]\,
      O => pipe_rx0_char_is_k(0)
    );
reg_symbol_after_eios_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000001000000000"
    )
        port map (
      I0 => \FSM_onehot_reg_state_eios_det[5]_i_2_n_0\,
      I1 => \^q\(15),
      I2 => \^q\(14),
      I3 => \^q\(9),
      I4 => \FSM_onehot_reg_state_eios_det[3]_i_2_n_0\,
      I5 => \FSM_onehot_reg_state_eios_det_reg_n_0_[3]\,
      O => reg_symbol_after_eios_i_1_n_0
    );
reg_symbol_after_eios_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_rx_phy_status_q_reg_0,
      CE => '1',
      D => reg_symbol_after_eios_i_1_n_0,
      Q => symbol_after_eios,
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_gt_rx_valid_filter_7x_15 is
  port (
    gt_rxvalid_q_reg_0 : out STD_LOGIC;
    pipe_rx1_elec_idle : out STD_LOGIC;
    pipe_rx1_phy_status : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_rx1_char_is_k : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rx_status_q_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gt_rx_status_q_reg[2]_1\ : in STD_LOGIC;
    SYNC_RXELECIDLE : in STD_LOGIC;
    PIPE_PHYSTATUS : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxvalid_q_reg_1 : in STD_LOGIC;
    gt_rxvalid_q_reg_2 : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rxcharisk_q_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \gt_rx_status_q_reg[2]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_gt_rx_valid_filter_7x_15 : entity is "spec7_pcie_7x_0_gt_rx_valid_filter_7x";
end spec7_pcie_7x_0_spec7_pcie_7x_0_gt_rx_valid_filter_7x_15;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_gt_rx_valid_filter_7x_15 is
  signal \FSM_onehot_reg_state_eios_det[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_reg_state_eios_det[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_reg_state_eios_det[1]_i_3__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_reg_state_eios_det[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_reg_state_eios_det[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_reg_state_eios_det[2]_i_3__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_reg_state_eios_det[2]_i_4__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_reg_state_eios_det[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_reg_state_eios_det[3]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_reg_state_eios_det[3]_i_3__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_reg_state_eios_det[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_reg_state_eios_det[5]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_reg_state_eios_det[5]_i_3__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_reg_state_eios_det_reg_n_0_[1]\ : STD_LOGIC;
  signal \FSM_onehot_reg_state_eios_det_reg_n_0_[2]\ : STD_LOGIC;
  signal \FSM_onehot_reg_state_eios_det_reg_n_0_[3]\ : STD_LOGIC;
  signal \FSM_onehot_reg_state_eios_det_reg_n_0_[5]\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \gt_rxcharisk_q_reg_n_0_[0]\ : STD_LOGIC;
  signal gt_rxvalid_q : STD_LOGIC;
  signal gt_rxvalid_q_i_3_n_0 : STD_LOGIC;
  signal \gt_rxvalid_q_i_4__0_n_0\ : STD_LOGIC;
  signal \^gt_rxvalid_q_reg_0\ : STD_LOGIC;
  signal p_0_in : STD_LOGIC;
  signal \reg_symbol_after_eios_i_1__0_n_0\ : STD_LOGIC;
  signal symbol_after_eios : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_reg_state_eios_det[1]_i_3__0\ : label is "soft_lutpair6";
  attribute SOFT_HLUTNM of \FSM_onehot_reg_state_eios_det[2]_i_1__0\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \FSM_onehot_reg_state_eios_det[2]_i_4__0\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \FSM_onehot_reg_state_eios_det[3]_i_1__0\ : label is "soft_lutpair4";
  attribute SOFT_HLUTNM of \FSM_onehot_reg_state_eios_det[3]_i_3__0\ : label is "soft_lutpair7";
  attribute SOFT_HLUTNM of \FSM_onehot_reg_state_eios_det[5]_i_1__0\ : label is "soft_lutpair6";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_reg_state_eios_det_reg[1]\ : label is "eios_det_no_str0:000100,eios_det_str0:001000,eios_det_str1:010000,eios_det_idl:000010,eios_det_done:100000,iSTATE:000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_reg_state_eios_det_reg[2]\ : label is "eios_det_no_str0:000100,eios_det_str0:001000,eios_det_str1:010000,eios_det_idl:000010,eios_det_done:100000,iSTATE:000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_reg_state_eios_det_reg[3]\ : label is "eios_det_no_str0:000100,eios_det_str0:001000,eios_det_str1:010000,eios_det_idl:000010,eios_det_done:100000,iSTATE:000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_reg_state_eios_det_reg[5]\ : label is "eios_det_no_str0:000100,eios_det_str0:001000,eios_det_str1:010000,eios_det_idl:000010,eios_det_done:100000,iSTATE:000001";
  attribute SOFT_HLUTNM of pcie_block_i_i_34 : label is "soft_lutpair5";
  attribute SOFT_HLUTNM of pcie_block_i_i_35 : label is "soft_lutpair5";
begin
  Q(15 downto 0) <= \^q\(15 downto 0);
  gt_rxvalid_q_reg_0 <= \^gt_rxvalid_q_reg_0\;
\FSM_onehot_reg_state_eios_det[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF55555155"
    )
        port map (
      I0 => \FSM_onehot_reg_state_eios_det[3]_i_3__0_n_0\,
      I1 => \FSM_onehot_reg_state_eios_det[3]_i_2__0_n_0\,
      I2 => \^q\(9),
      I3 => \^q\(15),
      I4 => \^q\(14),
      I5 => \FSM_onehot_reg_state_eios_det[1]_i_2__0_n_0\,
      O => \FSM_onehot_reg_state_eios_det[1]_i_1__0_n_0\
    );
\FSM_onehot_reg_state_eios_det[1]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFC5CCFFFFF5FC"
    )
        port map (
      I0 => \FSM_onehot_reg_state_eios_det_reg_n_0_[1]\,
      I1 => \FSM_onehot_reg_state_eios_det[5]_i_2__0_n_0\,
      I2 => \FSM_onehot_reg_state_eios_det_reg_n_0_[3]\,
      I3 => \FSM_onehot_reg_state_eios_det[1]_i_3__0_n_0\,
      I4 => \FSM_onehot_reg_state_eios_det_reg_n_0_[5]\,
      I5 => \FSM_onehot_reg_state_eios_det[2]_i_4__0_n_0\,
      O => \FSM_onehot_reg_state_eios_det[1]_i_2__0_n_0\
    );
\FSM_onehot_reg_state_eios_det[1]_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => symbol_after_eios,
      I1 => \FSM_onehot_reg_state_eios_det_reg_n_0_[2]\,
      O => \FSM_onehot_reg_state_eios_det[1]_i_3__0_n_0\
    );
\FSM_onehot_reg_state_eios_det[2]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \FSM_onehot_reg_state_eios_det_reg_n_0_[1]\,
      I1 => \FSM_onehot_reg_state_eios_det[2]_i_2__0_n_0\,
      O => \FSM_onehot_reg_state_eios_det[2]_i_1__0_n_0\
    );
\FSM_onehot_reg_state_eios_det[2]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BFFFFFFFFFFFFFFF"
    )
        port map (
      I0 => \FSM_onehot_reg_state_eios_det[2]_i_3__0_n_0\,
      I1 => \^q\(3),
      I2 => \^q\(5),
      I3 => \^q\(2),
      I4 => \^q\(4),
      I5 => \FSM_onehot_reg_state_eios_det[2]_i_4__0_n_0\,
      O => \FSM_onehot_reg_state_eios_det[2]_i_2__0_n_0\
    );
\FSM_onehot_reg_state_eios_det[2]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFDFFFF"
    )
        port map (
      I0 => \gt_rxcharisk_q_reg_n_0_[0]\,
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => \^q\(6),
      I4 => \^q\(7),
      O => \FSM_onehot_reg_state_eios_det[2]_i_3__0_n_0\
    );
\FSM_onehot_reg_state_eios_det[2]_i_4__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0020"
    )
        port map (
      I0 => \FSM_onehot_reg_state_eios_det[3]_i_2__0_n_0\,
      I1 => \^q\(9),
      I2 => \^q\(14),
      I3 => \^q\(15),
      O => \FSM_onehot_reg_state_eios_det[2]_i_4__0_n_0\
    );
\FSM_onehot_reg_state_eios_det[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000400"
    )
        port map (
      I0 => \^q\(14),
      I1 => \^q\(15),
      I2 => \^q\(9),
      I3 => \FSM_onehot_reg_state_eios_det[3]_i_2__0_n_0\,
      I4 => \FSM_onehot_reg_state_eios_det[3]_i_3__0_n_0\,
      O => \FSM_onehot_reg_state_eios_det[3]_i_1__0_n_0\
    );
\FSM_onehot_reg_state_eios_det[3]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0800000000000000"
    )
        port map (
      I0 => \^q\(11),
      I1 => \^q\(10),
      I2 => \^q\(8),
      I3 => p_0_in,
      I4 => \^q\(13),
      I5 => \^q\(12),
      O => \FSM_onehot_reg_state_eios_det[3]_i_2__0_n_0\
    );
\FSM_onehot_reg_state_eios_det[3]_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \FSM_onehot_reg_state_eios_det_reg_n_0_[1]\,
      I1 => \FSM_onehot_reg_state_eios_det[2]_i_2__0_n_0\,
      O => \FSM_onehot_reg_state_eios_det[3]_i_3__0_n_0\
    );
\FSM_onehot_reg_state_eios_det[5]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"54"
    )
        port map (
      I0 => \FSM_onehot_reg_state_eios_det[5]_i_2__0_n_0\,
      I1 => \FSM_onehot_reg_state_eios_det_reg_n_0_[2]\,
      I2 => symbol_after_eios,
      O => \FSM_onehot_reg_state_eios_det[5]_i_1__0_n_0\
    );
\FSM_onehot_reg_state_eios_det[5]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFEFFFFFFFFF"
    )
        port map (
      I0 => \FSM_onehot_reg_state_eios_det[5]_i_3__0_n_0\,
      I1 => \^q\(7),
      I2 => \^q\(6),
      I3 => \^q\(1),
      I4 => \^q\(0),
      I5 => \gt_rxcharisk_q_reg_n_0_[0]\,
      O => \FSM_onehot_reg_state_eios_det[5]_i_2__0_n_0\
    );
\FSM_onehot_reg_state_eios_det[5]_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(5),
      I2 => \^q\(2),
      I3 => \^q\(4),
      O => \FSM_onehot_reg_state_eios_det[5]_i_3__0_n_0\
    );
\FSM_onehot_reg_state_eios_det_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => \gt_rx_status_q_reg[2]_1\,
      CE => '1',
      D => \FSM_onehot_reg_state_eios_det[1]_i_1__0_n_0\,
      Q => \FSM_onehot_reg_state_eios_det_reg_n_0_[1]\,
      S => SR(0)
    );
\FSM_onehot_reg_state_eios_det_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \gt_rx_status_q_reg[2]_1\,
      CE => '1',
      D => \FSM_onehot_reg_state_eios_det[2]_i_1__0_n_0\,
      Q => \FSM_onehot_reg_state_eios_det_reg_n_0_[2]\,
      R => SR(0)
    );
\FSM_onehot_reg_state_eios_det_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \gt_rx_status_q_reg[2]_1\,
      CE => '1',
      D => \FSM_onehot_reg_state_eios_det[3]_i_1__0_n_0\,
      Q => \FSM_onehot_reg_state_eios_det_reg_n_0_[3]\,
      R => SR(0)
    );
\FSM_onehot_reg_state_eios_det_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \gt_rx_status_q_reg[2]_1\,
      CE => '1',
      D => \FSM_onehot_reg_state_eios_det[5]_i_1__0_n_0\,
      Q => \FSM_onehot_reg_state_eios_det_reg_n_0_[5]\,
      R => SR(0)
    );
gt_rx_phy_status_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \gt_rx_status_q_reg[2]_1\,
      CE => '1',
      D => PIPE_PHYSTATUS(0),
      Q => pipe_rx1_phy_status,
      R => SR(0)
    );
\gt_rx_status_q_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \gt_rx_status_q_reg[2]_1\,
      CE => '1',
      D => \gt_rx_status_q_reg[2]_2\(0),
      Q => \gt_rx_status_q_reg[2]_0\(0),
      R => SR(0)
    );
\gt_rx_status_q_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \gt_rx_status_q_reg[2]_1\,
      CE => '1',
      D => \gt_rx_status_q_reg[2]_2\(1),
      Q => \gt_rx_status_q_reg[2]_0\(1),
      R => SR(0)
    );
\gt_rx_status_q_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \gt_rx_status_q_reg[2]_1\,
      CE => '1',
      D => \gt_rx_status_q_reg[2]_2\(2),
      Q => \gt_rx_status_q_reg[2]_0\(2),
      R => SR(0)
    );
\gt_rxcharisk_q_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \gt_rx_status_q_reg[2]_1\,
      CE => '1',
      D => \gt_rxcharisk_q_reg[1]_0\(0),
      Q => \gt_rxcharisk_q_reg_n_0_[0]\,
      R => SR(0)
    );
\gt_rxcharisk_q_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \gt_rx_status_q_reg[2]_1\,
      CE => '1',
      D => \gt_rxcharisk_q_reg[1]_0\(1),
      Q => p_0_in,
      R => SR(0)
    );
\gt_rxdata_q_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \gt_rx_status_q_reg[2]_1\,
      CE => '1',
      D => D(0),
      Q => \^q\(0),
      R => SR(0)
    );
\gt_rxdata_q_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \gt_rx_status_q_reg[2]_1\,
      CE => '1',
      D => D(10),
      Q => \^q\(10),
      R => SR(0)
    );
\gt_rxdata_q_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \gt_rx_status_q_reg[2]_1\,
      CE => '1',
      D => D(11),
      Q => \^q\(11),
      R => SR(0)
    );
\gt_rxdata_q_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \gt_rx_status_q_reg[2]_1\,
      CE => '1',
      D => D(12),
      Q => \^q\(12),
      R => SR(0)
    );
\gt_rxdata_q_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \gt_rx_status_q_reg[2]_1\,
      CE => '1',
      D => D(13),
      Q => \^q\(13),
      R => SR(0)
    );
\gt_rxdata_q_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \gt_rx_status_q_reg[2]_1\,
      CE => '1',
      D => D(14),
      Q => \^q\(14),
      R => SR(0)
    );
\gt_rxdata_q_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \gt_rx_status_q_reg[2]_1\,
      CE => '1',
      D => D(15),
      Q => \^q\(15),
      R => SR(0)
    );
\gt_rxdata_q_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \gt_rx_status_q_reg[2]_1\,
      CE => '1',
      D => D(1),
      Q => \^q\(1),
      R => SR(0)
    );
\gt_rxdata_q_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \gt_rx_status_q_reg[2]_1\,
      CE => '1',
      D => D(2),
      Q => \^q\(2),
      R => SR(0)
    );
\gt_rxdata_q_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \gt_rx_status_q_reg[2]_1\,
      CE => '1',
      D => D(3),
      Q => \^q\(3),
      R => SR(0)
    );
\gt_rxdata_q_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \gt_rx_status_q_reg[2]_1\,
      CE => '1',
      D => D(4),
      Q => \^q\(4),
      R => SR(0)
    );
\gt_rxdata_q_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \gt_rx_status_q_reg[2]_1\,
      CE => '1',
      D => D(5),
      Q => \^q\(5),
      R => SR(0)
    );
\gt_rxdata_q_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \gt_rx_status_q_reg[2]_1\,
      CE => '1',
      D => D(6),
      Q => \^q\(6),
      R => SR(0)
    );
\gt_rxdata_q_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \gt_rx_status_q_reg[2]_1\,
      CE => '1',
      D => D(7),
      Q => \^q\(7),
      R => SR(0)
    );
\gt_rxdata_q_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \gt_rx_status_q_reg[2]_1\,
      CE => '1',
      D => D(8),
      Q => \^q\(8),
      R => SR(0)
    );
\gt_rxdata_q_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \gt_rx_status_q_reg[2]_1\,
      CE => '1',
      D => D(9),
      Q => \^q\(9),
      R => SR(0)
    );
gt_rxelecidle_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \gt_rx_status_q_reg[2]_1\,
      CE => '1',
      D => SYNC_RXELECIDLE,
      Q => pipe_rx1_elec_idle,
      R => SR(0)
    );
\gt_rxvalid_q_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"45004545"
    )
        port map (
      I0 => gt_rxvalid_q_reg_1,
      I1 => gt_rxvalid_q_reg_2,
      I2 => \FSM_onehot_reg_state_eios_det_reg_n_0_[5]\,
      I3 => gt_rxvalid_q_i_3_n_0,
      I4 => \gt_rxvalid_q_i_4__0_n_0\,
      O => gt_rxvalid_q
    );
gt_rxvalid_q_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FEFEFEFCFEFEFEFF"
    )
        port map (
      I0 => \FSM_onehot_reg_state_eios_det[5]_i_2__0_n_0\,
      I1 => \FSM_onehot_reg_state_eios_det_reg_n_0_[5]\,
      I2 => \FSM_onehot_reg_state_eios_det_reg_n_0_[1]\,
      I3 => symbol_after_eios,
      I4 => \FSM_onehot_reg_state_eios_det_reg_n_0_[2]\,
      I5 => \FSM_onehot_reg_state_eios_det_reg_n_0_[3]\,
      O => gt_rxvalid_q_i_3_n_0
    );
\gt_rxvalid_q_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000400FFFFFFFF"
    )
        port map (
      I0 => \FSM_onehot_reg_state_eios_det[5]_i_2__0_n_0\,
      I1 => \FSM_onehot_reg_state_eios_det[3]_i_2__0_n_0\,
      I2 => \^q\(9),
      I3 => \^q\(14),
      I4 => \^q\(15),
      I5 => \FSM_onehot_reg_state_eios_det_reg_n_0_[3]\,
      O => \gt_rxvalid_q_i_4__0_n_0\
    );
gt_rxvalid_q_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \gt_rx_status_q_reg[2]_1\,
      CE => '1',
      D => gt_rxvalid_q,
      Q => \^gt_rxvalid_q_reg_0\,
      R => SR(0)
    );
pcie_block_i_i_34: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => p_0_in,
      I1 => \^gt_rxvalid_q_reg_0\,
      I2 => symbol_after_eios,
      O => pipe_rx1_char_is_k(1)
    );
pcie_block_i_i_35: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^gt_rxvalid_q_reg_0\,
      I1 => \gt_rxcharisk_q_reg_n_0_[0]\,
      O => pipe_rx1_char_is_k(0)
    );
\reg_symbol_after_eios_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000040000000000"
    )
        port map (
      I0 => \FSM_onehot_reg_state_eios_det[5]_i_2__0_n_0\,
      I1 => \FSM_onehot_reg_state_eios_det[3]_i_2__0_n_0\,
      I2 => \^q\(9),
      I3 => \^q\(14),
      I4 => \^q\(15),
      I5 => \FSM_onehot_reg_state_eios_det_reg_n_0_[3]\,
      O => \reg_symbol_after_eios_i_1__0_n_0\
    );
reg_symbol_after_eios_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \gt_rx_status_q_reg[2]_1\,
      CE => '1',
      D => \reg_symbol_after_eios_i_1__0_n_0\,
      Q => symbol_after_eios,
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_gtx_cpllpd_ovrd is
  port (
    cpllrst : out STD_LOGIC;
    CPLLPD0 : out STD_LOGIC;
    gt_cpllpdrefclk : in STD_LOGIC;
    rate_cpllpd_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_gtx_cpllpd_ovrd : entity is "spec7_pcie_7x_0_gtx_cpllpd_ovrd";
end spec7_pcie_7x_0_spec7_pcie_7x_0_gtx_cpllpd_ovrd;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_gtx_cpllpd_ovrd is
  signal cpllpd : STD_LOGIC;
  signal \cpllpd_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[94]_srl31_n_0\ : STD_LOGIC;
  signal \cpllreset_wait_reg[126]_srl31_n_0\ : STD_LOGIC;
  signal \cpllreset_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[95]_srl32_n_1\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  attribute srl_bus_name : string;
  attribute srl_bus_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg ";
  attribute srl_name : string;
  attribute srl_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[94]_srl31 ";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \cpllpd_wait_reg[95]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[126]_srl31 ";
  attribute equivalent_register_removal of \cpllreset_wait_reg[127]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[95]_srl32 ";
begin
\cpllpd_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => '0',
      Q => \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[31]_srl32_n_1\
    );
\cpllpd_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllpd_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[63]_srl32_n_1\
    );
\cpllpd_wait_reg[94]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11110",
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllpd_wait_reg[63]_srl32_n_1\,
      Q => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q31 => \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\
    );
\cpllpd_wait_reg[95]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => gt_cpllpdrefclk,
      CE => '1',
      D => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q => cpllpd,
      R => '0'
    );
\cpllreset_wait_reg[126]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11110",
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[95]_srl32_n_1\,
      Q => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q31 => \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\
    );
\cpllreset_wait_reg[127]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_cpllpdrefclk,
      CE => '1',
      D => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q => cpllrst,
      R => '0'
    );
\cpllreset_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"000000FF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => '0',
      Q => \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[31]_srl32_n_1\
    );
\cpllreset_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[63]_srl32_n_1\
    );
\cpllreset_wait_reg[95]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[63]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[95]_srl32_n_1\
    );
\gtx_channel.gtxe2_channel_i_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => cpllpd,
      I1 => rate_cpllpd_1,
      O => CPLLPD0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_gtx_cpllpd_ovrd_23 is
  port (
    cpllrst : out STD_LOGIC;
    CPLLPD0 : out STD_LOGIC;
    gt_cpllpdrefclk : in STD_LOGIC;
    rate_cpllpd_0 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_gtx_cpllpd_ovrd_23 : entity is "spec7_pcie_7x_0_gtx_cpllpd_ovrd";
end spec7_pcie_7x_0_spec7_pcie_7x_0_gtx_cpllpd_ovrd_23;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_gtx_cpllpd_ovrd_23 is
  signal cpllpd : STD_LOGIC;
  signal \cpllpd_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllpd_wait_reg[94]_srl31_n_0\ : STD_LOGIC;
  signal \cpllreset_wait_reg[126]_srl31_n_0\ : STD_LOGIC;
  signal \cpllreset_wait_reg[31]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[63]_srl32_n_1\ : STD_LOGIC;
  signal \cpllreset_wait_reg[95]_srl32_n_1\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\ : STD_LOGIC;
  attribute srl_bus_name : string;
  attribute srl_bus_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg ";
  attribute srl_name : string;
  attribute srl_name of \cpllpd_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg ";
  attribute srl_name of \cpllpd_wait_reg[94]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllpd_wait_reg[94]_srl31 ";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of \cpllpd_wait_reg[95]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[126]_srl31\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[126]_srl31 ";
  attribute equivalent_register_removal of \cpllreset_wait_reg[127]\ : label is "no";
  attribute srl_bus_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[31]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[31]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[63]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[63]_srl32 ";
  attribute srl_bus_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg ";
  attribute srl_name of \cpllreset_wait_reg[95]_srl32\ : label is "U0/\inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/cpllPDInst/cpllreset_wait_reg[95]_srl32 ";
begin
\cpllpd_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => '0',
      Q => \NLW_cpllpd_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[31]_srl32_n_1\
    );
\cpllpd_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"FFFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllpd_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllpd_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllpd_wait_reg[63]_srl32_n_1\
    );
\cpllpd_wait_reg[94]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      A(4 downto 0) => B"11110",
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllpd_wait_reg[63]_srl32_n_1\,
      Q => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q31 => \NLW_cpllpd_wait_reg[94]_srl31_Q31_UNCONNECTED\
    );
\cpllpd_wait_reg[95]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => gt_cpllpdrefclk,
      CE => '1',
      D => \cpllpd_wait_reg[94]_srl31_n_0\,
      Q => cpllpd,
      R => '0'
    );
\cpllreset_wait_reg[126]_srl31\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11110",
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[95]_srl32_n_1\,
      Q => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q31 => \NLW_cpllreset_wait_reg[126]_srl31_Q31_UNCONNECTED\
    );
\cpllreset_wait_reg[127]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => gt_cpllpdrefclk,
      CE => '1',
      D => \cpllreset_wait_reg[126]_srl31_n_0\,
      Q => cpllrst,
      R => '0'
    );
\cpllreset_wait_reg[31]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"000000FF"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => '0',
      Q => \NLW_cpllreset_wait_reg[31]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[31]_srl32_n_1\
    );
\cpllreset_wait_reg[63]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[31]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[63]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[63]_srl32_n_1\
    );
\cpllreset_wait_reg[95]_srl32\: unisim.vcomponents.SRLC32E
    generic map(
      INIT => X"00000000"
    )
        port map (
      A(4 downto 0) => B"11111",
      CE => '1',
      CLK => gt_cpllpdrefclk,
      D => \cpllreset_wait_reg[63]_srl32_n_1\,
      Q => \NLW_cpllreset_wait_reg[95]_srl32_Q_UNCONNECTED\,
      Q31 => \cpllreset_wait_reg[95]_srl32_n_1\
    );
\gtx_channel.gtxe2_channel_i_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => cpllpd,
      I1 => rate_cpllpd_0,
      O => CPLLPD0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_clock is
  port (
    pclk_sel_reg_0 : out STD_LOGIC;
    CLK : out STD_LOGIC;
    mmcm_i_0 : out STD_LOGIC;
    SYNC_MMCM_LOCK : out STD_LOGIC;
    mmcm_i_1 : out STD_LOGIC;
    pipe_txoutclk_out : in STD_LOGIC;
    SYNC_GEN3 : in STD_LOGIC;
    pipe_mmcm_rst_n : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 1 downto 0 );
    int_pclk_sel_slave : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_clock : entity is "spec7_pcie_7x_0_pipe_clock";
end spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_clock;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_clock is
  signal RST0 : STD_LOGIC;
  signal S00 : STD_LOGIC;
  signal \^sync_mmcm_lock\ : STD_LOGIC;
  signal clk_125mhz : STD_LOGIC;
  signal clk_250mhz : STD_LOGIC;
  signal gen3_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of gen3_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of gen3_reg1 : signal is "true";
  signal gen3_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of gen3_reg2 : signal is "NO";
  attribute async_reg of gen3_reg2 : signal is "true";
  signal mmcm_fb : STD_LOGIC;
  signal pclk_sel : STD_LOGIC;
  attribute DONT_TOUCH : boolean;
  attribute DONT_TOUCH of pclk_sel : signal is std.standard.true;
  signal pclk_sel_i_1_n_0 : STD_LOGIC;
  signal pclk_sel_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of pclk_sel_reg1 : signal is "NO";
  attribute async_reg of pclk_sel_reg1 : signal is "true";
  signal pclk_sel_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of pclk_sel_reg2 : signal is "NO";
  attribute async_reg of pclk_sel_reg2 : signal is "true";
  signal \^pclk_sel_reg_0\ : STD_LOGIC;
  signal pclk_sel_slave_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of pclk_sel_slave_reg1 : signal is "NO";
  attribute async_reg of pclk_sel_slave_reg1 : signal is "true";
  signal pclk_sel_slave_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of pclk_sel_slave_reg2 : signal is "NO";
  attribute async_reg of pclk_sel_slave_reg2 : signal is "true";
  signal refclk : STD_LOGIC;
  signal userclk1 : STD_LOGIC;
  signal NLW_mmcm_i_CLKFBOUTB_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_CLKFBSTOPPED_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_CLKINSTOPPED_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_CLKOUT0B_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_CLKOUT1B_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_CLKOUT2B_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_CLKOUT3_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_CLKOUT3B_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_CLKOUT4_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_CLKOUT5_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_CLKOUT6_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_DRDY_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_PSDONE_UNCONNECTED : STD_LOGIC;
  signal NLW_mmcm_i_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  attribute box_type : string;
  attribute box_type of \dclk_i_bufg.dclk_i\ : label is "PRIMITIVE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of gen3_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of gen3_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of gen3_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of gen3_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of gen3_reg2_reg : label is "NO";
  attribute box_type of mmcm_i : label is "PRIMITIVE";
  attribute DONT_TOUCH of \pclk_i1_bufgctrl.pclk_i1\ : label is std.standard.true;
  attribute box_type of \pclk_i1_bufgctrl.pclk_i1\ : label is "PRIMITIVE";
  attribute DONT_TOUCH of pclk_sel_reg : label is std.standard.true;
  attribute KEEP of pclk_sel_reg : label is "yes";
  attribute ASYNC_REG_boolean of \pclk_sel_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \pclk_sel_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \pclk_sel_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \pclk_sel_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \pclk_sel_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \pclk_sel_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \pclk_sel_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \pclk_sel_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \pclk_sel_slave_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_slave_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \pclk_sel_slave_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \pclk_sel_slave_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_slave_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \pclk_sel_slave_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \pclk_sel_slave_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_slave_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \pclk_sel_slave_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \pclk_sel_slave_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \pclk_sel_slave_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \pclk_sel_slave_reg2_reg[1]\ : label is "NO";
  attribute box_type of \txoutclk_i.txoutclk_i\ : label is "PRIMITIVE";
  attribute box_type of \userclk1_i1.usrclk1_i1\ : label is "PRIMITIVE";
begin
  SYNC_MMCM_LOCK <= \^sync_mmcm_lock\;
  pclk_sel_reg_0 <= \^pclk_sel_reg_0\;
\dclk_i_bufg.dclk_i\: unisim.vcomponents.BUFG
     port map (
      I => clk_125mhz,
      O => CLK
    );
gen3_reg1_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^pclk_sel_reg_0\,
      CE => '1',
      D => SYNC_GEN3,
      Q => gen3_reg1,
      R => RST0
    );
gen3_reg2_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^pclk_sel_reg_0\,
      CE => '1',
      D => gen3_reg1,
      Q => gen3_reg2,
      R => RST0
    );
mmcm_i: unisim.vcomponents.MMCME2_ADV
    generic map(
      BANDWIDTH => "OPTIMIZED",
      CLKFBOUT_MULT_F => 10.000000,
      CLKFBOUT_PHASE => 0.000000,
      CLKFBOUT_USE_FINE_PS => false,
      CLKIN1_PERIOD => 10.000000,
      CLKIN2_PERIOD => 0.000000,
      CLKOUT0_DIVIDE_F => 8.000000,
      CLKOUT0_DUTY_CYCLE => 0.500000,
      CLKOUT0_PHASE => 0.000000,
      CLKOUT0_USE_FINE_PS => false,
      CLKOUT1_DIVIDE => 4,
      CLKOUT1_DUTY_CYCLE => 0.500000,
      CLKOUT1_PHASE => 0.000000,
      CLKOUT1_USE_FINE_PS => false,
      CLKOUT2_DIVIDE => 16,
      CLKOUT2_DUTY_CYCLE => 0.500000,
      CLKOUT2_PHASE => 0.000000,
      CLKOUT2_USE_FINE_PS => false,
      CLKOUT3_DIVIDE => 16,
      CLKOUT3_DUTY_CYCLE => 0.500000,
      CLKOUT3_PHASE => 0.000000,
      CLKOUT3_USE_FINE_PS => false,
      CLKOUT4_CASCADE => false,
      CLKOUT4_DIVIDE => 20,
      CLKOUT4_DUTY_CYCLE => 0.500000,
      CLKOUT4_PHASE => 0.000000,
      CLKOUT4_USE_FINE_PS => false,
      CLKOUT5_DIVIDE => 1,
      CLKOUT5_DUTY_CYCLE => 0.500000,
      CLKOUT5_PHASE => 0.000000,
      CLKOUT5_USE_FINE_PS => false,
      CLKOUT6_DIVIDE => 1,
      CLKOUT6_DUTY_CYCLE => 0.500000,
      CLKOUT6_PHASE => 0.000000,
      CLKOUT6_USE_FINE_PS => false,
      COMPENSATION => "INTERNAL",
      DIVCLK_DIVIDE => 1,
      IS_CLKINSEL_INVERTED => '0',
      IS_PSEN_INVERTED => '0',
      IS_PSINCDEC_INVERTED => '0',
      IS_PWRDWN_INVERTED => '0',
      IS_RST_INVERTED => '0',
      REF_JITTER1 => 0.010000,
      REF_JITTER2 => 0.010000,
      SS_EN => "FALSE",
      SS_MODE => "CENTER_HIGH",
      SS_MOD_PERIOD => 10000,
      STARTUP_WAIT => false
    )
        port map (
      CLKFBIN => mmcm_fb,
      CLKFBOUT => mmcm_fb,
      CLKFBOUTB => NLW_mmcm_i_CLKFBOUTB_UNCONNECTED,
      CLKFBSTOPPED => NLW_mmcm_i_CLKFBSTOPPED_UNCONNECTED,
      CLKIN1 => refclk,
      CLKIN2 => '0',
      CLKINSEL => '1',
      CLKINSTOPPED => NLW_mmcm_i_CLKINSTOPPED_UNCONNECTED,
      CLKOUT0 => clk_125mhz,
      CLKOUT0B => NLW_mmcm_i_CLKOUT0B_UNCONNECTED,
      CLKOUT1 => clk_250mhz,
      CLKOUT1B => NLW_mmcm_i_CLKOUT1B_UNCONNECTED,
      CLKOUT2 => userclk1,
      CLKOUT2B => NLW_mmcm_i_CLKOUT2B_UNCONNECTED,
      CLKOUT3 => NLW_mmcm_i_CLKOUT3_UNCONNECTED,
      CLKOUT3B => NLW_mmcm_i_CLKOUT3B_UNCONNECTED,
      CLKOUT4 => NLW_mmcm_i_CLKOUT4_UNCONNECTED,
      CLKOUT5 => NLW_mmcm_i_CLKOUT5_UNCONNECTED,
      CLKOUT6 => NLW_mmcm_i_CLKOUT6_UNCONNECTED,
      DADDR(6 downto 0) => B"0000000",
      DCLK => '0',
      DEN => '0',
      DI(15 downto 0) => B"0000000000000000",
      DO(15 downto 0) => NLW_mmcm_i_DO_UNCONNECTED(15 downto 0),
      DRDY => NLW_mmcm_i_DRDY_UNCONNECTED,
      DWE => '0',
      LOCKED => \^sync_mmcm_lock\,
      PSCLK => '0',
      PSDONE => NLW_mmcm_i_PSDONE_UNCONNECTED,
      PSEN => '0',
      PSINCDEC => '0',
      PWRDWN => '0',
      RST => RST0
    );
mmcm_i_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => pipe_mmcm_rst_n,
      O => RST0
    );
\pclk_i1_bufgctrl.pclk_i1\: unisim.vcomponents.BUFGCTRL
    generic map(
      CE_TYPE_CE0 => "SYNC",
      CE_TYPE_CE1 => "SYNC",
      INIT_OUT => 0,
      IS_CE0_INVERTED => '0',
      IS_CE1_INVERTED => '0',
      IS_I0_INVERTED => '0',
      IS_I1_INVERTED => '0',
      IS_IGNORE0_INVERTED => '0',
      IS_IGNORE1_INVERTED => '0',
      IS_S0_INVERTED => '0',
      IS_S1_INVERTED => '0',
      PRESELECT_I0 => false,
      PRESELECT_I1 => false,
      SIM_DEVICE => "7SERIES",
      STARTUP_SYNC => "FALSE"
    )
        port map (
      CE0 => '1',
      CE1 => '1',
      I0 => clk_125mhz,
      I1 => clk_250mhz,
      IGNORE0 => '0',
      IGNORE1 => '0',
      O => \^pclk_sel_reg_0\,
      S0 => S00,
      S1 => pclk_sel
    );
\pclk_i1_bufgctrl.pclk_i1_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => pclk_sel,
      O => S00
    );
pclk_sel_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"E8"
    )
        port map (
      I0 => pclk_sel_reg2(0),
      I1 => pclk_sel_reg2(1),
      I2 => pclk_sel,
      O => pclk_sel_i_1_n_0
    );
pclk_sel_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^pclk_sel_reg_0\,
      CE => '1',
      D => pclk_sel_i_1_n_0,
      Q => pclk_sel,
      R => RST0
    );
\pclk_sel_reg1_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^pclk_sel_reg_0\,
      CE => '1',
      D => D(0),
      Q => pclk_sel_reg1(0),
      R => RST0
    );
\pclk_sel_reg1_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^pclk_sel_reg_0\,
      CE => '1',
      D => D(1),
      Q => pclk_sel_reg1(1),
      R => RST0
    );
\pclk_sel_reg2_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^pclk_sel_reg_0\,
      CE => '1',
      D => pclk_sel_reg1(0),
      Q => pclk_sel_reg2(0),
      R => RST0
    );
\pclk_sel_reg2_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^pclk_sel_reg_0\,
      CE => '1',
      D => pclk_sel_reg1(1),
      Q => pclk_sel_reg2(1),
      R => RST0
    );
\pclk_sel_slave_reg1_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^pclk_sel_reg_0\,
      CE => '1',
      D => int_pclk_sel_slave(0),
      Q => pclk_sel_slave_reg1(0),
      R => RST0
    );
\pclk_sel_slave_reg1_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^pclk_sel_reg_0\,
      CE => '1',
      D => int_pclk_sel_slave(1),
      Q => pclk_sel_slave_reg1(1),
      R => RST0
    );
\pclk_sel_slave_reg2_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^pclk_sel_reg_0\,
      CE => '1',
      D => pclk_sel_slave_reg1(0),
      Q => pclk_sel_slave_reg2(0),
      R => RST0
    );
\pclk_sel_slave_reg2_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^pclk_sel_reg_0\,
      CE => '1',
      D => pclk_sel_slave_reg1(1),
      Q => pclk_sel_slave_reg2(1),
      R => RST0
    );
reg_clock_locked_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^sync_mmcm_lock\,
      O => mmcm_i_1
    );
\txoutclk_i.txoutclk_i\: unisim.vcomponents.BUFG
     port map (
      I => pipe_txoutclk_out,
      O => refclk
    );
\userclk1_i1.usrclk1_i1\: unisim.vcomponents.BUFG
     port map (
      I => userclk1,
      O => mmcm_i_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_drp is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    DRPADDR : out STD_LOGIC_VECTOR ( 8 downto 0 );
    drp_mux_en_0 : out STD_LOGIC;
    drp_mux_we_0 : out STD_LOGIC;
    DRPDI : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt_ch_drp_rdy : out STD_LOGIC_VECTOR ( 0 to 0 );
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    rate_drp_x16x20_mode_0 : in STD_LOGIC;
    CLK : in STD_LOGIC;
    rate_drp_start_0 : in STD_LOGIC;
    ext_ch_gt_drprdy : in STD_LOGIC_VECTOR ( 0 to 0 );
    rst_gtreset : in STD_LOGIC;
    ext_ch_gt_drpaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
    pipe_tx_rate : in STD_LOGIC;
    ext_ch_gt_drpdo : in STD_LOGIC_VECTOR ( 15 downto 0 );
    ext_ch_gt_drpen : in STD_LOGIC_VECTOR ( 0 to 0 );
    ext_ch_gt_drpwe : in STD_LOGIC_VECTOR ( 0 to 0 );
    ext_ch_gt_drpdi : in STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_drp : entity is "spec7_pcie_7x_0_pipe_drp";
end spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_drp;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_drp is
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal addr_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \addr_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \addr_reg[6]_i_1_n_0\ : STD_LOGIC;
  signal data_pma_rsv_a : STD_LOGIC_VECTOR ( 15 to 15 );
  signal di_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \di_reg[0]_i_2_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_3_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_2_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_3_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_4_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_5_n_0\ : STD_LOGIC;
  signal \di_reg[12]_i_2_n_0\ : STD_LOGIC;
  signal \di_reg[12]_i_3_n_0\ : STD_LOGIC;
  signal \di_reg[13]_i_2_n_0\ : STD_LOGIC;
  signal \di_reg[13]_i_3_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_2_n_0\ : STD_LOGIC;
  signal \di_reg[15]_i_2_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_2_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_3_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_2_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_3_n_0\ : STD_LOGIC;
  signal \di_reg[3]_i_2_n_0\ : STD_LOGIC;
  signal \di_reg[3]_i_3_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_2_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_3_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_4_n_0\ : STD_LOGIC;
  signal \di_reg[5]_i_2_n_0\ : STD_LOGIC;
  signal \di_reg[5]_i_3_n_0\ : STD_LOGIC;
  signal \di_reg[6]_i_2_n_0\ : STD_LOGIC;
  signal \di_reg[6]_i_3_n_0\ : STD_LOGIC;
  signal \di_reg[7]_i_2_n_0\ : STD_LOGIC;
  signal \di_reg[7]_i_3_n_0\ : STD_LOGIC;
  signal do_reg1 : STD_LOGIC_VECTOR ( 15 downto 0 );
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of do_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of do_reg1 : signal is "true";
  signal do_reg2 : STD_LOGIC_VECTOR ( 15 downto 0 );
  attribute SHIFT_EXTRACT of do_reg2 : signal is "NO";
  attribute async_reg of do_reg2 : signal is "true";
  signal \done_i_1__1_n_0\ : STD_LOGIC;
  signal drp_addr_0 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal drp_di_0 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal fsm : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \fsm1__8\ : STD_LOGIC;
  signal \fsm[0]_i_3_n_0\ : STD_LOGIC;
  signal gtxreset_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of gtxreset_reg1 : signal is "NO";
  attribute async_reg of gtxreset_reg1 : signal is "true";
  signal gtxreset_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of gtxreset_reg2 : signal is "NO";
  attribute async_reg of gtxreset_reg2 : signal is "true";
  signal index : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \index[0]_i_1_n_0\ : STD_LOGIC;
  signal \index[1]_i_1_n_0\ : STD_LOGIC;
  signal \index[2]_i_1_n_0\ : STD_LOGIC;
  signal \index[3]_i_1_n_0\ : STD_LOGIC;
  signal \index[3]_i_2_n_0\ : STD_LOGIC;
  signal \index[4]_i_1_n_0\ : STD_LOGIC;
  signal \index[4]_i_2_n_0\ : STD_LOGIC;
  signal \index[4]_i_3_n_0\ : STD_LOGIC;
  signal load_cnt : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \load_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
  signal rate_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rate_reg1 : signal is "NO";
  attribute async_reg of rate_reg1 : signal is "true";
  signal rate_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rate_reg2 : signal is "NO";
  attribute async_reg of rate_reg2 : signal is "true";
  signal rdy_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rdy_reg1 : signal is "NO";
  attribute async_reg of rdy_reg1 : signal is "true";
  signal rdy_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rdy_reg2 : signal is "NO";
  attribute async_reg of rdy_reg2 : signal is "true";
  signal start_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of start_reg1 : signal is "NO";
  attribute async_reg of start_reg1 : signal is "true";
  signal start_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of start_reg2 : signal is "NO";
  attribute async_reg of start_reg2 : signal is "true";
  signal x16_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of x16_reg1 : signal is "NO";
  attribute async_reg of x16_reg1 : signal is "true";
  signal x16_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of x16_reg2 : signal is "NO";
  attribute async_reg of x16_reg2 : signal is "true";
  signal x16x20_mode_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of x16x20_mode_reg1 : signal is "NO";
  attribute async_reg of x16x20_mode_reg1 : signal is "true";
  signal x16x20_mode_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of x16x20_mode_reg2 : signal is "NO";
  attribute async_reg of x16x20_mode_reg2 : signal is "true";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \addr_reg[1]_i_1\ : label is "soft_lutpair13";
  attribute SOFT_HLUTNM of \addr_reg[2]_i_1\ : label is "soft_lutpair11";
  attribute SOFT_HLUTNM of \addr_reg[5]_i_1\ : label is "soft_lutpair13";
  attribute SOFT_HLUTNM of \addr_reg[6]_i_1\ : label is "soft_lutpair11";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \do_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \do_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[10]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[10]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[11]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[11]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[12]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[12]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[13]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[13]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[14]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[14]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[15]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[15]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[6]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[6]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[7]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[7]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[8]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[8]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[9]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[9]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[10]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[10]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[11]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[11]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[12]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[12]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[13]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[13]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[14]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[14]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[15]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[15]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[6]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[6]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[7]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[7]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[8]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[8]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[9]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[9]\ : label is "NO";
  attribute SOFT_HLUTNM of \gt_ch_drp_rdy[0]_INST_0\ : label is "soft_lutpair10";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_15\ : label is "soft_lutpair9";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_3\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_39__0\ : label is "soft_lutpair14";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_47\ : label is "soft_lutpair10";
  attribute ASYNC_REG_boolean of gtxreset_reg1_reg : label is std.standard.true;
  attribute KEEP of gtxreset_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of gtxreset_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of gtxreset_reg2_reg : label is std.standard.true;
  attribute KEEP of gtxreset_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of gtxreset_reg2_reg : label is "NO";
  attribute SOFT_HLUTNM of \index[0]_i_1\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \index[1]_i_1\ : label is "soft_lutpair12";
  attribute SOFT_HLUTNM of \index[3]_i_2\ : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of \index[4]_i_3\ : label is "soft_lutpair15";
  attribute SOFT_HLUTNM of \load_cnt[0]_i_1__0\ : label is "soft_lutpair9";
  attribute ASYNC_REG_boolean of \rate_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of rdy_reg1_reg : label is std.standard.true;
  attribute KEEP of rdy_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rdy_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rdy_reg2_reg : label is std.standard.true;
  attribute KEEP of rdy_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rdy_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of start_reg1_reg : label is std.standard.true;
  attribute KEEP of start_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of start_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of start_reg2_reg : label is std.standard.true;
  attribute KEEP of start_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of start_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of x16_reg1_reg : label is std.standard.true;
  attribute KEEP of x16_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of x16_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of x16_reg2_reg : label is std.standard.true;
  attribute KEEP of x16_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of x16_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of x16x20_mode_reg1_reg : label is std.standard.true;
  attribute KEEP of x16x20_mode_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of x16x20_mode_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of x16x20_mode_reg2_reg : label is std.standard.true;
  attribute KEEP of x16x20_mode_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of x16x20_mode_reg2_reg : label is "NO";
begin
  Q(2 downto 0) <= \^q\(2 downto 0);
\addr_reg[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1736415517364154"
    )
        port map (
      I0 => index(4),
      I1 => index(3),
      I2 => index(2),
      I3 => index(1),
      I4 => index(0),
      I5 => x16x20_mode_reg2,
      O => addr_reg(0)
    );
\addr_reg[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40500F00"
    )
        port map (
      I0 => index(4),
      I1 => index(0),
      I2 => index(3),
      I3 => index(1),
      I4 => index(2),
      O => addr_reg(1)
    );
\addr_reg[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"05105A00"
    )
        port map (
      I0 => index(4),
      I1 => index(0),
      I2 => index(3),
      I3 => index(2),
      I4 => index(1),
      O => addr_reg(2)
    );
\addr_reg[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5767576753265327"
    )
        port map (
      I0 => index(4),
      I1 => index(3),
      I2 => index(2),
      I3 => index(1),
      I4 => x16x20_mode_reg2,
      I5 => index(0),
      O => addr_reg(3)
    );
\addr_reg[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FAAFFF04"
    )
        port map (
      I0 => index(0),
      I1 => x16x20_mode_reg2,
      I2 => index(1),
      I3 => index(2),
      I4 => index(3),
      I5 => index(4),
      O => \addr_reg[4]_i_1_n_0\
    );
\addr_reg[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"001A0F0A"
    )
        port map (
      I0 => index(4),
      I1 => index(0),
      I2 => index(3),
      I3 => index(1),
      I4 => index(2),
      O => addr_reg(5)
    );
\addr_reg[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001454"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => index(3),
      I3 => index(0),
      I4 => index(4),
      O => \addr_reg[6]_i_1_n_0\
    );
\addr_reg[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5252424223236263"
    )
        port map (
      I0 => index(4),
      I1 => index(3),
      I2 => index(2),
      I3 => x16x20_mode_reg2,
      I4 => index(0),
      I5 => index(1),
      O => addr_reg(7)
    );
\addr_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => addr_reg(0),
      Q => drp_addr_0(0),
      R => SR(0)
    );
\addr_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => addr_reg(1),
      Q => drp_addr_0(1),
      R => SR(0)
    );
\addr_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => addr_reg(2),
      Q => drp_addr_0(2),
      R => SR(0)
    );
\addr_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => addr_reg(3),
      Q => drp_addr_0(3),
      R => SR(0)
    );
\addr_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \addr_reg[4]_i_1_n_0\,
      Q => drp_addr_0(4),
      R => SR(0)
    );
\addr_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => addr_reg(5),
      Q => drp_addr_0(5),
      R => SR(0)
    );
\addr_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \addr_reg[6]_i_1_n_0\,
      Q => drp_addr_0(6),
      R => SR(0)
    );
\addr_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => addr_reg(7),
      Q => drp_addr_0(7),
      R => SR(0)
    );
\di_reg[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF5E7F6FA1001000"
    )
        port map (
      I0 => index(3),
      I1 => index(2),
      I2 => index(1),
      I3 => data_pma_rsv_a(15),
      I4 => index(0),
      I5 => do_reg2(0),
      O => \di_reg[0]_i_2_n_0\
    );
\di_reg[0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000005D0"
    )
        port map (
      I0 => index(0),
      I1 => do_reg2(0),
      I2 => index(2),
      I3 => index(1),
      I4 => index(3),
      O => \di_reg[0]_i_3_n_0\
    );
\di_reg[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"45555F5540000000"
    )
        port map (
      I0 => index(4),
      I1 => \di_reg[15]_i_2_n_0\,
      I2 => index(1),
      I3 => index(2),
      I4 => index(3),
      I5 => do_reg2(10),
      O => di_reg(10)
    );
\di_reg[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F40DDDD4F408888"
    )
        port map (
      I0 => index(3),
      I1 => do_reg2(11),
      I2 => index(1),
      I3 => \di_reg[11]_i_4_n_0\,
      I4 => index(2),
      I5 => \di_reg[11]_i_5_n_0\,
      O => \di_reg[11]_i_2_n_0\
    );
\di_reg[11]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000008080838"
    )
        port map (
      I0 => do_reg2(11),
      I1 => index(2),
      I2 => index(1),
      I3 => data_pma_rsv_a(15),
      I4 => index(0),
      I5 => index(3),
      O => \di_reg[11]_i_3_n_0\
    );
\di_reg[11]_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B8BB"
    )
        port map (
      I0 => do_reg2(11),
      I1 => index(0),
      I2 => rate_reg2(0),
      I3 => rate_reg2(1),
      O => \di_reg[11]_i_4_n_0\
    );
\di_reg[11]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFFF0100"
    )
        port map (
      I0 => index(1),
      I1 => index(0),
      I2 => x16_reg2,
      I3 => x16x20_mode_reg2,
      I4 => do_reg2(11),
      O => \di_reg[11]_i_5_n_0\
    );
\di_reg[12]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"777EFFFF01080000"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      I2 => index(0),
      I3 => data_pma_rsv_a(15),
      I4 => index(2),
      I5 => do_reg2(12),
      O => \di_reg[12]_i_2_n_0\
    );
\di_reg[12]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000B08"
    )
        port map (
      I0 => do_reg2(12),
      I1 => index(2),
      I2 => index(1),
      I3 => index(0),
      I4 => index(3),
      O => \di_reg[12]_i_3_n_0\
    );
\di_reg[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"767FFFFF00090000"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      I2 => index(0),
      I3 => data_pma_rsv_a(15),
      I4 => index(2),
      I5 => do_reg2(13),
      O => \di_reg[13]_i_2_n_0\
    );
\di_reg[13]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000008380808"
    )
        port map (
      I0 => do_reg2(13),
      I1 => index(2),
      I2 => index(1),
      I3 => index(0),
      I4 => data_pma_rsv_a(15),
      I5 => index(3),
      O => \di_reg[13]_i_3_n_0\
    );
\di_reg[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040FFFF00400000"
    )
        port map (
      I0 => index(1),
      I1 => index(2),
      I2 => do_reg2(14),
      I3 => index(3),
      I4 => index(4),
      I5 => \di_reg[14]_i_2_n_0\,
      O => di_reg(14)
    );
\di_reg[14]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"653BFFF721080080"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      I2 => data_pma_rsv_a(15),
      I3 => index(0),
      I4 => index(2),
      I5 => do_reg2(14),
      O => \di_reg[14]_i_2_n_0\
    );
\di_reg[14]_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      O => data_pma_rsv_a(15)
    );
\di_reg[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"45555F5540000000"
    )
        port map (
      I0 => index(4),
      I1 => \di_reg[15]_i_2_n_0\,
      I2 => index(1),
      I3 => index(2),
      I4 => index(3),
      I5 => do_reg2(15),
      O => di_reg(15)
    );
\di_reg[15]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(0),
      O => \di_reg[15]_i_2_n_0\
    );
\di_reg[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5FEE4E0076FF1000"
    )
        port map (
      I0 => index(3),
      I1 => index(2),
      I2 => data_pma_rsv_a(15),
      I3 => index(1),
      I4 => do_reg2(1),
      I5 => index(0),
      O => \di_reg[1]_i_2_n_0\
    );
\di_reg[1]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000005D0"
    )
        port map (
      I0 => index(0),
      I1 => do_reg2(1),
      I2 => index(2),
      I3 => index(1),
      I4 => index(3),
      O => \di_reg[1]_i_3_n_0\
    );
\di_reg[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5DEE080067FF0100"
    )
        port map (
      I0 => index(3),
      I1 => index(2),
      I2 => data_pma_rsv_a(15),
      I3 => index(1),
      I4 => do_reg2(2),
      I5 => index(0),
      O => \di_reg[2]_i_2_n_0\
    );
\di_reg[2]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000380"
    )
        port map (
      I0 => do_reg2(2),
      I1 => index(0),
      I2 => index(2),
      I3 => index(1),
      I4 => index(3),
      O => \di_reg[2]_i_3_n_0\
    );
\di_reg[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"43FFFFFF40000000"
    )
        port map (
      I0 => data_pma_rsv_a(15),
      I1 => index(2),
      I2 => index(0),
      I3 => index(1),
      I4 => index(3),
      I5 => do_reg2(3),
      O => \di_reg[3]_i_2_n_0\
    );
\di_reg[3]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000033D100"
    )
        port map (
      I0 => data_pma_rsv_a(15),
      I1 => index(0),
      I2 => do_reg2(3),
      I3 => index(2),
      I4 => index(1),
      I5 => index(3),
      O => \di_reg[3]_i_3_n_0\
    );
\di_reg[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \di_reg[4]_i_2_n_0\,
      I1 => index(4),
      I2 => \di_reg[4]_i_3_n_0\,
      I3 => index(3),
      I4 => \di_reg[4]_i_4_n_0\,
      O => di_reg(4)
    );
\di_reg[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F0400F0000400F0"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(1),
      I3 => index(2),
      I4 => index(0),
      I5 => do_reg2(4),
      O => \di_reg[4]_i_2_n_0\
    );
\di_reg[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"400FFFFF40000000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(2),
      I3 => index(0),
      I4 => index(1),
      I5 => do_reg2(4),
      O => \di_reg[4]_i_3_n_0\
    );
\di_reg[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BF00BF01FF40FE40"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => index(0),
      I3 => do_reg2(4),
      I4 => x16x20_mode_reg2,
      I5 => data_pma_rsv_a(15),
      O => \di_reg[4]_i_4_n_0\
    );
\di_reg[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F7F7F7E00000000"
    )
        port map (
      I0 => index(3),
      I1 => index(2),
      I2 => index(1),
      I3 => index(0),
      I4 => x16x20_mode_reg2,
      I5 => do_reg2(5),
      O => \di_reg[5]_i_2_n_0\
    );
\di_reg[5]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000038F0380"
    )
        port map (
      I0 => do_reg2(5),
      I1 => index(0),
      I2 => index(2),
      I3 => index(1),
      I4 => data_pma_rsv_a(15),
      I5 => index(3),
      O => \di_reg[5]_i_3_n_0\
    );
\di_reg[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7D7F7D7E00000000"
    )
        port map (
      I0 => index(3),
      I1 => index(2),
      I2 => index(1),
      I3 => index(0),
      I4 => x16x20_mode_reg2,
      I5 => do_reg2(6),
      O => \di_reg[6]_i_2_n_0\
    );
\di_reg[6]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000380"
    )
        port map (
      I0 => do_reg2(6),
      I1 => index(0),
      I2 => index(2),
      I3 => index(1),
      I4 => index(3),
      O => \di_reg[6]_i_3_n_0\
    );
\di_reg[7]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF0900"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => index(0),
      I3 => index(3),
      I4 => do_reg2(7),
      O => \di_reg[7]_i_2_n_0\
    );
\di_reg[7]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000003800383"
    )
        port map (
      I0 => do_reg2(7),
      I1 => index(0),
      I2 => index(2),
      I3 => index(1),
      I4 => data_pma_rsv_a(15),
      I5 => index(3),
      O => \di_reg[7]_i_3_n_0\
    );
\di_reg[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"03333F7300000040"
    )
        port map (
      I0 => index(0),
      I1 => index(4),
      I2 => index(1),
      I3 => index(2),
      I4 => index(3),
      I5 => do_reg2(8),
      O => di_reg(8)
    );
\di_reg[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"03333F7300000040"
    )
        port map (
      I0 => index(0),
      I1 => index(4),
      I2 => index(1),
      I3 => index(2),
      I4 => index(3),
      I5 => do_reg2(9),
      O => di_reg(9)
    );
\di_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(0),
      Q => drp_di_0(0),
      R => SR(0)
    );
\di_reg_reg[0]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[0]_i_2_n_0\,
      I1 => \di_reg[0]_i_3_n_0\,
      O => di_reg(0),
      S => index(4)
    );
\di_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(10),
      Q => drp_di_0(10),
      R => SR(0)
    );
\di_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(11),
      Q => drp_di_0(11),
      R => SR(0)
    );
\di_reg_reg[11]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[11]_i_2_n_0\,
      I1 => \di_reg[11]_i_3_n_0\,
      O => di_reg(11),
      S => index(4)
    );
\di_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(12),
      Q => drp_di_0(12),
      R => SR(0)
    );
\di_reg_reg[12]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[12]_i_2_n_0\,
      I1 => \di_reg[12]_i_3_n_0\,
      O => di_reg(12),
      S => index(4)
    );
\di_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(13),
      Q => drp_di_0(13),
      R => SR(0)
    );
\di_reg_reg[13]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[13]_i_2_n_0\,
      I1 => \di_reg[13]_i_3_n_0\,
      O => di_reg(13),
      S => index(4)
    );
\di_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(14),
      Q => drp_di_0(14),
      R => SR(0)
    );
\di_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(15),
      Q => drp_di_0(15),
      R => SR(0)
    );
\di_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(1),
      Q => drp_di_0(1),
      R => SR(0)
    );
\di_reg_reg[1]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[1]_i_2_n_0\,
      I1 => \di_reg[1]_i_3_n_0\,
      O => di_reg(1),
      S => index(4)
    );
\di_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(2),
      Q => drp_di_0(2),
      R => SR(0)
    );
\di_reg_reg[2]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[2]_i_2_n_0\,
      I1 => \di_reg[2]_i_3_n_0\,
      O => di_reg(2),
      S => index(4)
    );
\di_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(3),
      Q => drp_di_0(3),
      R => SR(0)
    );
\di_reg_reg[3]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[3]_i_2_n_0\,
      I1 => \di_reg[3]_i_3_n_0\,
      O => di_reg(3),
      S => index(4)
    );
\di_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(4),
      Q => drp_di_0(4),
      R => SR(0)
    );
\di_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(5),
      Q => drp_di_0(5),
      R => SR(0)
    );
\di_reg_reg[5]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[5]_i_2_n_0\,
      I1 => \di_reg[5]_i_3_n_0\,
      O => di_reg(5),
      S => index(4)
    );
\di_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(6),
      Q => drp_di_0(6),
      R => SR(0)
    );
\di_reg_reg[6]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[6]_i_2_n_0\,
      I1 => \di_reg[6]_i_3_n_0\,
      O => di_reg(6),
      S => index(4)
    );
\di_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(7),
      Q => drp_di_0(7),
      R => SR(0)
    );
\di_reg_reg[7]_i_1\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[7]_i_2_n_0\,
      I1 => \di_reg[7]_i_3_n_0\,
      O => di_reg(7),
      S => index(4)
    );
\di_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(8),
      Q => drp_di_0(8),
      R => SR(0)
    );
\di_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(9),
      Q => drp_di_0(9),
      R => SR(0)
    );
\do_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(0),
      Q => do_reg1(0),
      R => SR(0)
    );
\do_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(10),
      Q => do_reg1(10),
      R => SR(0)
    );
\do_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(11),
      Q => do_reg1(11),
      R => SR(0)
    );
\do_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(12),
      Q => do_reg1(12),
      R => SR(0)
    );
\do_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(13),
      Q => do_reg1(13),
      R => SR(0)
    );
\do_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(14),
      Q => do_reg1(14),
      R => SR(0)
    );
\do_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(15),
      Q => do_reg1(15),
      R => SR(0)
    );
\do_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(1),
      Q => do_reg1(1),
      R => SR(0)
    );
\do_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(2),
      Q => do_reg1(2),
      R => SR(0)
    );
\do_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(3),
      Q => do_reg1(3),
      R => SR(0)
    );
\do_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(4),
      Q => do_reg1(4),
      R => SR(0)
    );
\do_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(5),
      Q => do_reg1(5),
      R => SR(0)
    );
\do_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(6),
      Q => do_reg1(6),
      R => SR(0)
    );
\do_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(7),
      Q => do_reg1(7),
      R => SR(0)
    );
\do_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(8),
      Q => do_reg1(8),
      R => SR(0)
    );
\do_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(9),
      Q => do_reg1(9),
      R => SR(0)
    );
\do_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(0),
      Q => do_reg2(0),
      R => SR(0)
    );
\do_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(10),
      Q => do_reg2(10),
      R => SR(0)
    );
\do_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(11),
      Q => do_reg2(11),
      R => SR(0)
    );
\do_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(12),
      Q => do_reg2(12),
      R => SR(0)
    );
\do_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(13),
      Q => do_reg2(13),
      R => SR(0)
    );
\do_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(14),
      Q => do_reg2(14),
      R => SR(0)
    );
\do_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(15),
      Q => do_reg2(15),
      R => SR(0)
    );
\do_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(1),
      Q => do_reg2(1),
      R => SR(0)
    );
\do_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(2),
      Q => do_reg2(2),
      R => SR(0)
    );
\do_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(3),
      Q => do_reg2(3),
      R => SR(0)
    );
\do_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(4),
      Q => do_reg2(4),
      R => SR(0)
    );
\do_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(5),
      Q => do_reg2(5),
      R => SR(0)
    );
\do_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(6),
      Q => do_reg2(6),
      R => SR(0)
    );
\do_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(7),
      Q => do_reg2(7),
      R => SR(0)
    );
\do_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(8),
      Q => do_reg2(8),
      R => SR(0)
    );
\do_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(9),
      Q => do_reg2(9),
      R => SR(0)
    );
\done_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => start_reg2,
      I3 => \^q\(1),
      O => \done_i_1__1_n_0\
    );
done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \done_i_1__1_n_0\,
      Q => D(0),
      R => SR(0)
    );
\fsm[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0377FFFF03770000"
    )
        port map (
      I0 => \fsm1__8\,
      I1 => \^q\(1),
      I2 => rdy_reg2,
      I3 => \^q\(0),
      I4 => \^q\(2),
      I5 => \fsm[0]_i_3_n_0\,
      O => fsm(0)
    );
\fsm[0]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000110000000"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      I2 => index(0),
      I3 => index(4),
      I4 => index(2),
      I5 => x16x20_mode_reg2,
      O => \fsm1__8\
    );
\fsm[0]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"47FF47CC"
    )
        port map (
      I0 => rdy_reg2,
      I1 => \^q\(1),
      I2 => load_cnt(0),
      I3 => \^q\(0),
      I4 => start_reg2,
      O => \fsm[0]_i_3_n_0\
    );
\fsm[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1D501850"
    )
        port map (
      I0 => \^q\(2),
      I1 => rdy_reg2,
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => load_cnt(0),
      O => fsm(1)
    );
\fsm[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6222"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => rdy_reg2,
      I3 => \^q\(0),
      O => fsm(2)
    );
\fsm_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => fsm(0),
      Q => \^q\(0),
      R => SR(0)
    );
\fsm_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => fsm(1),
      Q => \^q\(1),
      R => SR(0)
    );
\fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => fsm(2),
      Q => \^q\(2),
      R => SR(0)
    );
\gt_ch_drp_rdy[0]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      O => gt_ch_drp_rdy(0)
    );
\gtx_channel.gtxe2_channel_i_i_10\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(11),
      I1 => drp_di_0(11),
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(11)
    );
\gtx_channel.gtxe2_channel_i_i_11\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(10),
      I1 => drp_di_0(10),
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(10)
    );
\gtx_channel.gtxe2_channel_i_i_12\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(9),
      I1 => drp_di_0(9),
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(9)
    );
\gtx_channel.gtxe2_channel_i_i_13\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(8),
      I1 => drp_di_0(8),
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(8)
    );
\gtx_channel.gtxe2_channel_i_i_14\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(7),
      I1 => drp_di_0(7),
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(7)
    );
\gtx_channel.gtxe2_channel_i_i_15\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(6),
      I1 => drp_di_0(6),
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(6)
    );
\gtx_channel.gtxe2_channel_i_i_16\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(5),
      I1 => drp_di_0(5),
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(5)
    );
\gtx_channel.gtxe2_channel_i_i_17\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(4),
      I1 => drp_di_0(4),
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(4)
    );
\gtx_channel.gtxe2_channel_i_i_18\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(3),
      I1 => drp_di_0(3),
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(3)
    );
\gtx_channel.gtxe2_channel_i_i_19\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(2),
      I1 => drp_di_0(2),
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(2)
    );
\gtx_channel.gtxe2_channel_i_i_20\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(1),
      I1 => drp_di_0(1),
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(1)
    );
\gtx_channel.gtxe2_channel_i_i_21\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(0),
      I1 => drp_di_0(0),
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(0)
    );
\gtx_channel.gtxe2_channel_i_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"030E"
    )
        port map (
      I0 => ext_ch_gt_drpen(0),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(1),
      O => drp_mux_en_0
    );
\gtx_channel.gtxe2_channel_i_i_39__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0002"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(8),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      O => DRPADDR(8)
    );
\gtx_channel.gtxe2_channel_i_i_4\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"000E"
    )
        port map (
      I0 => ext_ch_gt_drpwe(0),
      I1 => \^q\(2),
      I2 => \^q\(0),
      I3 => \^q\(1),
      O => drp_mux_we_0
    );
\gtx_channel.gtxe2_channel_i_i_40\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(7),
      I1 => drp_addr_0(7),
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(7)
    );
\gtx_channel.gtxe2_channel_i_i_41\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(6),
      I1 => drp_addr_0(6),
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(6)
    );
\gtx_channel.gtxe2_channel_i_i_42\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(5),
      I1 => drp_addr_0(5),
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(5)
    );
\gtx_channel.gtxe2_channel_i_i_43\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(4),
      I1 => drp_addr_0(4),
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(4)
    );
\gtx_channel.gtxe2_channel_i_i_44\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(3),
      I1 => drp_addr_0(3),
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(3)
    );
\gtx_channel.gtxe2_channel_i_i_45\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(2),
      I1 => drp_addr_0(2),
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(2)
    );
\gtx_channel.gtxe2_channel_i_i_46\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(1),
      I1 => drp_addr_0(1),
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(1)
    );
\gtx_channel.gtxe2_channel_i_i_47\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(0),
      I1 => drp_addr_0(0),
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPADDR(0)
    );
\gtx_channel.gtxe2_channel_i_i_6__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(15),
      I1 => drp_di_0(15),
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(15)
    );
\gtx_channel.gtxe2_channel_i_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(14),
      I1 => drp_di_0(14),
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(14)
    );
\gtx_channel.gtxe2_channel_i_i_8\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(13),
      I1 => drp_di_0(13),
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(13)
    );
\gtx_channel.gtxe2_channel_i_i_9\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCCCCCCA"
    )
        port map (
      I0 => ext_ch_gt_drpdi(12),
      I1 => drp_di_0(12),
      I2 => \^q\(2),
      I3 => \^q\(0),
      I4 => \^q\(1),
      O => DRPDI(12)
    );
gtxreset_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rst_gtreset,
      Q => gtxreset_reg1,
      R => SR(0)
    );
gtxreset_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => gtxreset_reg1,
      Q => gtxreset_reg2,
      R => SR(0)
    );
\index[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => \^q\(0),
      I1 => \fsm1__8\,
      I2 => index(0),
      I3 => \^q\(2),
      O => \index[0]_i_1_n_0\
    );
\index[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00140000"
    )
        port map (
      I0 => \^q\(0),
      I1 => index(1),
      I2 => index(0),
      I3 => \fsm1__8\,
      I4 => \^q\(2),
      O => \index[1]_i_1_n_0\
    );
\index[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000144400000000"
    )
        port map (
      I0 => \^q\(0),
      I1 => index(2),
      I2 => index(1),
      I3 => index(0),
      I4 => \fsm1__8\,
      I5 => \^q\(2),
      O => \index[2]_i_1_n_0\
    );
\index[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000144400000000"
    )
        port map (
      I0 => \^q\(0),
      I1 => index(3),
      I2 => index(2),
      I3 => \index[3]_i_2_n_0\,
      I4 => \fsm1__8\,
      I5 => \^q\(2),
      O => \index[3]_i_1_n_0\
    );
\index[3]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => index(1),
      I1 => index(0),
      O => \index[3]_i_2_n_0\
    );
\index[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A1"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      O => \index[4]_i_1_n_0\
    );
\index[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000144400000000"
    )
        port map (
      I0 => \^q\(0),
      I1 => index(4),
      I2 => index(3),
      I3 => \index[4]_i_3_n_0\,
      I4 => \fsm1__8\,
      I5 => \^q\(2),
      O => \index[4]_i_2_n_0\
    );
\index[4]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => index(2),
      I1 => index(0),
      I2 => index(1),
      O => \index[4]_i_3_n_0\
    );
\index_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \index[4]_i_1_n_0\,
      D => \index[0]_i_1_n_0\,
      Q => index(0),
      R => SR(0)
    );
\index_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \index[4]_i_1_n_0\,
      D => \index[1]_i_1_n_0\,
      Q => index(1),
      R => SR(0)
    );
\index_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \index[4]_i_1_n_0\,
      D => \index[2]_i_1_n_0\,
      Q => index(2),
      R => SR(0)
    );
\index_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \index[4]_i_1_n_0\,
      D => \index[3]_i_1_n_0\,
      Q => index(3),
      R => SR(0)
    );
\index_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \index[4]_i_1_n_0\,
      D => \index[4]_i_2_n_0\,
      Q => index(4),
      R => SR(0)
    );
\load_cnt[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      O => \load_cnt[0]_i_1__0_n_0\
    );
\load_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \load_cnt[0]_i_1__0_n_0\,
      Q => load_cnt(0),
      R => SR(0)
    );
\rate_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx_rate,
      Q => rate_reg1(0),
      R => SR(0)
    );
\rate_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rate_reg1(1),
      R => SR(0)
    );
\rate_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rate_reg1(0),
      Q => rate_reg2(0),
      R => SR(0)
    );
\rate_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rate_reg1(1),
      Q => rate_reg2(1),
      R => SR(0)
    );
rdy_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drprdy(0),
      Q => rdy_reg1,
      R => SR(0)
    );
rdy_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rdy_reg1,
      Q => rdy_reg2,
      R => SR(0)
    );
start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rate_drp_start_0,
      Q => start_reg1,
      R => SR(0)
    );
start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => start_reg1,
      Q => start_reg2,
      R => SR(0)
    );
x16_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rate_drp_x16x20_mode_0,
      Q => x16_reg1,
      R => SR(0)
    );
x16_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => x16_reg1,
      Q => x16_reg2,
      R => SR(0)
    );
x16x20_mode_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rate_drp_x16x20_mode_0,
      Q => x16x20_mode_reg1,
      R => SR(0)
    );
x16x20_mode_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => x16x20_mode_reg1,
      Q => x16x20_mode_reg2,
      R => SR(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_drp_17 is
  port (
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    drp_mux_en_1 : out STD_LOGIC;
    drp_mux_we_1 : out STD_LOGIC;
    DRPADDR : out STD_LOGIC_VECTOR ( 8 downto 0 );
    DRPDI : out STD_LOGIC_VECTOR ( 15 downto 0 );
    gt_ch_drp_rdy : out STD_LOGIC_VECTOR ( 0 to 0 );
    \out\ : in STD_LOGIC;
    rate_drp_x16x20_mode_1 : in STD_LOGIC;
    CLK : in STD_LOGIC;
    rate_drp_start_1 : in STD_LOGIC;
    ext_ch_gt_drprdy : in STD_LOGIC_VECTOR ( 0 to 0 );
    rst_gtreset : in STD_LOGIC;
    pipe_tx_rate : in STD_LOGIC;
    ext_ch_gt_drpdo : in STD_LOGIC_VECTOR ( 15 downto 0 );
    ext_ch_gt_drpen : in STD_LOGIC_VECTOR ( 0 to 0 );
    ext_ch_gt_drpwe : in STD_LOGIC_VECTOR ( 0 to 0 );
    ext_ch_gt_drpaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
    ext_ch_gt_drpdi : in STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_drp_17 : entity is "spec7_pcie_7x_0_pipe_drp";
end spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_drp_17;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_drp_17 is
  signal \^q\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal addr_reg : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \addr_reg[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \addr_reg[6]_i_1__0_n_0\ : STD_LOGIC;
  signal data_pma_rsv_a : STD_LOGIC_VECTOR ( 15 to 15 );
  signal di_reg : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \di_reg[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \di_reg[0]_i_3__0_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_2__0_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_3__0_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_4__0_n_0\ : STD_LOGIC;
  signal \di_reg[11]_i_5__0_n_0\ : STD_LOGIC;
  signal \di_reg[12]_i_2__0_n_0\ : STD_LOGIC;
  signal \di_reg[12]_i_3__0_n_0\ : STD_LOGIC;
  signal \di_reg[13]_i_2__0_n_0\ : STD_LOGIC;
  signal \di_reg[13]_i_3__0_n_0\ : STD_LOGIC;
  signal \di_reg[14]_i_2__0_n_0\ : STD_LOGIC;
  signal \di_reg[15]_i_2__0_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \di_reg[1]_i_3__0_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \di_reg[2]_i_3__0_n_0\ : STD_LOGIC;
  signal \di_reg[3]_i_2__0_n_0\ : STD_LOGIC;
  signal \di_reg[3]_i_3__0_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_2__0_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_3__0_n_0\ : STD_LOGIC;
  signal \di_reg[4]_i_4__0_n_0\ : STD_LOGIC;
  signal \di_reg[5]_i_2__0_n_0\ : STD_LOGIC;
  signal \di_reg[5]_i_3__0_n_0\ : STD_LOGIC;
  signal \di_reg[6]_i_2__0_n_0\ : STD_LOGIC;
  signal \di_reg[6]_i_3__0_n_0\ : STD_LOGIC;
  signal \di_reg[7]_i_2__0_n_0\ : STD_LOGIC;
  signal \di_reg[7]_i_3__0_n_0\ : STD_LOGIC;
  signal do_reg1 : STD_LOGIC_VECTOR ( 15 downto 0 );
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of do_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of do_reg1 : signal is "true";
  signal do_reg2 : STD_LOGIC_VECTOR ( 15 downto 0 );
  attribute SHIFT_EXTRACT of do_reg2 : signal is "NO";
  attribute async_reg of do_reg2 : signal is "true";
  signal \done_i_1__0_n_0\ : STD_LOGIC;
  signal drp_addr_9 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal drp_di_16 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal fsm : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \fsm1__8\ : STD_LOGIC;
  signal \fsm[0]_i_3__0_n_0\ : STD_LOGIC;
  signal gtxreset_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of gtxreset_reg1 : signal is "NO";
  attribute async_reg of gtxreset_reg1 : signal is "true";
  signal gtxreset_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of gtxreset_reg2 : signal is "NO";
  attribute async_reg of gtxreset_reg2 : signal is "true";
  signal index : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \index[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \index[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \index[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \index[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \index[3]_i_2__0_n_0\ : STD_LOGIC;
  signal \index[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \index[4]_i_2__0_n_0\ : STD_LOGIC;
  signal \index[4]_i_3__0_n_0\ : STD_LOGIC;
  signal load_cnt : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \load_cnt[0]_i_1__1_n_0\ : STD_LOGIC;
  signal rate_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rate_reg1 : signal is "NO";
  attribute async_reg of rate_reg1 : signal is "true";
  signal rate_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rate_reg2 : signal is "NO";
  attribute async_reg of rate_reg2 : signal is "true";
  signal rdy_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rdy_reg1 : signal is "NO";
  attribute async_reg of rdy_reg1 : signal is "true";
  signal rdy_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rdy_reg2 : signal is "NO";
  attribute async_reg of rdy_reg2 : signal is "true";
  signal start_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of start_reg1 : signal is "NO";
  attribute async_reg of start_reg1 : signal is "true";
  signal start_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of start_reg2 : signal is "NO";
  attribute async_reg of start_reg2 : signal is "true";
  signal x16_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of x16_reg1 : signal is "NO";
  attribute async_reg of x16_reg1 : signal is "true";
  signal x16_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of x16_reg2 : signal is "NO";
  attribute async_reg of x16_reg2 : signal is "true";
  signal x16x20_mode_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of x16x20_mode_reg1 : signal is "NO";
  attribute async_reg of x16x20_mode_reg1 : signal is "true";
  signal x16x20_mode_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of x16x20_mode_reg2 : signal is "NO";
  attribute async_reg of x16x20_mode_reg2 : signal is "true";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \addr_reg[1]_i_1__0\ : label is "soft_lutpair53";
  attribute SOFT_HLUTNM of \addr_reg[2]_i_1__0\ : label is "soft_lutpair51";
  attribute SOFT_HLUTNM of \addr_reg[5]_i_1__0\ : label is "soft_lutpair53";
  attribute SOFT_HLUTNM of \addr_reg[6]_i_1__0\ : label is "soft_lutpair51";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \do_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \do_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[10]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[10]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[11]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[11]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[12]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[12]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[13]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[13]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[14]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[14]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[15]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[15]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[6]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[6]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[7]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[7]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[8]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[8]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[9]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[9]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[10]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[10]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[11]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[11]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[12]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[12]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[13]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[13]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[14]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[14]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[15]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[15]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[6]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[6]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[7]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[7]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[8]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[8]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[9]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[9]\ : label is "NO";
  attribute SOFT_HLUTNM of \gt_ch_drp_rdy[1]_INST_0\ : label is "soft_lutpair50";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_3__0\ : label is "soft_lutpair54";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_45__0\ : label is "soft_lutpair49";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_48\ : label is "soft_lutpair50";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_4__0\ : label is "soft_lutpair54";
  attribute ASYNC_REG_boolean of gtxreset_reg1_reg : label is std.standard.true;
  attribute KEEP of gtxreset_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of gtxreset_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of gtxreset_reg2_reg : label is std.standard.true;
  attribute KEEP of gtxreset_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of gtxreset_reg2_reg : label is "NO";
  attribute SOFT_HLUTNM of \index[0]_i_1__0\ : label is "soft_lutpair52";
  attribute SOFT_HLUTNM of \index[1]_i_1__0\ : label is "soft_lutpair52";
  attribute SOFT_HLUTNM of \index[3]_i_2__0\ : label is "soft_lutpair55";
  attribute SOFT_HLUTNM of \index[4]_i_3__0\ : label is "soft_lutpair55";
  attribute SOFT_HLUTNM of \load_cnt[0]_i_1__1\ : label is "soft_lutpair49";
  attribute ASYNC_REG_boolean of \rate_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of rdy_reg1_reg : label is std.standard.true;
  attribute KEEP of rdy_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rdy_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rdy_reg2_reg : label is std.standard.true;
  attribute KEEP of rdy_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rdy_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of start_reg1_reg : label is std.standard.true;
  attribute KEEP of start_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of start_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of start_reg2_reg : label is std.standard.true;
  attribute KEEP of start_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of start_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of x16_reg1_reg : label is std.standard.true;
  attribute KEEP of x16_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of x16_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of x16_reg2_reg : label is std.standard.true;
  attribute KEEP of x16_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of x16_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of x16x20_mode_reg1_reg : label is std.standard.true;
  attribute KEEP of x16x20_mode_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of x16x20_mode_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of x16x20_mode_reg2_reg : label is std.standard.true;
  attribute KEEP of x16x20_mode_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of x16x20_mode_reg2_reg : label is "NO";
begin
  Q(2 downto 0) <= \^q\(2 downto 0);
\addr_reg[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1736415517364154"
    )
        port map (
      I0 => index(4),
      I1 => index(3),
      I2 => index(2),
      I3 => index(1),
      I4 => index(0),
      I5 => x16x20_mode_reg2,
      O => addr_reg(0)
    );
\addr_reg[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40500F00"
    )
        port map (
      I0 => index(4),
      I1 => index(0),
      I2 => index(3),
      I3 => index(1),
      I4 => index(2),
      O => addr_reg(1)
    );
\addr_reg[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"05105A00"
    )
        port map (
      I0 => index(4),
      I1 => index(0),
      I2 => index(3),
      I3 => index(2),
      I4 => index(1),
      O => addr_reg(2)
    );
\addr_reg[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5767576753265327"
    )
        port map (
      I0 => index(4),
      I1 => index(3),
      I2 => index(2),
      I3 => index(1),
      I4 => x16x20_mode_reg2,
      I5 => index(0),
      O => addr_reg(3)
    );
\addr_reg[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000FAAFFF04"
    )
        port map (
      I0 => index(0),
      I1 => x16x20_mode_reg2,
      I2 => index(1),
      I3 => index(2),
      I4 => index(3),
      I5 => index(4),
      O => \addr_reg[4]_i_1__0_n_0\
    );
\addr_reg[5]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"001A0F0A"
    )
        port map (
      I0 => index(4),
      I1 => index(0),
      I2 => index(3),
      I3 => index(1),
      I4 => index(2),
      O => addr_reg(5)
    );
\addr_reg[6]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001454"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => index(3),
      I3 => index(0),
      I4 => index(4),
      O => \addr_reg[6]_i_1__0_n_0\
    );
\addr_reg[7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5252424223236263"
    )
        port map (
      I0 => index(4),
      I1 => index(3),
      I2 => index(2),
      I3 => x16x20_mode_reg2,
      I4 => index(0),
      I5 => index(1),
      O => addr_reg(7)
    );
\addr_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => addr_reg(0),
      Q => drp_addr_9(0),
      R => \out\
    );
\addr_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => addr_reg(1),
      Q => drp_addr_9(1),
      R => \out\
    );
\addr_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => addr_reg(2),
      Q => drp_addr_9(2),
      R => \out\
    );
\addr_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => addr_reg(3),
      Q => drp_addr_9(3),
      R => \out\
    );
\addr_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \addr_reg[4]_i_1__0_n_0\,
      Q => drp_addr_9(4),
      R => \out\
    );
\addr_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => addr_reg(5),
      Q => drp_addr_9(5),
      R => \out\
    );
\addr_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \addr_reg[6]_i_1__0_n_0\,
      Q => drp_addr_9(6),
      R => \out\
    );
\addr_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => addr_reg(7),
      Q => drp_addr_9(7),
      R => \out\
    );
\di_reg[0]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF5E7F6FA1001000"
    )
        port map (
      I0 => index(3),
      I1 => index(2),
      I2 => index(1),
      I3 => data_pma_rsv_a(15),
      I4 => index(0),
      I5 => do_reg2(0),
      O => \di_reg[0]_i_2__0_n_0\
    );
\di_reg[0]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000005D0"
    )
        port map (
      I0 => index(0),
      I1 => do_reg2(0),
      I2 => index(2),
      I3 => index(1),
      I4 => index(3),
      O => \di_reg[0]_i_3__0_n_0\
    );
\di_reg[10]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"45555F5540000000"
    )
        port map (
      I0 => index(4),
      I1 => \di_reg[15]_i_2__0_n_0\,
      I2 => index(1),
      I3 => index(2),
      I4 => index(3),
      I5 => do_reg2(10),
      O => di_reg(10)
    );
\di_reg[11]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4F40DDDD4F408888"
    )
        port map (
      I0 => index(3),
      I1 => do_reg2(11),
      I2 => index(1),
      I3 => \di_reg[11]_i_4__0_n_0\,
      I4 => index(2),
      I5 => \di_reg[11]_i_5__0_n_0\,
      O => \di_reg[11]_i_2__0_n_0\
    );
\di_reg[11]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000008080838"
    )
        port map (
      I0 => do_reg2(11),
      I1 => index(2),
      I2 => index(1),
      I3 => data_pma_rsv_a(15),
      I4 => index(0),
      I5 => index(3),
      O => \di_reg[11]_i_3__0_n_0\
    );
\di_reg[11]_i_4__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B8BB"
    )
        port map (
      I0 => do_reg2(11),
      I1 => index(0),
      I2 => rate_reg2(0),
      I3 => rate_reg2(1),
      O => \di_reg[11]_i_4__0_n_0\
    );
\di_reg[11]_i_5__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EFFF0100"
    )
        port map (
      I0 => index(1),
      I1 => index(0),
      I2 => x16_reg2,
      I3 => x16x20_mode_reg2,
      I4 => do_reg2(11),
      O => \di_reg[11]_i_5__0_n_0\
    );
\di_reg[12]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"777EFFFF01080000"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      I2 => index(0),
      I3 => data_pma_rsv_a(15),
      I4 => index(2),
      I5 => do_reg2(12),
      O => \di_reg[12]_i_2__0_n_0\
    );
\di_reg[12]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000B08"
    )
        port map (
      I0 => do_reg2(12),
      I1 => index(2),
      I2 => index(1),
      I3 => index(0),
      I4 => index(3),
      O => \di_reg[12]_i_3__0_n_0\
    );
\di_reg[13]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"767FFFFF00090000"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      I2 => index(0),
      I3 => data_pma_rsv_a(15),
      I4 => index(2),
      I5 => do_reg2(13),
      O => \di_reg[13]_i_2__0_n_0\
    );
\di_reg[13]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000008380808"
    )
        port map (
      I0 => do_reg2(13),
      I1 => index(2),
      I2 => index(1),
      I3 => index(0),
      I4 => data_pma_rsv_a(15),
      I5 => index(3),
      O => \di_reg[13]_i_3__0_n_0\
    );
\di_reg[14]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0040FFFF00400000"
    )
        port map (
      I0 => index(1),
      I1 => index(2),
      I2 => do_reg2(14),
      I3 => index(3),
      I4 => index(4),
      I5 => \di_reg[14]_i_2__0_n_0\,
      O => di_reg(14)
    );
\di_reg[14]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"653BFFF721080080"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      I2 => data_pma_rsv_a(15),
      I3 => index(0),
      I4 => index(2),
      I5 => do_reg2(14),
      O => \di_reg[14]_i_2__0_n_0\
    );
\di_reg[14]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      O => data_pma_rsv_a(15)
    );
\di_reg[15]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"45555F5540000000"
    )
        port map (
      I0 => index(4),
      I1 => \di_reg[15]_i_2__0_n_0\,
      I2 => index(1),
      I3 => index(2),
      I4 => index(3),
      I5 => do_reg2(15),
      O => di_reg(15)
    );
\di_reg[15]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => rate_reg2(1),
      I1 => rate_reg2(0),
      I2 => index(0),
      O => \di_reg[15]_i_2__0_n_0\
    );
\di_reg[1]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5FEE4E0076FF1000"
    )
        port map (
      I0 => index(3),
      I1 => index(2),
      I2 => data_pma_rsv_a(15),
      I3 => index(1),
      I4 => do_reg2(1),
      I5 => index(0),
      O => \di_reg[1]_i_2__0_n_0\
    );
\di_reg[1]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"000005D0"
    )
        port map (
      I0 => index(0),
      I1 => do_reg2(1),
      I2 => index(2),
      I3 => index(1),
      I4 => index(3),
      O => \di_reg[1]_i_3__0_n_0\
    );
\di_reg[2]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5DEE080067FF0100"
    )
        port map (
      I0 => index(3),
      I1 => index(2),
      I2 => data_pma_rsv_a(15),
      I3 => index(1),
      I4 => do_reg2(2),
      I5 => index(0),
      O => \di_reg[2]_i_2__0_n_0\
    );
\di_reg[2]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000380"
    )
        port map (
      I0 => do_reg2(2),
      I1 => index(0),
      I2 => index(2),
      I3 => index(1),
      I4 => index(3),
      O => \di_reg[2]_i_3__0_n_0\
    );
\di_reg[3]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"43FFFFFF40000000"
    )
        port map (
      I0 => data_pma_rsv_a(15),
      I1 => index(2),
      I2 => index(0),
      I3 => index(1),
      I4 => index(3),
      I5 => do_reg2(3),
      O => \di_reg[3]_i_2__0_n_0\
    );
\di_reg[3]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000000033D100"
    )
        port map (
      I0 => data_pma_rsv_a(15),
      I1 => index(0),
      I2 => do_reg2(3),
      I3 => index(2),
      I4 => index(1),
      I5 => index(3),
      O => \di_reg[3]_i_3__0_n_0\
    );
\di_reg[4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"30BB3088"
    )
        port map (
      I0 => \di_reg[4]_i_2__0_n_0\,
      I1 => index(4),
      I2 => \di_reg[4]_i_3__0_n_0\,
      I3 => index(3),
      I4 => \di_reg[4]_i_4__0_n_0\,
      O => di_reg(4)
    );
\di_reg[4]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0F0400F0000400F0"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(1),
      I3 => index(2),
      I4 => index(0),
      I5 => do_reg2(4),
      O => \di_reg[4]_i_2__0_n_0\
    );
\di_reg[4]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"400FFFFF40000000"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => index(2),
      I3 => index(0),
      I4 => index(1),
      I5 => do_reg2(4),
      O => \di_reg[4]_i_3__0_n_0\
    );
\di_reg[4]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BF00BF01FF40FE40"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => index(0),
      I3 => do_reg2(4),
      I4 => x16x20_mode_reg2,
      I5 => data_pma_rsv_a(15),
      O => \di_reg[4]_i_4__0_n_0\
    );
\di_reg[5]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7F7F7F7E00000000"
    )
        port map (
      I0 => index(3),
      I1 => index(2),
      I2 => index(1),
      I3 => index(0),
      I4 => x16x20_mode_reg2,
      I5 => do_reg2(5),
      O => \di_reg[5]_i_2__0_n_0\
    );
\di_reg[5]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000000038F0380"
    )
        port map (
      I0 => do_reg2(5),
      I1 => index(0),
      I2 => index(2),
      I3 => index(1),
      I4 => data_pma_rsv_a(15),
      I5 => index(3),
      O => \di_reg[5]_i_3__0_n_0\
    );
\di_reg[6]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7D7F7D7E00000000"
    )
        port map (
      I0 => index(3),
      I1 => index(2),
      I2 => index(1),
      I3 => index(0),
      I4 => x16x20_mode_reg2,
      I5 => do_reg2(6),
      O => \di_reg[6]_i_2__0_n_0\
    );
\di_reg[6]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000380"
    )
        port map (
      I0 => do_reg2(6),
      I1 => index(0),
      I2 => index(2),
      I3 => index(1),
      I4 => index(3),
      O => \di_reg[6]_i_3__0_n_0\
    );
\di_reg[7]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFF0900"
    )
        port map (
      I0 => index(2),
      I1 => index(1),
      I2 => index(0),
      I3 => index(3),
      I4 => do_reg2(7),
      O => \di_reg[7]_i_2__0_n_0\
    );
\di_reg[7]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000003800383"
    )
        port map (
      I0 => do_reg2(7),
      I1 => index(0),
      I2 => index(2),
      I3 => index(1),
      I4 => data_pma_rsv_a(15),
      I5 => index(3),
      O => \di_reg[7]_i_3__0_n_0\
    );
\di_reg[8]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"03333F7300000040"
    )
        port map (
      I0 => index(0),
      I1 => index(4),
      I2 => index(1),
      I3 => index(2),
      I4 => index(3),
      I5 => do_reg2(8),
      O => di_reg(8)
    );
\di_reg[9]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"03333F7300000040"
    )
        port map (
      I0 => index(0),
      I1 => index(4),
      I2 => index(1),
      I3 => index(2),
      I4 => index(3),
      I5 => do_reg2(9),
      O => di_reg(9)
    );
\di_reg_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(0),
      Q => drp_di_16(0),
      R => \out\
    );
\di_reg_reg[0]_i_1__0\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[0]_i_2__0_n_0\,
      I1 => \di_reg[0]_i_3__0_n_0\,
      O => di_reg(0),
      S => index(4)
    );
\di_reg_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(10),
      Q => drp_di_16(10),
      R => \out\
    );
\di_reg_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(11),
      Q => drp_di_16(11),
      R => \out\
    );
\di_reg_reg[11]_i_1__0\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[11]_i_2__0_n_0\,
      I1 => \di_reg[11]_i_3__0_n_0\,
      O => di_reg(11),
      S => index(4)
    );
\di_reg_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(12),
      Q => drp_di_16(12),
      R => \out\
    );
\di_reg_reg[12]_i_1__0\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[12]_i_2__0_n_0\,
      I1 => \di_reg[12]_i_3__0_n_0\,
      O => di_reg(12),
      S => index(4)
    );
\di_reg_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(13),
      Q => drp_di_16(13),
      R => \out\
    );
\di_reg_reg[13]_i_1__0\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[13]_i_2__0_n_0\,
      I1 => \di_reg[13]_i_3__0_n_0\,
      O => di_reg(13),
      S => index(4)
    );
\di_reg_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(14),
      Q => drp_di_16(14),
      R => \out\
    );
\di_reg_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(15),
      Q => drp_di_16(15),
      R => \out\
    );
\di_reg_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(1),
      Q => drp_di_16(1),
      R => \out\
    );
\di_reg_reg[1]_i_1__0\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[1]_i_2__0_n_0\,
      I1 => \di_reg[1]_i_3__0_n_0\,
      O => di_reg(1),
      S => index(4)
    );
\di_reg_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(2),
      Q => drp_di_16(2),
      R => \out\
    );
\di_reg_reg[2]_i_1__0\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[2]_i_2__0_n_0\,
      I1 => \di_reg[2]_i_3__0_n_0\,
      O => di_reg(2),
      S => index(4)
    );
\di_reg_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(3),
      Q => drp_di_16(3),
      R => \out\
    );
\di_reg_reg[3]_i_1__0\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[3]_i_2__0_n_0\,
      I1 => \di_reg[3]_i_3__0_n_0\,
      O => di_reg(3),
      S => index(4)
    );
\di_reg_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(4),
      Q => drp_di_16(4),
      R => \out\
    );
\di_reg_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(5),
      Q => drp_di_16(5),
      R => \out\
    );
\di_reg_reg[5]_i_1__0\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[5]_i_2__0_n_0\,
      I1 => \di_reg[5]_i_3__0_n_0\,
      O => di_reg(5),
      S => index(4)
    );
\di_reg_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(6),
      Q => drp_di_16(6),
      R => \out\
    );
\di_reg_reg[6]_i_1__0\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[6]_i_2__0_n_0\,
      I1 => \di_reg[6]_i_3__0_n_0\,
      O => di_reg(6),
      S => index(4)
    );
\di_reg_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(7),
      Q => drp_di_16(7),
      R => \out\
    );
\di_reg_reg[7]_i_1__0\: unisim.vcomponents.MUXF7
     port map (
      I0 => \di_reg[7]_i_2__0_n_0\,
      I1 => \di_reg[7]_i_3__0_n_0\,
      O => di_reg(7),
      S => index(4)
    );
\di_reg_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(8),
      Q => drp_di_16(8),
      R => \out\
    );
\di_reg_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di_reg(9),
      Q => drp_di_16(9),
      R => \out\
    );
\do_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(0),
      Q => do_reg1(0),
      R => \out\
    );
\do_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(10),
      Q => do_reg1(10),
      R => \out\
    );
\do_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(11),
      Q => do_reg1(11),
      R => \out\
    );
\do_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(12),
      Q => do_reg1(12),
      R => \out\
    );
\do_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(13),
      Q => do_reg1(13),
      R => \out\
    );
\do_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(14),
      Q => do_reg1(14),
      R => \out\
    );
\do_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(15),
      Q => do_reg1(15),
      R => \out\
    );
\do_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(1),
      Q => do_reg1(1),
      R => \out\
    );
\do_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(2),
      Q => do_reg1(2),
      R => \out\
    );
\do_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(3),
      Q => do_reg1(3),
      R => \out\
    );
\do_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(4),
      Q => do_reg1(4),
      R => \out\
    );
\do_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(5),
      Q => do_reg1(5),
      R => \out\
    );
\do_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(6),
      Q => do_reg1(6),
      R => \out\
    );
\do_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(7),
      Q => do_reg1(7),
      R => \out\
    );
\do_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(8),
      Q => do_reg1(8),
      R => \out\
    );
\do_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drpdo(9),
      Q => do_reg1(9),
      R => \out\
    );
\do_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(0),
      Q => do_reg2(0),
      R => \out\
    );
\do_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(10),
      Q => do_reg2(10),
      R => \out\
    );
\do_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(11),
      Q => do_reg2(11),
      R => \out\
    );
\do_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(12),
      Q => do_reg2(12),
      R => \out\
    );
\do_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(13),
      Q => do_reg2(13),
      R => \out\
    );
\do_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(14),
      Q => do_reg2(14),
      R => \out\
    );
\do_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(15),
      Q => do_reg2(15),
      R => \out\
    );
\do_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(1),
      Q => do_reg2(1),
      R => \out\
    );
\do_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(2),
      Q => do_reg2(2),
      R => \out\
    );
\do_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(3),
      Q => do_reg2(3),
      R => \out\
    );
\do_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(4),
      Q => do_reg2(4),
      R => \out\
    );
\do_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(5),
      Q => do_reg2(5),
      R => \out\
    );
\do_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(6),
      Q => do_reg2(6),
      R => \out\
    );
\do_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(7),
      Q => do_reg2(7),
      R => \out\
    );
\do_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(8),
      Q => do_reg2(8),
      R => \out\
    );
\do_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(9),
      Q => do_reg2(9),
      R => \out\
    );
\done_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0001"
    )
        port map (
      I0 => \^q\(0),
      I1 => \^q\(2),
      I2 => start_reg2,
      I3 => \^q\(1),
      O => \done_i_1__0_n_0\
    );
done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \done_i_1__0_n_0\,
      Q => D(0),
      R => \out\
    );
\fsm[0]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0377FFFF03770000"
    )
        port map (
      I0 => \fsm1__8\,
      I1 => \^q\(1),
      I2 => rdy_reg2,
      I3 => \^q\(0),
      I4 => \^q\(2),
      I5 => \fsm[0]_i_3__0_n_0\,
      O => fsm(0)
    );
\fsm[0]_i_2__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"1000000110000000"
    )
        port map (
      I0 => index(3),
      I1 => index(1),
      I2 => index(0),
      I3 => index(4),
      I4 => index(2),
      I5 => x16x20_mode_reg2,
      O => \fsm1__8\
    );
\fsm[0]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"47FF47CC"
    )
        port map (
      I0 => rdy_reg2,
      I1 => \^q\(1),
      I2 => load_cnt(0),
      I3 => \^q\(0),
      I4 => start_reg2,
      O => \fsm[0]_i_3__0_n_0\
    );
\fsm[1]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1D501850"
    )
        port map (
      I0 => \^q\(2),
      I1 => rdy_reg2,
      I2 => \^q\(1),
      I3 => \^q\(0),
      I4 => load_cnt(0),
      O => fsm(1)
    );
\fsm[2]_i_1__1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6222"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(1),
      I2 => rdy_reg2,
      I3 => \^q\(0),
      O => fsm(2)
    );
\fsm_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => fsm(0),
      Q => \^q\(0),
      R => \out\
    );
\fsm_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => fsm(1),
      Q => \^q\(1),
      R => \out\
    );
\fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => fsm(2),
      Q => \^q\(2),
      R => \out\
    );
\gt_ch_drp_rdy[1]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      O => gt_ch_drp_rdy(0)
    );
\gtx_channel.gtxe2_channel_i_i_10__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0002"
    )
        port map (
      I0 => ext_ch_gt_drpdi(12),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => drp_di_16(12),
      O => DRPDI(12)
    );
\gtx_channel.gtxe2_channel_i_i_11__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0002"
    )
        port map (
      I0 => ext_ch_gt_drpdi(11),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => drp_di_16(11),
      O => DRPDI(11)
    );
\gtx_channel.gtxe2_channel_i_i_12__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0002"
    )
        port map (
      I0 => ext_ch_gt_drpdi(10),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => drp_di_16(10),
      O => DRPDI(10)
    );
\gtx_channel.gtxe2_channel_i_i_13__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0002"
    )
        port map (
      I0 => ext_ch_gt_drpdi(9),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => drp_di_16(9),
      O => DRPDI(9)
    );
\gtx_channel.gtxe2_channel_i_i_14__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0002"
    )
        port map (
      I0 => ext_ch_gt_drpdi(8),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => drp_di_16(8),
      O => DRPDI(8)
    );
\gtx_channel.gtxe2_channel_i_i_15__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0002"
    )
        port map (
      I0 => ext_ch_gt_drpdi(7),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => drp_di_16(7),
      O => DRPDI(7)
    );
\gtx_channel.gtxe2_channel_i_i_16__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0002"
    )
        port map (
      I0 => ext_ch_gt_drpdi(6),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => drp_di_16(6),
      O => DRPDI(6)
    );
\gtx_channel.gtxe2_channel_i_i_17__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0002"
    )
        port map (
      I0 => ext_ch_gt_drpdi(5),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => drp_di_16(5),
      O => DRPDI(5)
    );
\gtx_channel.gtxe2_channel_i_i_18__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0002"
    )
        port map (
      I0 => ext_ch_gt_drpdi(4),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => drp_di_16(4),
      O => DRPDI(4)
    );
\gtx_channel.gtxe2_channel_i_i_19__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0002"
    )
        port map (
      I0 => ext_ch_gt_drpdi(3),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => drp_di_16(3),
      O => DRPDI(3)
    );
\gtx_channel.gtxe2_channel_i_i_20__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0002"
    )
        port map (
      I0 => ext_ch_gt_drpdi(2),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => drp_di_16(2),
      O => DRPDI(2)
    );
\gtx_channel.gtxe2_channel_i_i_21__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0002"
    )
        port map (
      I0 => ext_ch_gt_drpdi(1),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => drp_di_16(1),
      O => DRPDI(1)
    );
\gtx_channel.gtxe2_channel_i_i_22__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0002"
    )
        port map (
      I0 => ext_ch_gt_drpdi(0),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => drp_di_16(0),
      O => DRPDI(0)
    );
\gtx_channel.gtxe2_channel_i_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"030E"
    )
        port map (
      I0 => ext_ch_gt_drpen(0),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      O => drp_mux_en_1
    );
\gtx_channel.gtxe2_channel_i_i_40__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => \^q\(2),
      I1 => \^q\(0),
      I2 => \^q\(1),
      I3 => ext_ch_gt_drpaddr(8),
      O => DRPADDR(8)
    );
\gtx_channel.gtxe2_channel_i_i_41__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0002"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(7),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => drp_addr_9(7),
      O => DRPADDR(7)
    );
\gtx_channel.gtxe2_channel_i_i_42__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0002"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(6),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => drp_addr_9(6),
      O => DRPADDR(6)
    );
\gtx_channel.gtxe2_channel_i_i_43__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0002"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(5),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => drp_addr_9(5),
      O => DRPADDR(5)
    );
\gtx_channel.gtxe2_channel_i_i_44__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0002"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(4),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => drp_addr_9(4),
      O => DRPADDR(4)
    );
\gtx_channel.gtxe2_channel_i_i_45__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0002"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(3),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => drp_addr_9(3),
      O => DRPADDR(3)
    );
\gtx_channel.gtxe2_channel_i_i_46__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0002"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(2),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => drp_addr_9(2),
      O => DRPADDR(2)
    );
\gtx_channel.gtxe2_channel_i_i_47__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0002"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(1),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => drp_addr_9(1),
      O => DRPADDR(1)
    );
\gtx_channel.gtxe2_channel_i_i_48\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0002"
    )
        port map (
      I0 => ext_ch_gt_drpaddr(0),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => drp_addr_9(0),
      O => DRPADDR(0)
    );
\gtx_channel.gtxe2_channel_i_i_4__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0302"
    )
        port map (
      I0 => ext_ch_gt_drpwe(0),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      O => drp_mux_we_1
    );
\gtx_channel.gtxe2_channel_i_i_7__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0002"
    )
        port map (
      I0 => ext_ch_gt_drpdi(15),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => drp_di_16(15),
      O => DRPDI(15)
    );
\gtx_channel.gtxe2_channel_i_i_8__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0002"
    )
        port map (
      I0 => ext_ch_gt_drpdi(14),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => drp_di_16(14),
      O => DRPDI(14)
    );
\gtx_channel.gtxe2_channel_i_i_9__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFE0002"
    )
        port map (
      I0 => ext_ch_gt_drpdi(13),
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => \^q\(2),
      I4 => drp_di_16(13),
      O => DRPDI(13)
    );
gtxreset_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rst_gtreset,
      Q => gtxreset_reg1,
      R => \out\
    );
gtxreset_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => gtxreset_reg1,
      Q => gtxreset_reg2,
      R => \out\
    );
\index[0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0100"
    )
        port map (
      I0 => \^q\(0),
      I1 => \fsm1__8\,
      I2 => index(0),
      I3 => \^q\(2),
      O => \index[0]_i_1__0_n_0\
    );
\index[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00140000"
    )
        port map (
      I0 => \^q\(0),
      I1 => index(1),
      I2 => index(0),
      I3 => \fsm1__8\,
      I4 => \^q\(2),
      O => \index[1]_i_1__0_n_0\
    );
\index[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000144400000000"
    )
        port map (
      I0 => \^q\(0),
      I1 => index(2),
      I2 => index(1),
      I3 => index(0),
      I4 => \fsm1__8\,
      I5 => \^q\(2),
      O => \index[2]_i_1__0_n_0\
    );
\index[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000144400000000"
    )
        port map (
      I0 => \^q\(0),
      I1 => index(3),
      I2 => index(2),
      I3 => \index[3]_i_2__0_n_0\,
      I4 => \fsm1__8\,
      I5 => \^q\(2),
      O => \index[3]_i_1__0_n_0\
    );
\index[3]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => index(1),
      I1 => index(0),
      O => \index[3]_i_2__0_n_0\
    );
\index[4]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A1"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(0),
      I2 => \^q\(2),
      O => \index[4]_i_1__0_n_0\
    );
\index[4]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000144400000000"
    )
        port map (
      I0 => \^q\(0),
      I1 => index(4),
      I2 => index(3),
      I3 => \index[4]_i_3__0_n_0\,
      I4 => \fsm1__8\,
      I5 => \^q\(2),
      O => \index[4]_i_2__0_n_0\
    );
\index[4]_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => index(2),
      I1 => index(0),
      I2 => index(1),
      O => \index[4]_i_3__0_n_0\
    );
\index_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \index[4]_i_1__0_n_0\,
      D => \index[0]_i_1__0_n_0\,
      Q => index(0),
      R => \out\
    );
\index_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \index[4]_i_1__0_n_0\,
      D => \index[1]_i_1__0_n_0\,
      Q => index(1),
      R => \out\
    );
\index_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \index[4]_i_1__0_n_0\,
      D => \index[2]_i_1__0_n_0\,
      Q => index(2),
      R => \out\
    );
\index_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \index[4]_i_1__0_n_0\,
      D => \index[3]_i_1__0_n_0\,
      Q => index(3),
      R => \out\
    );
\index_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => \index[4]_i_1__0_n_0\,
      D => \index[4]_i_2__0_n_0\,
      Q => index(4),
      R => \out\
    );
\load_cnt[0]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"10"
    )
        port map (
      I0 => \^q\(1),
      I1 => \^q\(2),
      I2 => \^q\(0),
      O => \load_cnt[0]_i_1__1_n_0\
    );
\load_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \load_cnt[0]_i_1__1_n_0\,
      Q => load_cnt(0),
      R => \out\
    );
\rate_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => pipe_tx_rate,
      Q => rate_reg1(0),
      R => \out\
    );
\rate_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => rate_reg1(1),
      R => \out\
    );
\rate_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rate_reg1(0),
      Q => rate_reg2(0),
      R => \out\
    );
\rate_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rate_reg1(1),
      Q => rate_reg2(1),
      R => \out\
    );
rdy_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ext_ch_gt_drprdy(0),
      Q => rdy_reg1,
      R => \out\
    );
rdy_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rdy_reg1,
      Q => rdy_reg2,
      R => \out\
    );
start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rate_drp_start_1,
      Q => start_reg1,
      R => \out\
    );
start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => start_reg1,
      Q => start_reg2,
      R => \out\
    );
x16_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rate_drp_x16x20_mode_1,
      Q => x16_reg1,
      R => \out\
    );
x16_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => x16_reg1,
      Q => x16_reg2,
      R => \out\
    );
x16x20_mode_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rate_drp_x16x20_mode_1,
      Q => x16x20_mode_reg1,
      R => \out\
    );
x16x20_mode_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => x16x20_mode_reg1,
      Q => x16x20_mode_reg2,
      R => \out\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_rate is
  port (
    rate_drp_start_0 : out STD_LOGIC;
    rate_drp_x16x20_mode_0 : out STD_LOGIC;
    rate_cpllpd_0 : out STD_LOGIC;
    qpllpd_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    rate_cpllreset_0 : out STD_LOGIC;
    qpllreset_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    rate_rxpmareset_0 : out STD_LOGIC;
    RXSYSCLKSEL : out STD_LOGIC_VECTOR ( 0 to 0 );
    pclk_sel_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    SYNC_GEN3 : out STD_LOGIC;
    RXRATE : out STD_LOGIC_VECTOR ( 0 to 0 );
    \FSM_onehot_fsm_reg[18]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_rate_fsm : out STD_LOGIC_VECTOR ( 4 downto 0 );
    pipe_rate_idle : out STD_LOGIC;
    rxchbonden_0 : out STD_LOGIC;
    QPLL_DRP_GEN3 : out STD_LOGIC;
    \out\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rate_out_reg[0]_0\ : in STD_LOGIC;
    gt_rxratedone_0 : in STD_LOGIC;
    gt_txratedone_0 : in STD_LOGIC;
    cplllock_reg1_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    QRST_QPLLLOCK : in STD_LOGIC_VECTOR ( 0 to 0 );
    drp_done_reg1_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    SYNC_MMCM_LOCK : in STD_LOGIC;
    gt_txresetdone_0 : in STD_LOGIC;
    gt_rxresetdone_0 : in STD_LOGIC;
    txsync_done_reg1_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \FSM_onehot_fsm_reg[14]_0\ : in STD_LOGIC;
    \FSM_onehot_fsm_reg[20]_0\ : in STD_LOGIC;
    \FSM_onehot_fsm_reg[20]_1\ : in STD_LOGIC;
    pipe_rate_idle_INST_0_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    rate_gen3_1 : in STD_LOGIC;
    pipe_tx_rate : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_rate : entity is "spec7_pcie_7x_0_pipe_rate";
end spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_rate;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_rate is
  signal \FSM_onehot_fsm[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[0]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[12]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[13]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[13]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[13]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[14]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[16]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[18]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[20]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[21]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[23]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[25]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[25]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[27]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[28]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[29]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[6]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[7]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[7]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[7]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[7]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[8]_i_1_n_0\ : STD_LOGIC;
  signal \^fsm_onehot_fsm_reg[18]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \FSM_onehot_fsm_reg_n_0_[12]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[13]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[14]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[15]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[16]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[1]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[20]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[21]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[23]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[24]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[25]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[26]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[27]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[28]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[29]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[4]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[5]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[7]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[8]\ : STD_LOGIC;
  signal \^rxrate\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^rxsysclksel\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^sync_gen3\ : STD_LOGIC;
  signal cplllock_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of cplllock_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of cplllock_reg1 : signal is "true";
  signal cplllock_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of cplllock_reg2 : signal is "NO";
  attribute async_reg of cplllock_reg2 : signal is "true";
  signal cpllpd_i_1_n_0 : STD_LOGIC;
  signal \cpllreset_i_1__0_n_0\ : STD_LOGIC;
  signal drp_done_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of drp_done_reg1 : signal is "NO";
  attribute async_reg of drp_done_reg1 : signal is "true";
  signal drp_done_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of drp_done_reg2 : signal is "NO";
  attribute async_reg of drp_done_reg2 : signal is "true";
  signal drp_start : STD_LOGIC;
  signal drp_x16x20_mode : STD_LOGIC;
  signal gen3_exit_i_1_n_0 : STD_LOGIC;
  signal gen3_exit_reg_n_0 : STD_LOGIC;
  signal gen3_i_1_n_0 : STD_LOGIC;
  signal mmcm_lock_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of mmcm_lock_reg1 : signal is "NO";
  attribute async_reg of mmcm_lock_reg1 : signal is "true";
  signal mmcm_lock_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of mmcm_lock_reg2 : signal is "NO";
  attribute async_reg of mmcm_lock_reg2 : signal is "true";
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \pclk_sel_i_1__0_n_0\ : STD_LOGIC;
  signal \^pclk_sel_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal phystatus_i_1_n_0 : STD_LOGIC;
  signal phystatus_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of phystatus_reg1 : signal is "NO";
  attribute async_reg of phystatus_reg1 : signal is "true";
  signal phystatus_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of phystatus_reg2 : signal is "NO";
  attribute async_reg of phystatus_reg2 : signal is "true";
  signal phystatus_reg_n_0 : STD_LOGIC;
  signal \pipe_rate_fsm[0]_INST_0_i_1_n_0\ : STD_LOGIC;
  signal \pipe_rate_fsm[0]_INST_0_i_2_n_0\ : STD_LOGIC;
  signal \pipe_rate_fsm[0]_INST_0_i_3_n_0\ : STD_LOGIC;
  signal \pipe_rate_fsm[1]_INST_0_i_1_n_0\ : STD_LOGIC;
  signal \pipe_rate_fsm[3]_INST_0_i_1_n_0\ : STD_LOGIC;
  signal \pipe_rate_fsm[3]_INST_0_i_2_n_0\ : STD_LOGIC;
  signal \pipe_rate_fsm[4]_INST_0_i_1_n_0\ : STD_LOGIC;
  signal qplllock_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of qplllock_reg1 : signal is "NO";
  attribute async_reg of qplllock_reg1 : signal is "true";
  signal qplllock_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of qplllock_reg2 : signal is "NO";
  attribute async_reg of qplllock_reg2 : signal is "true";
  signal \qpllpd_i_1__0_n_0\ : STD_LOGIC;
  signal \^qpllpd_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \qpllreset_i_1__0_n_0\ : STD_LOGIC;
  signal \^qpllreset_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^rate_cpllpd_0\ : STD_LOGIC;
  signal \^rate_cpllreset_0\ : STD_LOGIC;
  signal rate_in_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rate_in_reg1 : signal is "NO";
  attribute async_reg of rate_in_reg1 : signal is "true";
  signal rate_in_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rate_in_reg2 : signal is "NO";
  attribute async_reg of rate_in_reg2 : signal is "true";
  signal \rate_out[0]_i_1_n_0\ : STD_LOGIC;
  signal \^rate_rxpmareset_0\ : STD_LOGIC;
  signal ratedone_i_1_n_0 : STD_LOGIC;
  signal ratedone_reg_n_0 : STD_LOGIC;
  signal resetovrd_done_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of resetovrd_done_reg1 : signal is "NO";
  attribute async_reg of resetovrd_done_reg1 : signal is "true";
  signal resetovrd_done_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of resetovrd_done_reg2 : signal is "NO";
  attribute async_reg of resetovrd_done_reg2 : signal is "true";
  signal rst_idle_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rst_idle_reg1 : signal is "NO";
  attribute async_reg of rst_idle_reg1 : signal is "true";
  signal rst_idle_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rst_idle_reg2 : signal is "NO";
  attribute async_reg of rst_idle_reg2 : signal is "true";
  signal rxpmaresetdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxpmaresetdone_reg1 : signal is "NO";
  attribute async_reg of rxpmaresetdone_reg1 : signal is "true";
  signal rxpmaresetdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxpmaresetdone_reg2 : signal is "NO";
  attribute async_reg of rxpmaresetdone_reg2 : signal is "true";
  signal rxratedone_i_1_n_0 : STD_LOGIC;
  signal rxratedone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxratedone_reg1 : signal is "NO";
  attribute async_reg of rxratedone_reg1 : signal is "true";
  signal rxratedone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxratedone_reg2 : signal is "NO";
  attribute async_reg of rxratedone_reg2 : signal is "true";
  signal rxratedone_reg_n_0 : STD_LOGIC;
  signal rxresetdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxresetdone_reg1 : signal is "NO";
  attribute async_reg of rxresetdone_reg1 : signal is "true";
  signal rxresetdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxresetdone_reg2 : signal is "NO";
  attribute async_reg of rxresetdone_reg2 : signal is "true";
  signal rxsync_done_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxsync_done_reg1 : signal is "NO";
  attribute async_reg of rxsync_done_reg1 : signal is "true";
  signal rxsync_done_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxsync_done_reg2 : signal is "NO";
  attribute async_reg of rxsync_done_reg2 : signal is "true";
  signal \sysclksel[0]_i_1_n_0\ : STD_LOGIC;
  signal txdata_wait_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal txpmareset_i_1_n_0 : STD_LOGIC;
  signal txratedone_i_1_n_0 : STD_LOGIC;
  signal txratedone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txratedone_reg1 : signal is "NO";
  attribute async_reg of txratedone_reg1 : signal is "true";
  signal txratedone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txratedone_reg2 : signal is "NO";
  attribute async_reg of txratedone_reg2 : signal is "true";
  signal txratedone_reg_n_0 : STD_LOGIC;
  signal txresetdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txresetdone_reg1 : signal is "NO";
  attribute async_reg of txresetdone_reg1 : signal is "true";
  signal txresetdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txresetdone_reg2 : signal is "NO";
  attribute async_reg of txresetdone_reg2 : signal is "true";
  signal txsync_done_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsync_done_reg1 : signal is "NO";
  attribute async_reg of txsync_done_reg1 : signal is "true";
  signal txsync_done_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsync_done_reg2 : signal is "NO";
  attribute async_reg of txsync_done_reg2 : signal is "true";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_fsm[4]_i_1\ : label is "soft_lutpair40";
  attribute SOFT_HLUTNM of \FSM_onehot_fsm[7]_i_5\ : label is "soft_lutpair41";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[0]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[12]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[13]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[14]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[15]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[16]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[18]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[1]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[20]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[21]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[23]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[24]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[25]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[26]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[27]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[28]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[29]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[4]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[5]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[6]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[7]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[8]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of cplllock_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of cplllock_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of cplllock_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of cplllock_reg2_reg : label is std.standard.true;
  attribute KEEP of cplllock_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of cplllock_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of drp_done_reg1_reg : label is std.standard.true;
  attribute KEEP of drp_done_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of drp_done_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of drp_done_reg2_reg : label is std.standard.true;
  attribute KEEP of drp_done_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of drp_done_reg2_reg : label is "NO";
  attribute SOFT_HLUTNM of drp_start_i_1 : label is "soft_lutpair43";
  attribute SOFT_HLUTNM of drp_x16x20_mode_i_1 : label is "soft_lutpair43";
  attribute SOFT_HLUTNM of gen3_reg1_i_1 : label is "soft_lutpair44";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_5\ : label is "soft_lutpair44";
  attribute ASYNC_REG_boolean of mmcm_lock_reg1_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of mmcm_lock_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of mmcm_lock_reg2_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of mmcm_lock_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of phystatus_reg1_reg : label is std.standard.true;
  attribute KEEP of phystatus_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of phystatus_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of phystatus_reg2_reg : label is std.standard.true;
  attribute KEEP of phystatus_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of phystatus_reg2_reg : label is "NO";
  attribute SOFT_HLUTNM of \pipe_rate_fsm[0]_INST_0_i_2\ : label is "soft_lutpair42";
  attribute SOFT_HLUTNM of \pipe_rate_fsm[3]_INST_0_i_2\ : label is "soft_lutpair42";
  attribute ASYNC_REG_boolean of qplllock_reg1_reg : label is std.standard.true;
  attribute KEEP of qplllock_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of qplllock_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of qplllock_reg2_reg : label is std.standard.true;
  attribute KEEP of qplllock_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of qplllock_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of \rate_in_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_in_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_in_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_in_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_in_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_in_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_in_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_in_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of resetovrd_done_reg1_reg : label is std.standard.true;
  attribute KEEP of resetovrd_done_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of resetovrd_done_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of resetovrd_done_reg2_reg : label is std.standard.true;
  attribute KEEP of resetovrd_done_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of resetovrd_done_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rst_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rst_idle_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rst_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rst_idle_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxpmaresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxpmaresetdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxpmaresetdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxpmaresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxpmaresetdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxpmaresetdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxratedone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxratedone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxratedone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxratedone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxratedone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxratedone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxresetdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxresetdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxsync_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_done_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxsync_done_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxsync_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_done_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxsync_done_reg2_reg : label is "NO";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[0]_i_1\ : label is "soft_lutpair39";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[1]_i_1\ : label is "soft_lutpair40";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[2]_i_1\ : label is "soft_lutpair39";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[3]_i_1\ : label is "soft_lutpair41";
  attribute ASYNC_REG_boolean of txratedone_reg1_reg : label is std.standard.true;
  attribute KEEP of txratedone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txratedone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txratedone_reg2_reg : label is std.standard.true;
  attribute KEEP of txratedone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txratedone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txresetdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txresetdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsync_done_reg1_reg : label is std.standard.true;
  attribute KEEP of txsync_done_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsync_done_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsync_done_reg2_reg : label is std.standard.true;
  attribute KEEP of txsync_done_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsync_done_reg2_reg : label is "NO";
begin
  \FSM_onehot_fsm_reg[18]_0\(2 downto 0) <= \^fsm_onehot_fsm_reg[18]_0\(2 downto 0);
  RXRATE(0) <= \^rxrate\(0);
  RXSYSCLKSEL(0) <= \^rxsysclksel\(0);
  SYNC_GEN3 <= \^sync_gen3\;
  pclk_sel_reg_0(0) <= \^pclk_sel_reg_0\(0);
  qpllpd_reg_0(0) <= \^qpllpd_reg_0\(0);
  qpllreset_reg_0(0) <= \^qpllreset_reg_0\(0);
  rate_cpllpd_0 <= \^rate_cpllpd_0\;
  rate_cpllreset_0 <= \^rate_cpllreset_0\;
  rate_rxpmareset_0 <= \^rate_rxpmareset_0\;
\FSM_onehot_fsm[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF404040"
    )
        port map (
      I0 => rst_idle_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[25]\,
      I2 => \FSM_onehot_fsm[0]_i_2__0_n_0\,
      I3 => \^fsm_onehot_fsm_reg[18]_0\(0),
      I4 => \FSM_onehot_fsm[0]_i_3_n_0\,
      I5 => \^fsm_onehot_fsm_reg[18]_0\(1),
      O => \FSM_onehot_fsm[0]_i_1__0_n_0\
    );
\FSM_onehot_fsm[0]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BA8A0000"
    )
        port map (
      I0 => cplllock_reg2,
      I1 => rate_in_reg2(0),
      I2 => rate_in_reg2(1),
      I3 => qplllock_reg2,
      I4 => drp_done_reg2,
      O => \FSM_onehot_fsm[0]_i_2__0_n_0\
    );
\FSM_onehot_fsm[0]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => rate_in_reg1(1),
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg1(0),
      I3 => rate_in_reg2(0),
      O => \FSM_onehot_fsm[0]_i_3_n_0\
    );
\FSM_onehot_fsm[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8F888888"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[29]\,
      I1 => drp_done_reg2,
      I2 => \FSM_onehot_fsm[13]_i_2_n_0\,
      I3 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I4 => \FSM_onehot_fsm[13]_i_3_n_0\,
      O => \FSM_onehot_fsm[12]_i_1_n_0\
    );
\FSM_onehot_fsm[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F8888888"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[13]\,
      I1 => drp_done_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm[13]_i_2_n_0\,
      I4 => \FSM_onehot_fsm[13]_i_3_n_0\,
      O => \FSM_onehot_fsm[13]_i_1_n_0\
    );
\FSM_onehot_fsm[13]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => rst_idle_reg2,
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg2(0),
      O => \FSM_onehot_fsm[13]_i_2_n_0\
    );
\FSM_onehot_fsm[13]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => qplllock_reg2,
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg2(0),
      I3 => cplllock_reg2,
      O => \FSM_onehot_fsm[13]_i_3_n_0\
    );
\FSM_onehot_fsm[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAAE"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[5]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[14]\,
      I2 => \FSM_onehot_fsm[25]_i_2_n_0\,
      I3 => gen3_exit_reg_n_0,
      I4 => \FSM_onehot_fsm_reg[14]_0\,
      I5 => ratedone_reg_n_0,
      O => \FSM_onehot_fsm[14]_i_1_n_0\
    );
\FSM_onehot_fsm[16]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"54"
    )
        port map (
      I0 => txsync_done_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[16]\,
      I2 => \^fsm_onehot_fsm_reg[18]_0\(2),
      O => \FSM_onehot_fsm[16]_i_1__0_n_0\
    );
\FSM_onehot_fsm[18]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[24]\,
      I1 => \^fsm_onehot_fsm_reg[18]_0\(2),
      I2 => txsync_done_reg2,
      O => \FSM_onehot_fsm[18]_i_1_n_0\
    );
\FSM_onehot_fsm[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABAFFBFAAAAAAAA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[15]\,
      I1 => qplllock_reg2,
      I2 => rate_in_reg2(1),
      I3 => rate_in_reg2(0),
      I4 => cplllock_reg2,
      I5 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => \FSM_onehot_fsm[1]_i_1__0_n_0\
    );
\FSM_onehot_fsm[20]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAA888"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[14]\,
      I1 => ratedone_reg_n_0,
      I2 => \FSM_onehot_fsm_reg[20]_0\,
      I3 => \FSM_onehot_fsm_reg[20]_1\,
      I4 => gen3_exit_reg_n_0,
      I5 => \FSM_onehot_fsm[25]_i_2_n_0\,
      O => \FSM_onehot_fsm[20]_i_1_n_0\
    );
\FSM_onehot_fsm[21]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0808A208"
    )
        port map (
      I0 => \^fsm_onehot_fsm_reg[18]_0\(0),
      I1 => rate_in_reg1(1),
      I2 => rate_in_reg1(0),
      I3 => rate_in_reg2(1),
      I4 => rate_in_reg2(0),
      O => \FSM_onehot_fsm[21]_i_1_n_0\
    );
\FSM_onehot_fsm[23]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A80000000000000"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => qplllock_reg2,
      I2 => \FSM_onehot_fsm[25]_i_2_n_0\,
      I3 => cplllock_reg2,
      I4 => \FSM_onehot_fsm_reg_n_0_[25]\,
      I5 => rst_idle_reg2,
      O => \FSM_onehot_fsm[23]_i_1_n_0\
    );
\FSM_onehot_fsm[25]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0ECE0E0E0ECECECE"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[28]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[25]\,
      I2 => drp_done_reg2,
      I3 => qplllock_reg2,
      I4 => \FSM_onehot_fsm[25]_i_2_n_0\,
      I5 => cplllock_reg2,
      O => \FSM_onehot_fsm[25]_i_1_n_0\
    );
\FSM_onehot_fsm[25]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rate_in_reg2(1),
      I1 => rate_in_reg2(0),
      O => \FSM_onehot_fsm[25]_i_2_n_0\
    );
\FSM_onehot_fsm[27]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FBAA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[26]\,
      I1 => mmcm_lock_reg2,
      I2 => rxpmaresetdone_reg2,
      I3 => \FSM_onehot_fsm_reg_n_0_[27]\,
      O => \FSM_onehot_fsm[27]_i_1_n_0\
    );
\FSM_onehot_fsm[28]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88F88888"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[28]\,
      I1 => drp_done_reg2,
      I2 => mmcm_lock_reg2,
      I3 => rxpmaresetdone_reg2,
      I4 => \FSM_onehot_fsm_reg_n_0_[27]\,
      O => \FSM_onehot_fsm[28]_i_1_n_0\
    );
\FSM_onehot_fsm[29]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"54"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[29]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[13]\,
      O => \FSM_onehot_fsm[29]_i_1_n_0\
    );
\FSM_onehot_fsm[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[7]\,
      I1 => txdata_wait_cnt_reg(1),
      I2 => txdata_wait_cnt_reg(0),
      I3 => txdata_wait_cnt_reg(2),
      I4 => txdata_wait_cnt_reg(3),
      O => \FSM_onehot_fsm[4]_i_1_n_0\
    );
\FSM_onehot_fsm[6]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => txsync_done_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[16]\,
      O => \FSM_onehot_fsm[6]_i_1_n_0\
    );
\FSM_onehot_fsm[7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"88F888F8FFFF88F8"
    )
        port map (
      I0 => \FSM_onehot_fsm[7]_i_2_n_0\,
      I1 => \FSM_onehot_fsm[7]_i_3_n_0\,
      I2 => \FSM_onehot_fsm_reg_n_0_[8]\,
      I3 => \FSM_onehot_fsm[7]_i_4_n_0\,
      I4 => \FSM_onehot_fsm_reg_n_0_[7]\,
      I5 => \FSM_onehot_fsm[7]_i_5_n_0\,
      O => \FSM_onehot_fsm[7]_i_1__0_n_0\
    );
\FSM_onehot_fsm[7]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"B0BB"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg1(0),
      I3 => rate_in_reg1(1),
      O => \FSM_onehot_fsm[7]_i_2_n_0\
    );
\FSM_onehot_fsm[7]_i_3\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"28AAAA28"
    )
        port map (
      I0 => \^fsm_onehot_fsm_reg[18]_0\(0),
      I1 => rate_in_reg2(0),
      I2 => rate_in_reg1(0),
      I3 => rate_in_reg2(1),
      I4 => rate_in_reg1(1),
      O => \FSM_onehot_fsm[7]_i_3_n_0\
    );
\FSM_onehot_fsm[7]_i_4\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"70777777"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg[20]_0\,
      I1 => \FSM_onehot_fsm_reg[20]_1\,
      I2 => phystatus_reg2,
      I3 => rxresetdone_reg2,
      I4 => txresetdone_reg2,
      O => \FSM_onehot_fsm[7]_i_4_n_0\
    );
\FSM_onehot_fsm[7]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => txdata_wait_cnt_reg(3),
      I1 => txdata_wait_cnt_reg(2),
      I2 => txdata_wait_cnt_reg(0),
      I3 => txdata_wait_cnt_reg(1),
      O => \FSM_onehot_fsm[7]_i_5_n_0\
    );
\FSM_onehot_fsm[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BABBBBBBAAAAAAAA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[23]\,
      I1 => \FSM_onehot_fsm_reg[14]_0\,
      I2 => phystatus_reg2,
      I3 => rxresetdone_reg2,
      I4 => txresetdone_reg2,
      I5 => \FSM_onehot_fsm_reg_n_0_[8]\,
      O => \FSM_onehot_fsm[8]_i_1_n_0\
    );
\FSM_onehot_fsm_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[0]_i_1__0_n_0\,
      Q => \^fsm_onehot_fsm_reg[18]_0\(0),
      R => \out\
    );
\FSM_onehot_fsm_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[12]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[12]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[13]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[13]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[14]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[14]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm_reg_n_0_[21]\,
      Q => \FSM_onehot_fsm_reg_n_0_[15]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[16]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[16]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[18]_i_1_n_0\,
      Q => \^fsm_onehot_fsm_reg[18]_0\(2),
      R => \out\
    );
\FSM_onehot_fsm_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[1]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[1]\,
      S => \out\
    );
\FSM_onehot_fsm_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[20]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[20]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[21]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[21]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[23]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[23]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm_reg_n_0_[20]\,
      Q => \FSM_onehot_fsm_reg_n_0_[24]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[25]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[25]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm_reg_n_0_[12]\,
      Q => \FSM_onehot_fsm_reg_n_0_[26]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[27]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[27]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[28]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[28]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[29]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[29]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[4]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[4]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm_reg_n_0_[4]\,
      Q => \FSM_onehot_fsm_reg_n_0_[5]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[6]_i_1_n_0\,
      Q => \^fsm_onehot_fsm_reg[18]_0\(1),
      R => \out\
    );
\FSM_onehot_fsm_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[7]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[7]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[8]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[8]\,
      R => \out\
    );
cplllock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => cplllock_reg1_reg_0(0),
      Q => cplllock_reg1,
      R => \out\
    );
cplllock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => cplllock_reg1,
      Q => cplllock_reg2,
      R => \out\
    );
cpllpd_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"404F4040"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \FSM_onehot_fsm_reg_n_0_[24]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[21]\,
      I4 => \^rate_cpllpd_0\,
      O => cpllpd_i_1_n_0
    );
cpllpd_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => cpllpd_i_1_n_0,
      Q => \^rate_cpllpd_0\,
      R => \out\
    );
\cpllreset_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"404F4040"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \FSM_onehot_fsm_reg_n_0_[20]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[15]\,
      I4 => \^rate_cpllreset_0\,
      O => \cpllreset_i_1__0_n_0\
    );
cpllreset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \cpllreset_i_1__0_n_0\,
      Q => \^rate_cpllreset_0\,
      R => \out\
    );
drp_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => drp_done_reg1_reg_0(0),
      Q => drp_done_reg1,
      R => \out\
    );
drp_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => drp_done_reg1,
      Q => drp_done_reg2,
      R => \out\
    );
drp_start_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[28]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[13]\,
      O => drp_start
    );
drp_start_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => drp_start,
      Q => rate_drp_start_0,
      R => \out\
    );
drp_x16x20_mode_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[29]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[13]\,
      O => drp_x16x20_mode
    );
drp_x16x20_mode_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => drp_x16x20_mode,
      Q => rate_drp_x16x20_mode_0,
      R => \out\
    );
gen3_exit_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F75577D720002200"
    )
        port map (
      I0 => \^fsm_onehot_fsm_reg[18]_0\(0),
      I1 => rate_in_reg2(0),
      I2 => rate_in_reg1(0),
      I3 => rate_in_reg2(1),
      I4 => rate_in_reg1(1),
      I5 => gen3_exit_reg_n_0,
      O => gen3_exit_i_1_n_0
    );
gen3_exit_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => gen3_exit_i_1_n_0,
      Q => gen3_exit_reg_n_0,
      R => \out\
    );
gen3_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F40"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \FSM_onehot_fsm_reg_n_0_[28]\,
      I3 => \^sync_gen3\,
      O => gen3_i_1_n_0
    );
gen3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => gen3_i_1_n_0,
      Q => \^sync_gen3\,
      R => \out\
    );
gen3_reg1_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^sync_gen3\,
      I1 => rate_gen3_1,
      O => QPLL_DRP_GEN3
    );
\gtx_channel.gtxe2_channel_i_i_5\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^sync_gen3\,
      O => rxchbonden_0
    );
mmcm_lock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => SYNC_MMCM_LOCK,
      Q => mmcm_lock_reg1,
      R => \out\
    );
mmcm_lock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => mmcm_lock_reg1,
      Q => mmcm_lock_reg2,
      R => \out\
    );
\pclk_sel_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"02FEFE02"
    )
        port map (
      I0 => \^pclk_sel_reg_0\(0),
      I1 => \FSM_onehot_fsm_reg_n_0_[28]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I3 => rate_in_reg2(0),
      I4 => rate_in_reg2(1),
      O => \pclk_sel_i_1__0_n_0\
    );
pclk_sel_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \pclk_sel_i_1__0_n_0\,
      Q => \^pclk_sel_reg_0\(0),
      R => \out\
    );
phystatus_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => phystatus_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[14]\,
      I2 => phystatus_reg_n_0,
      O => phystatus_i_1_n_0
    );
phystatus_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => phystatus_i_1_n_0,
      Q => phystatus_reg_n_0,
      R => \out\
    );
phystatus_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => D(0),
      Q => phystatus_reg1,
      R => \out\
    );
phystatus_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => phystatus_reg1,
      Q => phystatus_reg2,
      R => \out\
    );
\pipe_rate_fsm[0]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[29]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[5]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[7]\,
      I3 => \pipe_rate_fsm[0]_INST_0_i_1_n_0\,
      I4 => \pipe_rate_fsm[0]_INST_0_i_2_n_0\,
      I5 => \pipe_rate_fsm[0]_INST_0_i_3_n_0\,
      O => pipe_rate_fsm(0)
    );
\pipe_rate_fsm[0]_INST_0_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[24]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[21]\,
      O => \pipe_rate_fsm[0]_INST_0_i_1_n_0\
    );
\pipe_rate_fsm[0]_INST_0_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[28]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[16]\,
      O => \pipe_rate_fsm[0]_INST_0_i_2_n_0\
    );
\pipe_rate_fsm[0]_INST_0_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[26]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[14]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[23]\,
      O => \pipe_rate_fsm[0]_INST_0_i_3_n_0\
    );
\pipe_rate_fsm[1]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[15]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[26]\,
      I3 => \pipe_rate_fsm[1]_INST_0_i_1_n_0\,
      O => pipe_rate_fsm(1)
    );
\pipe_rate_fsm[1]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[23]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[12]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[25]\,
      I4 => \^fsm_onehot_fsm_reg[18]_0\(2),
      I5 => \FSM_onehot_fsm_reg_n_0_[16]\,
      O => \pipe_rate_fsm[1]_INST_0_i_1_n_0\
    );
\pipe_rate_fsm[2]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \pipe_rate_fsm[3]_INST_0_i_1_n_0\,
      I1 => \FSM_onehot_fsm_reg_n_0_[13]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[29]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[12]\,
      I4 => \FSM_onehot_fsm_reg_n_0_[26]\,
      I5 => \FSM_onehot_fsm_reg_n_0_[14]\,
      O => pipe_rate_fsm(2)
    );
\pipe_rate_fsm[3]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \pipe_rate_fsm[3]_INST_0_i_1_n_0\,
      I1 => \pipe_rate_fsm[3]_INST_0_i_2_n_0\,
      I2 => \^fsm_onehot_fsm_reg[18]_0\(2),
      I3 => \FSM_onehot_fsm_reg_n_0_[23]\,
      I4 => \FSM_onehot_fsm_reg_n_0_[27]\,
      I5 => \FSM_onehot_fsm_reg_n_0_[25]\,
      O => pipe_rate_fsm(3)
    );
\pipe_rate_fsm[3]_INST_0_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[7]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[8]\,
      I3 => \^fsm_onehot_fsm_reg[18]_0\(1),
      O => \pipe_rate_fsm[3]_INST_0_i_1_n_0\
    );
\pipe_rate_fsm[3]_INST_0_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[20]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[24]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[16]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[28]\,
      O => \pipe_rate_fsm[3]_INST_0_i_2_n_0\
    );
\pipe_rate_fsm[4]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEFF"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[5]\,
      I1 => \^fsm_onehot_fsm_reg[18]_0\(1),
      I2 => \FSM_onehot_fsm_reg_n_0_[14]\,
      I3 => \pipe_rate_fsm[4]_INST_0_i_1_n_0\,
      I4 => \FSM_onehot_fsm_reg_n_0_[24]\,
      I5 => \FSM_onehot_fsm_reg_n_0_[20]\,
      O => pipe_rate_fsm(4)
    );
\pipe_rate_fsm[4]_INST_0_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^fsm_onehot_fsm_reg[18]_0\(2),
      I1 => \FSM_onehot_fsm_reg_n_0_[16]\,
      O => \pipe_rate_fsm[4]_INST_0_i_1_n_0\
    );
pipe_rate_idle_INST_0: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^fsm_onehot_fsm_reg[18]_0\(0),
      I1 => pipe_rate_idle_INST_0_0(0),
      O => pipe_rate_idle
    );
qplllock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => QRST_QPLLLOCK(0),
      Q => qplllock_reg1,
      R => \out\
    );
qplllock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => qplllock_reg1,
      Q => qplllock_reg2,
      R => \out\
    );
\qpllpd_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B0BFB0B0"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \FSM_onehot_fsm_reg_n_0_[24]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[21]\,
      I4 => \^qpllpd_reg_0\(0),
      O => \qpllpd_i_1__0_n_0\
    );
qpllpd_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \qpllpd_i_1__0_n_0\,
      Q => \^qpllpd_reg_0\(0),
      R => \out\
    );
\qpllreset_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B0BFB0B0"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \FSM_onehot_fsm_reg_n_0_[20]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[15]\,
      I4 => \^qpllreset_reg_0\(0),
      O => \qpllreset_i_1__0_n_0\
    );
qpllreset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \qpllreset_i_1__0_n_0\,
      Q => \^qpllreset_reg_0\(0),
      R => \out\
    );
\rate_in_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => pipe_tx_rate,
      Q => rate_in_reg1(0),
      R => \out\
    );
\rate_in_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => '0',
      Q => rate_in_reg1(1),
      R => \out\
    );
\rate_in_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => rate_in_reg1(0),
      Q => rate_in_reg2(0),
      R => \out\
    );
\rate_in_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => rate_in_reg1(1),
      Q => rate_in_reg2(1),
      R => \out\
    );
\rate_out[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"10F155F500E000A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[5]\,
      I1 => gen3_exit_reg_n_0,
      I2 => rate_in_reg2(0),
      I3 => rate_in_reg2(1),
      I4 => \FSM_onehot_fsm_reg_n_0_[28]\,
      I5 => \^rxrate\(0),
      O => \rate_out[0]_i_1_n_0\
    );
\rate_out_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \rate_out[0]_i_1_n_0\,
      Q => \^rxrate\(0),
      R => \out\
    );
ratedone_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF008000"
    )
        port map (
      I0 => txratedone_reg_n_0,
      I1 => phystatus_reg_n_0,
      I2 => rxratedone_reg_n_0,
      I3 => \FSM_onehot_fsm_reg_n_0_[14]\,
      I4 => ratedone_reg_n_0,
      O => ratedone_i_1_n_0
    );
ratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => ratedone_i_1_n_0,
      Q => ratedone_reg_n_0,
      R => \out\
    );
resetovrd_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => '1',
      Q => resetovrd_done_reg1,
      R => \out\
    );
resetovrd_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => resetovrd_done_reg1,
      Q => resetovrd_done_reg2,
      R => \out\
    );
rst_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => Q(0),
      Q => rst_idle_reg1,
      R => \out\
    );
rst_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => rst_idle_reg1,
      Q => rst_idle_reg2,
      R => \out\
    );
rxpmaresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => '0',
      Q => rxpmaresetdone_reg1,
      R => \out\
    );
rxpmaresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => rxpmaresetdone_reg1,
      Q => rxpmaresetdone_reg2,
      R => \out\
    );
rxratedone_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => rxratedone_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[14]\,
      I2 => rxratedone_reg_n_0,
      O => rxratedone_i_1_n_0
    );
rxratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => rxratedone_i_1_n_0,
      Q => rxratedone_reg_n_0,
      R => \out\
    );
rxratedone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => gt_rxratedone_0,
      Q => rxratedone_reg1,
      R => \out\
    );
rxratedone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => rxratedone_reg1,
      Q => rxratedone_reg2,
      R => \out\
    );
rxresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => gt_rxresetdone_0,
      Q => rxresetdone_reg1,
      R => \out\
    );
rxresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => rxresetdone_reg1,
      Q => rxresetdone_reg2,
      R => \out\
    );
rxsync_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => '0',
      Q => rxsync_done_reg1,
      R => \out\
    );
rxsync_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => rxsync_done_reg1,
      Q => rxsync_done_reg2,
      R => \out\
    );
\sysclksel[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F40"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \FSM_onehot_fsm_reg_n_0_[26]\,
      I3 => \^rxsysclksel\(0),
      O => \sysclksel[0]_i_1_n_0\
    );
\sysclksel_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \sysclksel[0]_i_1_n_0\,
      Q => \^rxsysclksel\(0),
      R => \out\
    );
\txdata_wait_cnt[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80AA00AA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[7]\,
      I1 => txdata_wait_cnt_reg(3),
      I2 => txdata_wait_cnt_reg(2),
      I3 => txdata_wait_cnt_reg(0),
      I4 => txdata_wait_cnt_reg(1),
      O => \p_0_in__0\(0)
    );
\txdata_wait_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8282828"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[7]\,
      I1 => txdata_wait_cnt_reg(0),
      I2 => txdata_wait_cnt_reg(1),
      I3 => txdata_wait_cnt_reg(3),
      I4 => txdata_wait_cnt_reg(2),
      O => \p_0_in__0\(1)
    );
\txdata_wait_cnt[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EA006A00"
    )
        port map (
      I0 => txdata_wait_cnt_reg(2),
      I1 => txdata_wait_cnt_reg(1),
      I2 => txdata_wait_cnt_reg(0),
      I3 => \FSM_onehot_fsm_reg_n_0_[7]\,
      I4 => txdata_wait_cnt_reg(3),
      O => \p_0_in__0\(2)
    );
\txdata_wait_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8888888"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[7]\,
      I1 => txdata_wait_cnt_reg(3),
      I2 => txdata_wait_cnt_reg(1),
      I3 => txdata_wait_cnt_reg(0),
      I4 => txdata_wait_cnt_reg(2),
      O => \p_0_in__0\(3)
    );
\txdata_wait_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \p_0_in__0\(0),
      Q => txdata_wait_cnt_reg(0),
      R => \out\
    );
\txdata_wait_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \p_0_in__0\(1),
      Q => txdata_wait_cnt_reg(1),
      R => \out\
    );
\txdata_wait_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \p_0_in__0\(2),
      Q => txdata_wait_cnt_reg(2),
      R => \out\
    );
\txdata_wait_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \p_0_in__0\(3),
      Q => txdata_wait_cnt_reg(3),
      R => \out\
    );
txpmareset_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F200F2FFF200F200"
    )
        port map (
      I0 => rate_in_reg2(1),
      I1 => rate_in_reg2(0),
      I2 => gen3_exit_reg_n_0,
      I3 => \FSM_onehot_fsm_reg_n_0_[12]\,
      I4 => \FSM_onehot_fsm_reg_n_0_[23]\,
      I5 => \^rate_rxpmareset_0\,
      O => txpmareset_i_1_n_0
    );
txpmareset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => txpmareset_i_1_n_0,
      Q => \^rate_rxpmareset_0\,
      R => \out\
    );
txratedone_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => txratedone_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[14]\,
      I2 => txratedone_reg_n_0,
      O => txratedone_i_1_n_0
    );
txratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => txratedone_i_1_n_0,
      Q => txratedone_reg_n_0,
      R => \out\
    );
txratedone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => gt_txratedone_0,
      Q => txratedone_reg1,
      R => \out\
    );
txratedone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => txratedone_reg1,
      Q => txratedone_reg2,
      R => \out\
    );
txresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => gt_txresetdone_0,
      Q => txresetdone_reg1,
      R => \out\
    );
txresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => txresetdone_reg1,
      Q => txresetdone_reg2,
      R => \out\
    );
txsync_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => txsync_done_reg1_reg_0(0),
      Q => txsync_done_reg1,
      R => \out\
    );
txsync_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => txsync_done_reg1,
      Q => txsync_done_reg2,
      R => \out\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_rate_19 is
  port (
    rate_drp_start_1 : out STD_LOGIC;
    rate_drp_x16x20_mode_1 : out STD_LOGIC;
    rate_cpllpd_1 : out STD_LOGIC;
    qpllpd_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    qpllreset_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    rate_rxpmareset_1 : out STD_LOGIC;
    RXSYSCLKSEL : out STD_LOGIC_VECTOR ( 0 to 0 );
    pclk_sel_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    rate_gen3_1 : out STD_LOGIC;
    RXRATE : out STD_LOGIC_VECTOR ( 0 to 0 );
    \FSM_onehot_fsm_reg[18]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_rate_fsm : out STD_LOGIC_VECTOR ( 4 downto 0 );
    CPLLRESET0 : out STD_LOGIC;
    rxchbonden_1 : out STD_LOGIC;
    \out\ : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 0 to 0 );
    \rate_out_reg[0]_0\ : in STD_LOGIC;
    gt_rxratedone_1 : in STD_LOGIC;
    gt_txratedone_1 : in STD_LOGIC;
    cplllock_reg1_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    QRST_QPLLLOCK : in STD_LOGIC_VECTOR ( 0 to 0 );
    drp_done_reg1_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    SYNC_MMCM_LOCK : in STD_LOGIC;
    gt_txresetdone_1 : in STD_LOGIC;
    gt_rxresetdone_1 : in STD_LOGIC;
    txsync_done_reg1_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    \FSM_onehot_fsm_reg[14]_0\ : in STD_LOGIC;
    \FSM_onehot_fsm_reg[20]_0\ : in STD_LOGIC;
    \FSM_onehot_fsm_reg[20]_1\ : in STD_LOGIC;
    cpllrst : in STD_LOGIC;
    pipe_tx_rate : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_rate_19 : entity is "spec7_pcie_7x_0_pipe_rate";
end spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_rate_19;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_rate_19 is
  signal \FSM_onehot_fsm[0]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[0]_i_2__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[0]_i_3__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[12]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[13]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[13]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[13]_i_3__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[14]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[16]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[18]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[1]_i_1__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[20]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[21]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[23]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[25]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[25]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[27]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[28]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[29]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[7]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[7]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[7]_i_3__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[8]_i_1__0_n_0\ : STD_LOGIC;
  signal \^fsm_onehot_fsm_reg[18]_0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \FSM_onehot_fsm_reg_n_0_[12]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[13]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[14]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[15]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[16]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[1]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[20]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[21]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[23]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[24]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[25]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[26]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[27]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[28]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[29]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[4]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[5]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[7]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[8]\ : STD_LOGIC;
  signal \^rxrate\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^rxsysclksel\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal cplllock_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of cplllock_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of cplllock_reg1 : signal is "true";
  signal cplllock_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of cplllock_reg2 : signal is "NO";
  attribute async_reg of cplllock_reg2 : signal is "true";
  signal \cpllpd_i_1__0_n_0\ : STD_LOGIC;
  signal \cpllreset_i_1__1_n_0\ : STD_LOGIC;
  signal drp_done_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of drp_done_reg1 : signal is "NO";
  attribute async_reg of drp_done_reg1 : signal is "true";
  signal drp_done_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of drp_done_reg2 : signal is "NO";
  attribute async_reg of drp_done_reg2 : signal is "true";
  signal drp_start : STD_LOGIC;
  signal drp_x16x20_mode : STD_LOGIC;
  signal \gen3_exit_i_1__0_n_0\ : STD_LOGIC;
  signal gen3_exit_reg_n_0 : STD_LOGIC;
  signal \gen3_i_1__0_n_0\ : STD_LOGIC;
  signal mmcm_lock_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of mmcm_lock_reg1 : signal is "NO";
  attribute async_reg of mmcm_lock_reg1 : signal is "true";
  signal mmcm_lock_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of mmcm_lock_reg2 : signal is "NO";
  attribute async_reg of mmcm_lock_reg2 : signal is "true";
  signal \p_0_in__3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \pclk_sel_i_1__1_n_0\ : STD_LOGIC;
  signal \^pclk_sel_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \phystatus_i_1__0_n_0\ : STD_LOGIC;
  signal phystatus_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of phystatus_reg1 : signal is "NO";
  attribute async_reg of phystatus_reg1 : signal is "true";
  signal phystatus_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of phystatus_reg2 : signal is "NO";
  attribute async_reg of phystatus_reg2 : signal is "true";
  signal phystatus_reg_n_0 : STD_LOGIC;
  signal \pipe_rate_fsm[5]_INST_0_i_1_n_0\ : STD_LOGIC;
  signal \pipe_rate_fsm[5]_INST_0_i_2_n_0\ : STD_LOGIC;
  signal \pipe_rate_fsm[5]_INST_0_i_3_n_0\ : STD_LOGIC;
  signal \pipe_rate_fsm[6]_INST_0_i_1_n_0\ : STD_LOGIC;
  signal \pipe_rate_fsm[8]_INST_0_i_1_n_0\ : STD_LOGIC;
  signal \pipe_rate_fsm[8]_INST_0_i_2_n_0\ : STD_LOGIC;
  signal \pipe_rate_fsm[9]_INST_0_i_1_n_0\ : STD_LOGIC;
  signal qplllock_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of qplllock_reg1 : signal is "NO";
  attribute async_reg of qplllock_reg1 : signal is "true";
  signal qplllock_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of qplllock_reg2 : signal is "NO";
  attribute async_reg of qplllock_reg2 : signal is "true";
  signal \qpllpd_i_1__1_n_0\ : STD_LOGIC;
  signal \^qpllpd_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \qpllreset_i_1__1_n_0\ : STD_LOGIC;
  signal \^qpllreset_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^rate_cpllpd_1\ : STD_LOGIC;
  signal rate_cpllreset_1 : STD_LOGIC;
  signal \^rate_gen3_1\ : STD_LOGIC;
  signal rate_in_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rate_in_reg1 : signal is "NO";
  attribute async_reg of rate_in_reg1 : signal is "true";
  signal rate_in_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rate_in_reg2 : signal is "NO";
  attribute async_reg of rate_in_reg2 : signal is "true";
  signal \rate_out[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \^rate_rxpmareset_1\ : STD_LOGIC;
  signal \ratedone_i_1__0_n_0\ : STD_LOGIC;
  signal ratedone_reg_n_0 : STD_LOGIC;
  signal resetovrd_done_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of resetovrd_done_reg1 : signal is "NO";
  attribute async_reg of resetovrd_done_reg1 : signal is "true";
  signal resetovrd_done_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of resetovrd_done_reg2 : signal is "NO";
  attribute async_reg of resetovrd_done_reg2 : signal is "true";
  signal rst_idle_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rst_idle_reg1 : signal is "NO";
  attribute async_reg of rst_idle_reg1 : signal is "true";
  signal rst_idle_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rst_idle_reg2 : signal is "NO";
  attribute async_reg of rst_idle_reg2 : signal is "true";
  signal rxpmaresetdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxpmaresetdone_reg1 : signal is "NO";
  attribute async_reg of rxpmaresetdone_reg1 : signal is "true";
  signal rxpmaresetdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxpmaresetdone_reg2 : signal is "NO";
  attribute async_reg of rxpmaresetdone_reg2 : signal is "true";
  signal \rxratedone_i_1__0_n_0\ : STD_LOGIC;
  signal rxratedone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxratedone_reg1 : signal is "NO";
  attribute async_reg of rxratedone_reg1 : signal is "true";
  signal rxratedone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxratedone_reg2 : signal is "NO";
  attribute async_reg of rxratedone_reg2 : signal is "true";
  signal rxratedone_reg_n_0 : STD_LOGIC;
  signal rxresetdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxresetdone_reg1 : signal is "NO";
  attribute async_reg of rxresetdone_reg1 : signal is "true";
  signal rxresetdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxresetdone_reg2 : signal is "NO";
  attribute async_reg of rxresetdone_reg2 : signal is "true";
  signal rxsync_done_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxsync_done_reg1 : signal is "NO";
  attribute async_reg of rxsync_done_reg1 : signal is "true";
  signal rxsync_done_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxsync_done_reg2 : signal is "NO";
  attribute async_reg of rxsync_done_reg2 : signal is "true";
  signal \sysclksel[0]_i_1__0_n_0\ : STD_LOGIC;
  signal txdata_wait_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \txpmareset_i_1__0_n_0\ : STD_LOGIC;
  signal \txratedone_i_1__0_n_0\ : STD_LOGIC;
  signal txratedone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txratedone_reg1 : signal is "NO";
  attribute async_reg of txratedone_reg1 : signal is "true";
  signal txratedone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txratedone_reg2 : signal is "NO";
  attribute async_reg of txratedone_reg2 : signal is "true";
  signal txratedone_reg_n_0 : STD_LOGIC;
  signal txresetdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txresetdone_reg1 : signal is "NO";
  attribute async_reg of txresetdone_reg1 : signal is "true";
  signal txresetdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txresetdone_reg2 : signal is "NO";
  attribute async_reg of txresetdone_reg2 : signal is "true";
  signal txsync_done_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsync_done_reg1 : signal is "NO";
  attribute async_reg of txsync_done_reg1 : signal is "true";
  signal txsync_done_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsync_done_reg2 : signal is "NO";
  attribute async_reg of txsync_done_reg2 : signal is "true";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_fsm[4]_i_1__1\ : label is "soft_lutpair70";
  attribute SOFT_HLUTNM of \FSM_onehot_fsm[7]_i_3__0\ : label is "soft_lutpair68";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[0]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[12]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[13]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[14]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[15]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[16]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[18]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[1]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[20]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[21]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[23]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[24]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[25]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[26]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[27]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[28]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[29]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[4]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[5]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[6]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[7]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[8]\ : label is "FSM_PCLK_SEL:0000000000000000000000000010000,FSM_RXSYNC_START:0000000000000000000000000000100,FSM_DONE:0000000000000000000000001000000,FSM_TXDATA_WAIT:0000000000000000000000010000000,FSM_PMARESET_DONE:0000000000000000000000100000000,FSM_DRP_X20_START:0000000000000000000001000000000,FSM_RXPMARESETDONE:0000000000000000000100000000000,FSM_PLL_LOCK:0000000000000000000000000000010,FSM_PLL_PURESET:0000000000000001000000000000000,FSM_RATE_SEL:0000000000000000000000000100000,FSM_DRP_X16_DONE:0000000000000100000000000000000,FSM_TXSYNC_DONE:0000000000000010000000000000000,FSM_TXSYNC_START:0000000000001000000000000000000,FSM_PLL_PU:0000000001000000000000000000000,FSM_RESETOVRD_DONE:0000000000010000000000000000000,FSM_PMARESET_RELEASE:0000000100000000000000000000000,FSM_RESETOVRD_START:0000000010000000000000000000000,FSM_IDLE:0000000000000000000000000000001,FSM_PLL_PD:0000001000000000000000000000000,FSM_DRP_DONE:0000010000000000000000000000000,FSM_PLL_SEL:0000100000000000000000000000000,FSM_PLL_PDRESET:0000000000100000000000000000000,FSM_RATE_DONE:0000000000000000100000000000000,FSM_PMARESET_HOLD:0000000000000000001000000000000,FSM_DRP_X20_DONE:0000000000000000000010000000000,FSM_DRP_START:0010000000000000000000000000000,FSM_MMCM_LOCK:0001000000000000000000000000000,FSM_RXSYNC_DONE:0000000000000000000000000001000,FSM_DRP_X16_GEN3_DONE:0100000000000000000000000000000,FSM_DRP_X16_START:1000000000000000000000000000000,FSM_DRP_X16_GEN3_START:0000000000000000010000000000000";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of cplllock_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of cplllock_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of cplllock_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of cplllock_reg2_reg : label is std.standard.true;
  attribute KEEP of cplllock_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of cplllock_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of drp_done_reg1_reg : label is std.standard.true;
  attribute KEEP of drp_done_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of drp_done_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of drp_done_reg2_reg : label is std.standard.true;
  attribute KEEP of drp_done_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of drp_done_reg2_reg : label is "NO";
  attribute SOFT_HLUTNM of \drp_start_i_1__0\ : label is "soft_lutpair72";
  attribute SOFT_HLUTNM of \drp_x16x20_mode_i_1__0\ : label is "soft_lutpair72";
  attribute ASYNC_REG_boolean of mmcm_lock_reg1_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of mmcm_lock_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of mmcm_lock_reg2_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of mmcm_lock_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of phystatus_reg1_reg : label is std.standard.true;
  attribute KEEP of phystatus_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of phystatus_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of phystatus_reg2_reg : label is std.standard.true;
  attribute KEEP of phystatus_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of phystatus_reg2_reg : label is "NO";
  attribute SOFT_HLUTNM of \pipe_rate_fsm[5]_INST_0_i_2\ : label is "soft_lutpair71";
  attribute SOFT_HLUTNM of \pipe_rate_fsm[8]_INST_0_i_2\ : label is "soft_lutpair71";
  attribute ASYNC_REG_boolean of qplllock_reg1_reg : label is std.standard.true;
  attribute KEEP of qplllock_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of qplllock_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of qplllock_reg2_reg : label is std.standard.true;
  attribute KEEP of qplllock_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of qplllock_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of \rate_in_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_in_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_in_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_in_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_in_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_in_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_in_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_in_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_in_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of resetovrd_done_reg1_reg : label is std.standard.true;
  attribute KEEP of resetovrd_done_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of resetovrd_done_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of resetovrd_done_reg2_reg : label is std.standard.true;
  attribute KEEP of resetovrd_done_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of resetovrd_done_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rst_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rst_idle_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rst_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rst_idle_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxpmaresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxpmaresetdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxpmaresetdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxpmaresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxpmaresetdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxpmaresetdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxratedone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxratedone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxratedone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxratedone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxratedone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxratedone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxresetdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxresetdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxsync_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_done_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxsync_done_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxsync_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_done_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxsync_done_reg2_reg : label is "NO";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[0]_i_1__0\ : label is "soft_lutpair68";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[1]_i_1__0\ : label is "soft_lutpair69";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[2]_i_1__0\ : label is "soft_lutpair69";
  attribute SOFT_HLUTNM of \txdata_wait_cnt[3]_i_1__0\ : label is "soft_lutpair70";
  attribute ASYNC_REG_boolean of txratedone_reg1_reg : label is std.standard.true;
  attribute KEEP of txratedone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txratedone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txratedone_reg2_reg : label is std.standard.true;
  attribute KEEP of txratedone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txratedone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txresetdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txresetdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsync_done_reg1_reg : label is std.standard.true;
  attribute KEEP of txsync_done_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsync_done_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsync_done_reg2_reg : label is std.standard.true;
  attribute KEEP of txsync_done_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsync_done_reg2_reg : label is "NO";
begin
  \FSM_onehot_fsm_reg[18]_0\(2 downto 0) <= \^fsm_onehot_fsm_reg[18]_0\(2 downto 0);
  RXRATE(0) <= \^rxrate\(0);
  RXSYSCLKSEL(0) <= \^rxsysclksel\(0);
  pclk_sel_reg_0(0) <= \^pclk_sel_reg_0\(0);
  qpllpd_reg_0(0) <= \^qpllpd_reg_0\(0);
  qpllreset_reg_0(0) <= \^qpllreset_reg_0\(0);
  rate_cpllpd_1 <= \^rate_cpllpd_1\;
  rate_gen3_1 <= \^rate_gen3_1\;
  rate_rxpmareset_1 <= \^rate_rxpmareset_1\;
\FSM_onehot_fsm[0]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFF404040"
    )
        port map (
      I0 => rst_idle_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[25]\,
      I2 => \FSM_onehot_fsm[0]_i_2__1_n_0\,
      I3 => \^fsm_onehot_fsm_reg[18]_0\(0),
      I4 => \FSM_onehot_fsm[0]_i_3__0_n_0\,
      I5 => \^fsm_onehot_fsm_reg[18]_0\(1),
      O => \FSM_onehot_fsm[0]_i_1__1_n_0\
    );
\FSM_onehot_fsm[0]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BA8A0000"
    )
        port map (
      I0 => cplllock_reg2,
      I1 => rate_in_reg2(0),
      I2 => rate_in_reg2(1),
      I3 => qplllock_reg2,
      I4 => drp_done_reg2,
      O => \FSM_onehot_fsm[0]_i_2__1_n_0\
    );
\FSM_onehot_fsm[0]_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"9009"
    )
        port map (
      I0 => rate_in_reg1(1),
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg1(0),
      I3 => rate_in_reg2(0),
      O => \FSM_onehot_fsm[0]_i_3__0_n_0\
    );
\FSM_onehot_fsm[12]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8F888888"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[29]\,
      I1 => drp_done_reg2,
      I2 => \FSM_onehot_fsm[13]_i_2__0_n_0\,
      I3 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I4 => \FSM_onehot_fsm[13]_i_3__0_n_0\,
      O => \FSM_onehot_fsm[12]_i_1__0_n_0\
    );
\FSM_onehot_fsm[13]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F8888888"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[13]\,
      I1 => drp_done_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm[13]_i_2__0_n_0\,
      I4 => \FSM_onehot_fsm[13]_i_3__0_n_0\,
      O => \FSM_onehot_fsm[13]_i_1__0_n_0\
    );
\FSM_onehot_fsm[13]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"8A"
    )
        port map (
      I0 => rst_idle_reg2,
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg2(0),
      O => \FSM_onehot_fsm[13]_i_2__0_n_0\
    );
\FSM_onehot_fsm[13]_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FB08"
    )
        port map (
      I0 => qplllock_reg2,
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg2(0),
      I3 => cplllock_reg2,
      O => \FSM_onehot_fsm[13]_i_3__0_n_0\
    );
\FSM_onehot_fsm[14]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAAAAE"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[5]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[14]\,
      I2 => \FSM_onehot_fsm[25]_i_2__0_n_0\,
      I3 => gen3_exit_reg_n_0,
      I4 => \FSM_onehot_fsm_reg[14]_0\,
      I5 => ratedone_reg_n_0,
      O => \FSM_onehot_fsm[14]_i_1__0_n_0\
    );
\FSM_onehot_fsm[16]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"54"
    )
        port map (
      I0 => txsync_done_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[16]\,
      I2 => \^fsm_onehot_fsm_reg[18]_0\(2),
      O => \FSM_onehot_fsm[16]_i_1_n_0\
    );
\FSM_onehot_fsm[18]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[24]\,
      I1 => \^fsm_onehot_fsm_reg[18]_0\(2),
      I2 => txsync_done_reg2,
      O => \FSM_onehot_fsm[18]_i_1__0_n_0\
    );
\FSM_onehot_fsm[1]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AABAFFBFAAAAAAAA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[15]\,
      I1 => qplllock_reg2,
      I2 => rate_in_reg2(1),
      I3 => rate_in_reg2(0),
      I4 => cplllock_reg2,
      I5 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => \FSM_onehot_fsm[1]_i_1__2_n_0\
    );
\FSM_onehot_fsm[20]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAA888"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[14]\,
      I1 => ratedone_reg_n_0,
      I2 => \FSM_onehot_fsm_reg[20]_0\,
      I3 => \FSM_onehot_fsm_reg[20]_1\,
      I4 => gen3_exit_reg_n_0,
      I5 => \FSM_onehot_fsm[25]_i_2__0_n_0\,
      O => \FSM_onehot_fsm[20]_i_1__0_n_0\
    );
\FSM_onehot_fsm[21]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0808A208"
    )
        port map (
      I0 => \^fsm_onehot_fsm_reg[18]_0\(0),
      I1 => rate_in_reg1(1),
      I2 => rate_in_reg1(0),
      I3 => rate_in_reg2(1),
      I4 => rate_in_reg2(0),
      O => \FSM_onehot_fsm[21]_i_1__0_n_0\
    );
\FSM_onehot_fsm[23]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8A80000000000000"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => qplllock_reg2,
      I2 => \FSM_onehot_fsm[25]_i_2__0_n_0\,
      I3 => cplllock_reg2,
      I4 => \FSM_onehot_fsm_reg_n_0_[25]\,
      I5 => rst_idle_reg2,
      O => \FSM_onehot_fsm[23]_i_1__0_n_0\
    );
\FSM_onehot_fsm[25]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0ECE0E0E0ECECECE"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[28]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[25]\,
      I2 => drp_done_reg2,
      I3 => qplllock_reg2,
      I4 => \FSM_onehot_fsm[25]_i_2__0_n_0\,
      I5 => cplllock_reg2,
      O => \FSM_onehot_fsm[25]_i_1__0_n_0\
    );
\FSM_onehot_fsm[25]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => rate_in_reg2(1),
      I1 => rate_in_reg2(0),
      O => \FSM_onehot_fsm[25]_i_2__0_n_0\
    );
\FSM_onehot_fsm[27]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FBAA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[26]\,
      I1 => mmcm_lock_reg2,
      I2 => rxpmaresetdone_reg2,
      I3 => \FSM_onehot_fsm_reg_n_0_[27]\,
      O => \FSM_onehot_fsm[27]_i_1__0_n_0\
    );
\FSM_onehot_fsm[28]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88F88888"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[28]\,
      I1 => drp_done_reg2,
      I2 => mmcm_lock_reg2,
      I3 => rxpmaresetdone_reg2,
      I4 => \FSM_onehot_fsm_reg_n_0_[27]\,
      O => \FSM_onehot_fsm[28]_i_1__0_n_0\
    );
\FSM_onehot_fsm[29]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"54"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[29]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[13]\,
      O => \FSM_onehot_fsm[29]_i_1__0_n_0\
    );
\FSM_onehot_fsm[4]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[7]\,
      I1 => txdata_wait_cnt_reg(1),
      I2 => txdata_wait_cnt_reg(0),
      I3 => txdata_wait_cnt_reg(2),
      I4 => txdata_wait_cnt_reg(3),
      O => \FSM_onehot_fsm[4]_i_1__1_n_0\
    );
\FSM_onehot_fsm[6]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => txsync_done_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[16]\,
      O => \FSM_onehot_fsm[6]_i_1__0_n_0\
    );
\FSM_onehot_fsm[7]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF309A0000"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => rate_in_reg1(0),
      I3 => rate_in_reg1(1),
      I4 => \^fsm_onehot_fsm_reg[18]_0\(0),
      I5 => \FSM_onehot_fsm[7]_i_2__0_n_0\,
      O => \FSM_onehot_fsm[7]_i_1__1_n_0\
    );
\FSM_onehot_fsm[7]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EFEEEEEEAAAAAAAA"
    )
        port map (
      I0 => \FSM_onehot_fsm[7]_i_3__0_n_0\,
      I1 => \FSM_onehot_fsm_reg[14]_0\,
      I2 => phystatus_reg2,
      I3 => rxresetdone_reg2,
      I4 => txresetdone_reg2,
      I5 => \FSM_onehot_fsm_reg_n_0_[8]\,
      O => \FSM_onehot_fsm[7]_i_2__0_n_0\
    );
\FSM_onehot_fsm[7]_i_3__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2AAAAAAA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[7]\,
      I1 => txdata_wait_cnt_reg(1),
      I2 => txdata_wait_cnt_reg(0),
      I3 => txdata_wait_cnt_reg(2),
      I4 => txdata_wait_cnt_reg(3),
      O => \FSM_onehot_fsm[7]_i_3__0_n_0\
    );
\FSM_onehot_fsm[8]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BABBBBBBAAAAAAAA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[23]\,
      I1 => \FSM_onehot_fsm_reg[14]_0\,
      I2 => phystatus_reg2,
      I3 => rxresetdone_reg2,
      I4 => txresetdone_reg2,
      I5 => \FSM_onehot_fsm_reg_n_0_[8]\,
      O => \FSM_onehot_fsm[8]_i_1__0_n_0\
    );
\FSM_onehot_fsm_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[0]_i_1__1_n_0\,
      Q => \^fsm_onehot_fsm_reg[18]_0\(0),
      R => \out\
    );
\FSM_onehot_fsm_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[12]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[12]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[13]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[13]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[14]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[14]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm_reg_n_0_[21]\,
      Q => \FSM_onehot_fsm_reg_n_0_[15]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[16]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[16]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[18]_i_1__0_n_0\,
      Q => \^fsm_onehot_fsm_reg[18]_0\(2),
      R => \out\
    );
\FSM_onehot_fsm_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[1]_i_1__2_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[1]\,
      S => \out\
    );
\FSM_onehot_fsm_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[20]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[20]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[21]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[21]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[23]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[23]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[23]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[24]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm_reg_n_0_[20]\,
      Q => \FSM_onehot_fsm_reg_n_0_[24]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[25]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[25]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[25]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[26]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm_reg_n_0_[12]\,
      Q => \FSM_onehot_fsm_reg_n_0_[26]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[27]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[27]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[27]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[28]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[28]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[28]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[29]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[29]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[29]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[4]_i_1__1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[4]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm_reg_n_0_[4]\,
      Q => \FSM_onehot_fsm_reg_n_0_[5]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[6]_i_1__0_n_0\,
      Q => \^fsm_onehot_fsm_reg[18]_0\(1),
      R => \out\
    );
\FSM_onehot_fsm_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[7]_i_1__1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[7]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[8]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[8]\,
      R => \out\
    );
cplllock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => cplllock_reg1_reg_0(0),
      Q => cplllock_reg1,
      R => \out\
    );
cplllock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => cplllock_reg1,
      Q => cplllock_reg2,
      R => \out\
    );
\cpllpd_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"404F4040"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \FSM_onehot_fsm_reg_n_0_[24]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[21]\,
      I4 => \^rate_cpllpd_1\,
      O => \cpllpd_i_1__0_n_0\
    );
cpllpd_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \cpllpd_i_1__0_n_0\,
      Q => \^rate_cpllpd_1\,
      R => \out\
    );
\cpllreset_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"404F4040"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \FSM_onehot_fsm_reg_n_0_[20]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[15]\,
      I4 => rate_cpllreset_1,
      O => \cpllreset_i_1__1_n_0\
    );
cpllreset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \cpllreset_i_1__1_n_0\,
      Q => rate_cpllreset_1,
      R => \out\
    );
drp_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => drp_done_reg1_reg_0(0),
      Q => drp_done_reg1,
      R => \out\
    );
drp_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => drp_done_reg1,
      Q => drp_done_reg2,
      R => \out\
    );
\drp_start_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[28]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[13]\,
      O => drp_start
    );
drp_start_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => drp_start,
      Q => rate_drp_start_1,
      R => \out\
    );
\drp_x16x20_mode_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[29]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[13]\,
      O => drp_x16x20_mode
    );
drp_x16x20_mode_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => drp_x16x20_mode,
      Q => rate_drp_x16x20_mode_1,
      R => \out\
    );
\gen3_exit_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F75577D720002200"
    )
        port map (
      I0 => \^fsm_onehot_fsm_reg[18]_0\(0),
      I1 => rate_in_reg2(0),
      I2 => rate_in_reg1(0),
      I3 => rate_in_reg2(1),
      I4 => rate_in_reg1(1),
      I5 => gen3_exit_reg_n_0,
      O => \gen3_exit_i_1__0_n_0\
    );
gen3_exit_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \gen3_exit_i_1__0_n_0\,
      Q => gen3_exit_reg_n_0,
      R => \out\
    );
\gen3_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F40"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \FSM_onehot_fsm_reg_n_0_[28]\,
      I3 => \^rate_gen3_1\,
      O => \gen3_i_1__0_n_0\
    );
gen3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \gen3_i_1__0_n_0\,
      Q => \^rate_gen3_1\,
      R => \out\
    );
\gtx_channel.gtxe2_channel_i_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => rate_cpllreset_1,
      I1 => \out\,
      I2 => cpllrst,
      O => CPLLRESET0
    );
\gtx_channel.gtxe2_channel_i_i_5__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^rate_gen3_1\,
      O => rxchbonden_1
    );
mmcm_lock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => SYNC_MMCM_LOCK,
      Q => mmcm_lock_reg1,
      R => \out\
    );
mmcm_lock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => mmcm_lock_reg1,
      Q => mmcm_lock_reg2,
      R => \out\
    );
\pclk_sel_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"02FEFE02"
    )
        port map (
      I0 => \^pclk_sel_reg_0\(0),
      I1 => \FSM_onehot_fsm_reg_n_0_[28]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I3 => rate_in_reg2(0),
      I4 => rate_in_reg2(1),
      O => \pclk_sel_i_1__1_n_0\
    );
pclk_sel_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \pclk_sel_i_1__1_n_0\,
      Q => \^pclk_sel_reg_0\(0),
      R => \out\
    );
\phystatus_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => phystatus_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[14]\,
      I2 => phystatus_reg_n_0,
      O => \phystatus_i_1__0_n_0\
    );
phystatus_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \phystatus_i_1__0_n_0\,
      Q => phystatus_reg_n_0,
      R => \out\
    );
phystatus_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => D(0),
      Q => phystatus_reg1,
      R => \out\
    );
phystatus_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => phystatus_reg1,
      Q => phystatus_reg2,
      R => \out\
    );
\pipe_rate_fsm[5]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[29]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[5]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[7]\,
      I3 => \pipe_rate_fsm[5]_INST_0_i_1_n_0\,
      I4 => \pipe_rate_fsm[5]_INST_0_i_2_n_0\,
      I5 => \pipe_rate_fsm[5]_INST_0_i_3_n_0\,
      O => pipe_rate_fsm(0)
    );
\pipe_rate_fsm[5]_INST_0_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[24]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[21]\,
      O => \pipe_rate_fsm[5]_INST_0_i_1_n_0\
    );
\pipe_rate_fsm[5]_INST_0_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[28]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[16]\,
      O => \pipe_rate_fsm[5]_INST_0_i_2_n_0\
    );
\pipe_rate_fsm[5]_INST_0_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[26]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[14]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[23]\,
      O => \pipe_rate_fsm[5]_INST_0_i_3_n_0\
    );
\pipe_rate_fsm[6]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[15]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[25]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I3 => \pipe_rate_fsm[6]_INST_0_i_1_n_0\,
      O => pipe_rate_fsm(1)
    );
\pipe_rate_fsm[6]_INST_0_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[16]\,
      I1 => \^fsm_onehot_fsm_reg[18]_0\(2),
      I2 => \FSM_onehot_fsm_reg_n_0_[26]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I4 => \FSM_onehot_fsm_reg_n_0_[12]\,
      I5 => \FSM_onehot_fsm_reg_n_0_[23]\,
      O => \pipe_rate_fsm[6]_INST_0_i_1_n_0\
    );
\pipe_rate_fsm[7]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \pipe_rate_fsm[8]_INST_0_i_1_n_0\,
      I1 => \FSM_onehot_fsm_reg_n_0_[13]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[29]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[12]\,
      I4 => \FSM_onehot_fsm_reg_n_0_[26]\,
      I5 => \FSM_onehot_fsm_reg_n_0_[14]\,
      O => pipe_rate_fsm(2)
    );
\pipe_rate_fsm[8]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \pipe_rate_fsm[8]_INST_0_i_1_n_0\,
      I1 => \pipe_rate_fsm[8]_INST_0_i_2_n_0\,
      I2 => \^fsm_onehot_fsm_reg[18]_0\(2),
      I3 => \FSM_onehot_fsm_reg_n_0_[23]\,
      I4 => \FSM_onehot_fsm_reg_n_0_[27]\,
      I5 => \FSM_onehot_fsm_reg_n_0_[25]\,
      O => pipe_rate_fsm(3)
    );
\pipe_rate_fsm[8]_INST_0_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[7]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[8]\,
      I3 => \^fsm_onehot_fsm_reg[18]_0\(1),
      O => \pipe_rate_fsm[8]_INST_0_i_1_n_0\
    );
\pipe_rate_fsm[8]_INST_0_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[20]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[24]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[16]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[28]\,
      O => \pipe_rate_fsm[8]_INST_0_i_2_n_0\
    );
\pipe_rate_fsm[9]_INST_0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEFF"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[5]\,
      I1 => \^fsm_onehot_fsm_reg[18]_0\(1),
      I2 => \FSM_onehot_fsm_reg_n_0_[14]\,
      I3 => \pipe_rate_fsm[9]_INST_0_i_1_n_0\,
      I4 => \FSM_onehot_fsm_reg_n_0_[24]\,
      I5 => \FSM_onehot_fsm_reg_n_0_[20]\,
      O => pipe_rate_fsm(4)
    );
\pipe_rate_fsm[9]_INST_0_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^fsm_onehot_fsm_reg[18]_0\(2),
      I1 => \FSM_onehot_fsm_reg_n_0_[16]\,
      O => \pipe_rate_fsm[9]_INST_0_i_1_n_0\
    );
qplllock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => QRST_QPLLLOCK(0),
      Q => qplllock_reg1,
      R => \out\
    );
qplllock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => qplllock_reg1,
      Q => qplllock_reg2,
      R => \out\
    );
\qpllpd_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B0BFB0B0"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \FSM_onehot_fsm_reg_n_0_[24]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[21]\,
      I4 => \^qpllpd_reg_0\(0),
      O => \qpllpd_i_1__1_n_0\
    );
qpllpd_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \qpllpd_i_1__1_n_0\,
      Q => \^qpllpd_reg_0\(0),
      R => \out\
    );
\qpllreset_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"B0BFB0B0"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \FSM_onehot_fsm_reg_n_0_[20]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[15]\,
      I4 => \^qpllreset_reg_0\(0),
      O => \qpllreset_i_1__1_n_0\
    );
qpllreset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \qpllreset_i_1__1_n_0\,
      Q => \^qpllreset_reg_0\(0),
      R => \out\
    );
\rate_in_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => pipe_tx_rate,
      Q => rate_in_reg1(0),
      R => \out\
    );
\rate_in_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => '0',
      Q => rate_in_reg1(1),
      R => \out\
    );
\rate_in_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => rate_in_reg1(0),
      Q => rate_in_reg2(0),
      R => \out\
    );
\rate_in_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => rate_in_reg1(1),
      Q => rate_in_reg2(1),
      R => \out\
    );
\rate_out[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"10F155F500E000A0"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[5]\,
      I1 => gen3_exit_reg_n_0,
      I2 => rate_in_reg2(0),
      I3 => rate_in_reg2(1),
      I4 => \FSM_onehot_fsm_reg_n_0_[28]\,
      I5 => \^rxrate\(0),
      O => \rate_out[0]_i_1__0_n_0\
    );
\rate_out_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \rate_out[0]_i_1__0_n_0\,
      Q => \^rxrate\(0),
      R => \out\
    );
\ratedone_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF008000"
    )
        port map (
      I0 => txratedone_reg_n_0,
      I1 => phystatus_reg_n_0,
      I2 => rxratedone_reg_n_0,
      I3 => \FSM_onehot_fsm_reg_n_0_[14]\,
      I4 => ratedone_reg_n_0,
      O => \ratedone_i_1__0_n_0\
    );
ratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \ratedone_i_1__0_n_0\,
      Q => ratedone_reg_n_0,
      R => \out\
    );
resetovrd_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => '1',
      Q => resetovrd_done_reg1,
      R => \out\
    );
resetovrd_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => resetovrd_done_reg1,
      Q => resetovrd_done_reg2,
      R => \out\
    );
rst_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => Q(0),
      Q => rst_idle_reg1,
      R => \out\
    );
rst_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => rst_idle_reg1,
      Q => rst_idle_reg2,
      R => \out\
    );
rxpmaresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => '0',
      Q => rxpmaresetdone_reg1,
      R => \out\
    );
rxpmaresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => rxpmaresetdone_reg1,
      Q => rxpmaresetdone_reg2,
      R => \out\
    );
\rxratedone_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => rxratedone_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[14]\,
      I2 => rxratedone_reg_n_0,
      O => \rxratedone_i_1__0_n_0\
    );
rxratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \rxratedone_i_1__0_n_0\,
      Q => rxratedone_reg_n_0,
      R => \out\
    );
rxratedone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => gt_rxratedone_1,
      Q => rxratedone_reg1,
      R => \out\
    );
rxratedone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => rxratedone_reg1,
      Q => rxratedone_reg2,
      R => \out\
    );
rxresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => gt_rxresetdone_1,
      Q => rxresetdone_reg1,
      R => \out\
    );
rxresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => rxresetdone_reg1,
      Q => rxresetdone_reg2,
      R => \out\
    );
rxsync_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => '0',
      Q => rxsync_done_reg1,
      R => \out\
    );
rxsync_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => rxsync_done_reg1,
      Q => rxsync_done_reg2,
      R => \out\
    );
\sysclksel[0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4F40"
    )
        port map (
      I0 => rate_in_reg2(0),
      I1 => rate_in_reg2(1),
      I2 => \FSM_onehot_fsm_reg_n_0_[26]\,
      I3 => \^rxsysclksel\(0),
      O => \sysclksel[0]_i_1__0_n_0\
    );
\sysclksel_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \sysclksel[0]_i_1__0_n_0\,
      Q => \^rxsysclksel\(0),
      R => \out\
    );
\txdata_wait_cnt[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80AA00AA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[7]\,
      I1 => txdata_wait_cnt_reg(3),
      I2 => txdata_wait_cnt_reg(2),
      I3 => txdata_wait_cnt_reg(0),
      I4 => txdata_wait_cnt_reg(1),
      O => \p_0_in__3\(0)
    );
\txdata_wait_cnt[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"E0606060"
    )
        port map (
      I0 => txdata_wait_cnt_reg(0),
      I1 => txdata_wait_cnt_reg(1),
      I2 => \FSM_onehot_fsm_reg_n_0_[7]\,
      I3 => txdata_wait_cnt_reg(2),
      I4 => txdata_wait_cnt_reg(3),
      O => \p_0_in__3\(1)
    );
\txdata_wait_cnt[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EA006A00"
    )
        port map (
      I0 => txdata_wait_cnt_reg(2),
      I1 => txdata_wait_cnt_reg(1),
      I2 => txdata_wait_cnt_reg(0),
      I3 => \FSM_onehot_fsm_reg_n_0_[7]\,
      I4 => txdata_wait_cnt_reg(3),
      O => \p_0_in__3\(2)
    );
\txdata_wait_cnt[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8888888"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[7]\,
      I1 => txdata_wait_cnt_reg(3),
      I2 => txdata_wait_cnt_reg(1),
      I3 => txdata_wait_cnt_reg(0),
      I4 => txdata_wait_cnt_reg(2),
      O => \p_0_in__3\(3)
    );
\txdata_wait_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \p_0_in__3\(0),
      Q => txdata_wait_cnt_reg(0),
      R => \out\
    );
\txdata_wait_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \p_0_in__3\(1),
      Q => txdata_wait_cnt_reg(1),
      R => \out\
    );
\txdata_wait_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \p_0_in__3\(2),
      Q => txdata_wait_cnt_reg(2),
      R => \out\
    );
\txdata_wait_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \p_0_in__3\(3),
      Q => txdata_wait_cnt_reg(3),
      R => \out\
    );
\txpmareset_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F200F2FFF200F200"
    )
        port map (
      I0 => rate_in_reg2(1),
      I1 => rate_in_reg2(0),
      I2 => gen3_exit_reg_n_0,
      I3 => \FSM_onehot_fsm_reg_n_0_[12]\,
      I4 => \FSM_onehot_fsm_reg_n_0_[23]\,
      I5 => \^rate_rxpmareset_1\,
      O => \txpmareset_i_1__0_n_0\
    );
txpmareset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \txpmareset_i_1__0_n_0\,
      Q => \^rate_rxpmareset_1\,
      R => \out\
    );
\txratedone_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => txratedone_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[14]\,
      I2 => txratedone_reg_n_0,
      O => \txratedone_i_1__0_n_0\
    );
txratedone_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => \txratedone_i_1__0_n_0\,
      Q => txratedone_reg_n_0,
      R => \out\
    );
txratedone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => gt_txratedone_1,
      Q => txratedone_reg1,
      R => \out\
    );
txratedone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => txratedone_reg1,
      Q => txratedone_reg2,
      R => \out\
    );
txresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => gt_txresetdone_1,
      Q => txresetdone_reg1,
      R => \out\
    );
txresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => txresetdone_reg1,
      Q => txresetdone_reg2,
      R => \out\
    );
txsync_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => txsync_done_reg1_reg_0(0),
      Q => txsync_done_reg1,
      R => \out\
    );
txsync_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rate_out_reg[0]_0\,
      CE => '1',
      D => txsync_done_reg1,
      Q => txsync_done_reg2,
      R => \out\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_reset is
  port (
    \out\ : out STD_LOGIC;
    rxusrclk_rst_reg2_reg_0 : out STD_LOGIC;
    dclk_rst_reg2_reg_0 : out STD_LOGIC;
    reset_n_reg2_reg : out STD_LOGIC;
    rst_gtreset : out STD_LOGIC;
    rst_userrdy : out STD_LOGIC;
    pipe_rst_fsm : out STD_LOGIC_VECTOR ( 3 downto 0 );
    CPLLRESET0 : out STD_LOGIC;
    SYNC_TXSYNC_START : out STD_LOGIC;
    \FSM_onehot_fsm_reg[3]_0\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
    SYNC_MMCM_LOCK : in STD_LOGIC;
    \rxcdrlock_reg2_reg[1]_0\ : in STD_LOGIC;
    CLK : in STD_LOGIC;
    QRST_IDLE : in STD_LOGIC;
    \cfg_wait_cnt_reg[0]_0\ : in STD_LOGIC;
    rate_cpllreset_0 : in STD_LOGIC;
    cpllrst : in STD_LOGIC;
    txsync_start_reg1_reg : in STD_LOGIC_VECTOR ( 1 downto 0 );
    txsync_start_reg1_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    D : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \cplllock_reg1_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \drp_done_reg1_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \phystatus_reg1_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \txsync_done_reg1_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \rxcdrlock_reg1_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_reset : entity is "spec7_pcie_7x_0_pipe_reset";
end spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_reset;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_reset is
  signal \FSM_onehot_fsm[0]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[0]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[10]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[13]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[14]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[1]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_1__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[5]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[8]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[9]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[0]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[13]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[14]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[1]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[4]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[8]\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \cfg_wait_cnt[5]_i_2_n_0\ : STD_LOGIC;
  signal cfg_wait_cnt_reg : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal cplllock_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of cplllock_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of cplllock_reg1 : signal is "true";
  signal cplllock_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of cplllock_reg2 : signal is "NO";
  attribute async_reg of cplllock_reg2 : signal is "true";
  signal cpllpd : STD_LOGIC;
  signal cpllreset : STD_LOGIC;
  signal cpllreset_i_1_n_0 : STD_LOGIC;
  signal cpllreset_i_2_n_0 : STD_LOGIC;
  signal dclk_rst : STD_LOGIC;
  signal dclk_rst_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of dclk_rst_reg1 : signal is "NO";
  attribute async_reg of dclk_rst_reg1 : signal is "true";
  signal dclk_rst_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of dclk_rst_reg2 : signal is "NO";
  attribute async_reg of dclk_rst_reg2 : signal is "true";
  signal drp_done_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of drp_done_reg1 : signal is "NO";
  attribute async_reg of drp_done_reg1 : signal is "true";
  signal drp_done_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of drp_done_reg2 : signal is "NO";
  attribute async_reg of drp_done_reg2 : signal is "true";
  signal gtreset_i_1_n_0 : STD_LOGIC;
  signal mmcm_lock_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of mmcm_lock_reg1 : signal is "NO";
  attribute async_reg of mmcm_lock_reg1 : signal is "true";
  signal mmcm_lock_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of mmcm_lock_reg2 : signal is "NO";
  attribute async_reg of mmcm_lock_reg2 : signal is "true";
  signal p_0_in : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal phystatus_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of phystatus_reg1 : signal is "NO";
  attribute async_reg of phystatus_reg1 : signal is "true";
  signal phystatus_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of phystatus_reg2 : signal is "NO";
  attribute async_reg of phystatus_reg2 : signal is "true";
  signal \pipe_rst_fsm[2]_INST_0_i_1_n_0\ : STD_LOGIC;
  signal qpll_idle_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of qpll_idle_reg1 : signal is "NO";
  attribute async_reg of qpll_idle_reg1 : signal is "true";
  signal qpll_idle_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of qpll_idle_reg2 : signal is "NO";
  attribute async_reg of qpll_idle_reg2 : signal is "true";
  signal rate_idle_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rate_idle_reg1 : signal is "NO";
  attribute async_reg of rate_idle_reg1 : signal is "true";
  signal rate_idle_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rate_idle_reg2 : signal is "NO";
  attribute async_reg of rate_idle_reg2 : signal is "true";
  signal \^reset_n_reg2_reg\ : STD_LOGIC;
  signal resetdone_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of resetdone_reg1 : signal is "NO";
  attribute async_reg of resetdone_reg1 : signal is "true";
  signal resetdone_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of resetdone_reg2 : signal is "NO";
  attribute async_reg of resetdone_reg2 : signal is "true";
  signal \^rst_gtreset\ : STD_LOGIC;
  signal rst_txsync_start : STD_LOGIC;
  signal \^rst_userrdy\ : STD_LOGIC;
  signal rxcdrlock_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rxcdrlock_reg1 : signal is "NO";
  attribute async_reg of rxcdrlock_reg1 : signal is "true";
  signal rxcdrlock_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rxcdrlock_reg2 : signal is "NO";
  attribute async_reg of rxcdrlock_reg2 : signal is "true";
  signal rxpmaresetdone_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rxpmaresetdone_reg1 : signal is "NO";
  attribute async_reg of rxpmaresetdone_reg1 : signal is "true";
  signal rxpmaresetdone_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rxpmaresetdone_reg2 : signal is "NO";
  attribute async_reg of rxpmaresetdone_reg2 : signal is "true";
  signal rxusrclk_rst_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxusrclk_rst_reg1 : signal is "NO";
  attribute async_reg of rxusrclk_rst_reg1 : signal is "true";
  signal rxusrclk_rst_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxusrclk_rst_reg2 : signal is "NO";
  attribute async_reg of rxusrclk_rst_reg2 : signal is "true";
  signal txsync_done_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of txsync_done_reg1 : signal is "NO";
  attribute async_reg of txsync_done_reg1 : signal is "true";
  signal txsync_done_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of txsync_done_reg2 : signal is "NO";
  attribute async_reg of txsync_done_reg2 : signal is "true";
  signal userrdy : STD_LOGIC;
  signal userrdy_i_1_n_0 : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_fsm[0]_i_2\ : label is "soft_lutpair80";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[0]\ : label is "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[10]\ : label is "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[13]\ : label is "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[14]\ : label is "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[1]\ : label is "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[2]\ : label is "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[3]\ : label is "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[4]\ : label is "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[5]\ : label is "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[8]\ : label is "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[9]\ : label is "FSM_CPLL_PD:00000000000000100,FSM_RESETDONE:00000000000010000,FSM_MMCM_LOCK:00000000000100000,FSM_DRP_X16_START:00000000001000000,FSM_CPLLRESET:00000000000000001,FSM_TXSYNC_DONE:00000001000000000,FSM_CFG_WAIT:00000000000000010,FSM_DRP_X20_DONE:00000100000000000,FSM_IDLE:00000010000000000,FSM_DRP_X20_START:00001000000000000,FSM_GTRESET:00010000000000000,FSM_DRP:00100000000000000,FSM_RXPMARESETDONE_2:01000000000000000,FSM_RXPMARESETDONE_1:10000000000000000,FSM_CPLLLOCK:00000000100000000,FSM_DRP_X16_DONE:00000000010000000,FSM_TXSYNC_START:00000000000001000";
  attribute SOFT_HLUTNM of \cfg_wait_cnt[0]_i_1\ : label is "soft_lutpair80";
  attribute SOFT_HLUTNM of \cfg_wait_cnt[1]_i_1\ : label is "soft_lutpair76";
  attribute SOFT_HLUTNM of \cfg_wait_cnt[2]_i_1\ : label is "soft_lutpair76";
  attribute SOFT_HLUTNM of \cfg_wait_cnt[4]_i_1\ : label is "soft_lutpair79";
  attribute SOFT_HLUTNM of \cfg_wait_cnt[5]_i_1\ : label is "soft_lutpair79";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \cplllock_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \cplllock_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \cplllock_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \cplllock_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \cplllock_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \cplllock_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \cplllock_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \cplllock_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \cplllock_reg2_reg[1]\ : label is "NO";
  attribute SOFT_HLUTNM of cpllreset_i_2 : label is "soft_lutpair77";
  attribute ASYNC_REG_boolean of dclk_rst_reg1_reg : label is std.standard.true;
  attribute KEEP of dclk_rst_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of dclk_rst_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of dclk_rst_reg2_reg : label is std.standard.true;
  attribute KEEP of dclk_rst_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of dclk_rst_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of \drp_done_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \drp_done_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \drp_done_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \drp_done_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \drp_done_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \drp_done_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \drp_done_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \drp_done_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \drp_done_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \drp_done_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \drp_done_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \drp_done_reg2_reg[1]\ : label is "NO";
  attribute SOFT_HLUTNM of gtreset_i_1 : label is "soft_lutpair81";
  attribute ASYNC_REG_boolean of mmcm_lock_reg1_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of mmcm_lock_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of mmcm_lock_reg2_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of mmcm_lock_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of \phystatus_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \phystatus_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \phystatus_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \phystatus_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \phystatus_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \phystatus_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \phystatus_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \phystatus_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \phystatus_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \phystatus_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \phystatus_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \phystatus_reg2_reg[1]\ : label is "NO";
  attribute SOFT_HLUTNM of \pipe_rst_fsm[0]_INST_0\ : label is "soft_lutpair77";
  attribute SOFT_HLUTNM of \pipe_rst_fsm[2]_INST_0\ : label is "soft_lutpair81";
  attribute SOFT_HLUTNM of \pipe_rst_fsm[2]_INST_0_i_1\ : label is "soft_lutpair78";
  attribute SOFT_HLUTNM of \pipe_rst_fsm[3]_INST_0\ : label is "soft_lutpair78";
  attribute ASYNC_REG_boolean of qpll_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of qpll_idle_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of qpll_idle_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of qpll_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of qpll_idle_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of qpll_idle_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of \rate_idle_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_idle_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_idle_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_idle_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_idle_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_idle_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_idle_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_idle_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_idle_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_idle_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_idle_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_idle_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \resetdone_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \resetdone_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \resetdone_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \resetdone_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \resetdone_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \resetdone_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \resetdone_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \resetdone_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \resetdone_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \resetdone_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \resetdone_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \resetdone_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxcdrlock_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxcdrlock_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxcdrlock_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxcdrlock_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxcdrlock_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxcdrlock_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxcdrlock_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxcdrlock_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxcdrlock_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxcdrlock_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxcdrlock_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxcdrlock_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxpmaresetdone_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxpmaresetdone_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxpmaresetdone_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxpmaresetdone_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxpmaresetdone_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxpmaresetdone_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxpmaresetdone_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxpmaresetdone_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxpmaresetdone_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxpmaresetdone_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxpmaresetdone_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxpmaresetdone_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of rxusrclk_rst_reg1_reg : label is std.standard.true;
  attribute KEEP of rxusrclk_rst_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxusrclk_rst_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxusrclk_rst_reg2_reg : label is std.standard.true;
  attribute KEEP of rxusrclk_rst_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxusrclk_rst_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of \txsync_done_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txsync_done_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txsync_done_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txsync_done_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txsync_done_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txsync_done_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txsync_done_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txsync_done_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txsync_done_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txsync_done_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txsync_done_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txsync_done_reg2_reg[1]\ : label is "NO";
  attribute SOFT_HLUTNM of txsync_start_reg1_i_1 : label is "soft_lutpair82";
  attribute SOFT_HLUTNM of \txsync_start_reg1_i_1__0\ : label is "soft_lutpair82";
begin
  Q(1 downto 0) <= \^q\(1 downto 0);
  dclk_rst_reg2_reg_0 <= dclk_rst_reg2;
  \out\ <= cpllreset;
  reset_n_reg2_reg <= \^reset_n_reg2_reg\;
  rst_gtreset <= \^rst_gtreset\;
  rst_userrdy <= \^rst_userrdy\;
  rxusrclk_rst_reg2_reg_0 <= rxusrclk_rst_reg2;
\FSM_onehot_fsm[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEAAAAAAAA"
    )
        port map (
      I0 => \FSM_onehot_fsm[0]_i_2_n_0\,
      I1 => cplllock_reg2(0),
      I2 => resetdone_reg2(1),
      I3 => cplllock_reg2(1),
      I4 => resetdone_reg2(0),
      I5 => \FSM_onehot_fsm_reg_n_0_[0]\,
      O => \FSM_onehot_fsm[0]_i_1_n_0\
    );
\FSM_onehot_fsm[0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I1 => \FSM_onehot_fsm[1]_i_2_n_0\,
      O => \FSM_onehot_fsm[0]_i_2_n_0\
    );
\FSM_onehot_fsm[10]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"EAAA"
    )
        port map (
      I0 => \^q\(1),
      I1 => txsync_done_reg2(1),
      I2 => txsync_done_reg2(0),
      I3 => \^q\(0),
      O => \FSM_onehot_fsm[10]_i_1_n_0\
    );
\FSM_onehot_fsm[13]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[14]\,
      I1 => rate_idle_reg2(0),
      I2 => rate_idle_reg2(1),
      O => \FSM_onehot_fsm[13]_i_1__1_n_0\
    );
\FSM_onehot_fsm[14]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF70707070707070"
    )
        port map (
      I0 => rate_idle_reg2(1),
      I1 => rate_idle_reg2(0),
      I2 => \FSM_onehot_fsm_reg_n_0_[14]\,
      I3 => cplllock_reg2(1),
      I4 => cplllock_reg2(0),
      I5 => \FSM_onehot_fsm_reg_n_0_[8]\,
      O => \FSM_onehot_fsm[14]_i_1__1_n_0\
    );
\FSM_onehot_fsm[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I1 => \FSM_onehot_fsm[1]_i_2_n_0\,
      O => \FSM_onehot_fsm[1]_i_1_n_0\
    );
\FSM_onehot_fsm[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"7FFFFFFFFFFFFFFF"
    )
        port map (
      I0 => cfg_wait_cnt_reg(2),
      I1 => cfg_wait_cnt_reg(0),
      I2 => cfg_wait_cnt_reg(1),
      I3 => cfg_wait_cnt_reg(4),
      I4 => cfg_wait_cnt_reg(3),
      I5 => cfg_wait_cnt_reg(5),
      O => \FSM_onehot_fsm[1]_i_2_n_0\
    );
\FSM_onehot_fsm[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00002000"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => phystatus_reg2(0),
      I2 => resetdone_reg2(0),
      I3 => resetdone_reg2(1),
      I4 => phystatus_reg2(1),
      O => \FSM_onehot_fsm[2]_i_1_n_0\
    );
\FSM_onehot_fsm[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEAA"
    )
        port map (
      I0 => cpllpd,
      I1 => txsync_done_reg2(1),
      I2 => txsync_done_reg2(0),
      I3 => rst_txsync_start,
      O => \FSM_onehot_fsm[3]_i_1_n_0\
    );
\FSM_onehot_fsm[4]_i_1__3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => userrdy,
      I1 => mmcm_lock_reg2,
      I2 => \FSM_onehot_fsm[4]_i_2_n_0\,
      I3 => \FSM_onehot_fsm_reg_n_0_[4]\,
      O => \FSM_onehot_fsm[4]_i_1__3_n_0\
    );
\FSM_onehot_fsm[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0040"
    )
        port map (
      I0 => phystatus_reg2(1),
      I1 => resetdone_reg2(1),
      I2 => resetdone_reg2(0),
      I3 => phystatus_reg2(0),
      O => \FSM_onehot_fsm[4]_i_2_n_0\
    );
\FSM_onehot_fsm[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"BA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[13]\,
      I1 => mmcm_lock_reg2,
      I2 => userrdy,
      O => \FSM_onehot_fsm[5]_i_1_n_0\
    );
\FSM_onehot_fsm[8]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"22AA22AB22AA22AA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[8]\,
      I1 => cplllock_reg2(0),
      I2 => resetdone_reg2(1),
      I3 => cplllock_reg2(1),
      I4 => resetdone_reg2(0),
      I5 => \FSM_onehot_fsm_reg_n_0_[0]\,
      O => \FSM_onehot_fsm[8]_i_1__1_n_0\
    );
\FSM_onehot_fsm[9]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \cfg_wait_cnt_reg[0]_0\,
      O => \^reset_n_reg2_reg\
    );
\FSM_onehot_fsm[9]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2B2A"
    )
        port map (
      I0 => \^q\(0),
      I1 => txsync_done_reg2(1),
      I2 => txsync_done_reg2(0),
      I3 => rst_txsync_start,
      O => \FSM_onehot_fsm[9]_i_2_n_0\
    );
\FSM_onehot_fsm_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '1'
    )
        port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[0]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[0]\,
      R => \^reset_n_reg2_reg\
    );
\FSM_onehot_fsm_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[10]_i_1_n_0\,
      Q => \^q\(1),
      R => \^reset_n_reg2_reg\
    );
\FSM_onehot_fsm_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[13]_i_1__1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[13]\,
      R => \^reset_n_reg2_reg\
    );
\FSM_onehot_fsm_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[14]_i_1__1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[14]\,
      R => \^reset_n_reg2_reg\
    );
\FSM_onehot_fsm_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[1]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[1]\,
      S => \^reset_n_reg2_reg\
    );
\FSM_onehot_fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[2]_i_1_n_0\,
      Q => cpllpd,
      R => \^reset_n_reg2_reg\
    );
\FSM_onehot_fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[3]_i_1_n_0\,
      Q => rst_txsync_start,
      R => \^reset_n_reg2_reg\
    );
\FSM_onehot_fsm_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[4]_i_1__3_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[4]\,
      R => \^reset_n_reg2_reg\
    );
\FSM_onehot_fsm_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[5]_i_1_n_0\,
      Q => userrdy,
      R => \^reset_n_reg2_reg\
    );
\FSM_onehot_fsm_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[8]_i_1__1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[8]\,
      R => \^reset_n_reg2_reg\
    );
\FSM_onehot_fsm_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[9]_i_2_n_0\,
      Q => \^q\(0),
      R => \^reset_n_reg2_reg\
    );
\cfg_wait_cnt[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2A"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I1 => \FSM_onehot_fsm[1]_i_2_n_0\,
      I2 => cfg_wait_cnt_reg(0),
      O => p_0_in(0)
    );
\cfg_wait_cnt[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"28AA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I1 => cfg_wait_cnt_reg(0),
      I2 => cfg_wait_cnt_reg(1),
      I3 => \FSM_onehot_fsm[1]_i_2_n_0\,
      O => p_0_in(1)
    );
\cfg_wait_cnt[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2888AAAA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I1 => cfg_wait_cnt_reg(2),
      I2 => cfg_wait_cnt_reg(1),
      I3 => cfg_wait_cnt_reg(0),
      I4 => \FSM_onehot_fsm[1]_i_2_n_0\,
      O => p_0_in(2)
    );
\cfg_wait_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"28888888AAAAAAAA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I1 => cfg_wait_cnt_reg(3),
      I2 => cfg_wait_cnt_reg(2),
      I3 => cfg_wait_cnt_reg(0),
      I4 => cfg_wait_cnt_reg(1),
      I5 => \FSM_onehot_fsm[1]_i_2_n_0\,
      O => p_0_in(3)
    );
\cfg_wait_cnt[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AE00A600"
    )
        port map (
      I0 => cfg_wait_cnt_reg(4),
      I1 => cfg_wait_cnt_reg(3),
      I2 => \cfg_wait_cnt[5]_i_2_n_0\,
      I3 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I4 => cfg_wait_cnt_reg(5),
      O => p_0_in(4)
    );
\cfg_wait_cnt[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88A88888"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I1 => cfg_wait_cnt_reg(5),
      I2 => cfg_wait_cnt_reg(3),
      I3 => \cfg_wait_cnt[5]_i_2_n_0\,
      I4 => cfg_wait_cnt_reg(4),
      O => p_0_in(5)
    );
\cfg_wait_cnt[5]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => cfg_wait_cnt_reg(1),
      I1 => cfg_wait_cnt_reg(0),
      I2 => cfg_wait_cnt_reg(2),
      O => \cfg_wait_cnt[5]_i_2_n_0\
    );
\cfg_wait_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => p_0_in(0),
      Q => cfg_wait_cnt_reg(0),
      R => \^reset_n_reg2_reg\
    );
\cfg_wait_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => p_0_in(1),
      Q => cfg_wait_cnt_reg(1),
      R => \^reset_n_reg2_reg\
    );
\cfg_wait_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => p_0_in(2),
      Q => cfg_wait_cnt_reg(2),
      R => \^reset_n_reg2_reg\
    );
\cfg_wait_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => p_0_in(3),
      Q => cfg_wait_cnt_reg(3),
      R => \^reset_n_reg2_reg\
    );
\cfg_wait_cnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => p_0_in(4),
      Q => cfg_wait_cnt_reg(4),
      R => \^reset_n_reg2_reg\
    );
\cfg_wait_cnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => p_0_in(5),
      Q => cfg_wait_cnt_reg(5),
      R => \^reset_n_reg2_reg\
    );
\cplllock_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => \cplllock_reg1_reg[1]_0\(0),
      Q => cplllock_reg1(0),
      R => \^reset_n_reg2_reg\
    );
\cplllock_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => \cplllock_reg1_reg[1]_0\(1),
      Q => cplllock_reg1(1),
      R => \^reset_n_reg2_reg\
    );
\cplllock_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => cplllock_reg1(0),
      Q => cplllock_reg2(0),
      R => \^reset_n_reg2_reg\
    );
\cplllock_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => cplllock_reg1(1),
      Q => cplllock_reg2(1),
      R => \^reset_n_reg2_reg\
    );
cpllreset_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFBAAAAAAAA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[0]\,
      I1 => \pipe_rst_fsm[2]_INST_0_i_1_n_0\,
      I2 => \^q\(0),
      I3 => \^q\(1),
      I4 => cpllreset_i_2_n_0,
      I5 => cpllreset,
      O => cpllreset_i_1_n_0
    );
cpllreset_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[13]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => cpllreset_i_2_n_0
    );
cpllreset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => cpllreset_i_1_n_0,
      Q => cpllreset,
      R => \^reset_n_reg2_reg\
    );
dclk_rst_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => \FSM_onehot_fsm_reg_n_0_[1]\,
      Q => dclk_rst,
      R => '0'
    );
dclk_rst_reg1_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => dclk_rst,
      Q => dclk_rst_reg1,
      R => '0'
    );
dclk_rst_reg2_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => dclk_rst_reg1,
      Q => dclk_rst_reg2,
      R => '0'
    );
\drp_done_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => \drp_done_reg1_reg[1]_0\(0),
      Q => drp_done_reg1(0),
      R => \^reset_n_reg2_reg\
    );
\drp_done_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => \drp_done_reg1_reg[1]_0\(1),
      Q => drp_done_reg1(1),
      R => \^reset_n_reg2_reg\
    );
\drp_done_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => drp_done_reg1(0),
      Q => drp_done_reg2(0),
      R => \^reset_n_reg2_reg\
    );
\drp_done_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => drp_done_reg1(1),
      Q => drp_done_reg2(1),
      R => \^reset_n_reg2_reg\
    );
gtreset_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"DC"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[13]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[0]\,
      I2 => \^rst_gtreset\,
      O => gtreset_i_1_n_0
    );
gtreset_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => gtreset_i_1_n_0,
      Q => \^rst_gtreset\,
      R => \^reset_n_reg2_reg\
    );
\gtx_channel.gtxe2_channel_i_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => cpllreset,
      I1 => rate_cpllreset_0,
      I2 => cpllrst,
      O => CPLLRESET0
    );
mmcm_lock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => SYNC_MMCM_LOCK,
      Q => mmcm_lock_reg1,
      R => \^reset_n_reg2_reg\
    );
mmcm_lock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => mmcm_lock_reg1,
      Q => mmcm_lock_reg2,
      R => \^reset_n_reg2_reg\
    );
\phystatus_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => \phystatus_reg1_reg[1]_0\(0),
      Q => phystatus_reg1(0),
      R => \^reset_n_reg2_reg\
    );
\phystatus_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => \phystatus_reg1_reg[1]_0\(1),
      Q => phystatus_reg1(1),
      R => \^reset_n_reg2_reg\
    );
\phystatus_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => phystatus_reg1(0),
      Q => phystatus_reg2(0),
      R => \^reset_n_reg2_reg\
    );
\phystatus_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => phystatus_reg1(1),
      Q => phystatus_reg2(1),
      R => \^reset_n_reg2_reg\
    );
\pipe_rst_fsm[0]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[13]\,
      I2 => rst_txsync_start,
      I3 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I4 => \FSM_onehot_fsm_reg_n_0_[8]\,
      O => pipe_rst_fsm(0)
    );
\pipe_rst_fsm[1]_INST_0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[0]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[13]\,
      I2 => rst_txsync_start,
      I3 => cpllpd,
      I4 => \FSM_onehot_fsm_reg_n_0_[14]\,
      O => pipe_rst_fsm(1)
    );
\pipe_rst_fsm[2]_INST_0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FD"
    )
        port map (
      I0 => \pipe_rst_fsm[2]_INST_0_i_1_n_0\,
      I1 => \FSM_onehot_fsm_reg_n_0_[8]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[13]\,
      O => pipe_rst_fsm(2)
    );
\pipe_rst_fsm[2]_INST_0_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[14]\,
      I1 => userrdy,
      I2 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I3 => rst_txsync_start,
      I4 => cpllpd,
      O => \pipe_rst_fsm[2]_INST_0_i_1_n_0\
    );
\pipe_rst_fsm[3]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => cpllpd,
      I1 => rst_txsync_start,
      I2 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I3 => userrdy,
      O => pipe_rst_fsm(3)
    );
qpll_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => QRST_IDLE,
      Q => qpll_idle_reg1,
      R => \^reset_n_reg2_reg\
    );
qpll_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => qpll_idle_reg1,
      Q => qpll_idle_reg2,
      R => \^reset_n_reg2_reg\
    );
\rate_idle_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => txsync_start_reg1_reg(0),
      Q => rate_idle_reg1(0),
      R => \^reset_n_reg2_reg\
    );
\rate_idle_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => txsync_start_reg1_reg_0(0),
      Q => rate_idle_reg1(1),
      R => \^reset_n_reg2_reg\
    );
\rate_idle_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => rate_idle_reg1(0),
      Q => rate_idle_reg2(0),
      R => \^reset_n_reg2_reg\
    );
\rate_idle_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => rate_idle_reg1(1),
      Q => rate_idle_reg2(1),
      R => \^reset_n_reg2_reg\
    );
\resetdone_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => D(0),
      Q => resetdone_reg1(0),
      R => \^reset_n_reg2_reg\
    );
\resetdone_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => D(1),
      Q => resetdone_reg1(1),
      R => \^reset_n_reg2_reg\
    );
\resetdone_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => resetdone_reg1(0),
      Q => resetdone_reg2(0),
      R => \^reset_n_reg2_reg\
    );
\resetdone_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => resetdone_reg1(1),
      Q => resetdone_reg2(1),
      R => \^reset_n_reg2_reg\
    );
\rxcdrlock_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => \rxcdrlock_reg1_reg[1]_0\(0),
      Q => rxcdrlock_reg1(0),
      R => \^reset_n_reg2_reg\
    );
\rxcdrlock_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => \rxcdrlock_reg1_reg[1]_0\(1),
      Q => rxcdrlock_reg1(1),
      R => \^reset_n_reg2_reg\
    );
\rxcdrlock_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => rxcdrlock_reg1(0),
      Q => rxcdrlock_reg2(0),
      R => \^reset_n_reg2_reg\
    );
\rxcdrlock_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => rxcdrlock_reg1(1),
      Q => rxcdrlock_reg2(1),
      R => \^reset_n_reg2_reg\
    );
\rxpmaresetdone_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => '0',
      Q => rxpmaresetdone_reg1(0),
      R => \^reset_n_reg2_reg\
    );
\rxpmaresetdone_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => '0',
      Q => rxpmaresetdone_reg1(1),
      R => \^reset_n_reg2_reg\
    );
\rxpmaresetdone_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => rxpmaresetdone_reg1(0),
      Q => rxpmaresetdone_reg2(0),
      R => \^reset_n_reg2_reg\
    );
\rxpmaresetdone_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => rxpmaresetdone_reg1(1),
      Q => rxpmaresetdone_reg2(1),
      R => \^reset_n_reg2_reg\
    );
rxusrclk_rst_reg1_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => cpllreset,
      Q => rxusrclk_rst_reg1,
      R => '0'
    );
rxusrclk_rst_reg2_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => rxusrclk_rst_reg1,
      Q => rxusrclk_rst_reg2,
      R => '0'
    );
\txsync_done_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => \txsync_done_reg1_reg[1]_0\(0),
      Q => txsync_done_reg1(0),
      R => \^reset_n_reg2_reg\
    );
\txsync_done_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => \txsync_done_reg1_reg[1]_0\(1),
      Q => txsync_done_reg1(1),
      R => \^reset_n_reg2_reg\
    );
\txsync_done_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => txsync_done_reg1(0),
      Q => txsync_done_reg2(0),
      R => \^reset_n_reg2_reg\
    );
\txsync_done_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => txsync_done_reg1(1),
      Q => txsync_done_reg2(1),
      R => \^reset_n_reg2_reg\
    );
txsync_start_reg1_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rst_txsync_start,
      I1 => txsync_start_reg1_reg(1),
      O => SYNC_TXSYNC_START
    );
\txsync_start_reg1_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => rst_txsync_start,
      I1 => txsync_start_reg1_reg_0(1),
      O => \FSM_onehot_fsm_reg[3]_0\
    );
userrdy_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => mmcm_lock_reg2,
      I1 => userrdy,
      I2 => \^rst_userrdy\,
      O => userrdy_i_1_n_0
    );
userrdy_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \rxcdrlock_reg2_reg[1]_0\,
      CE => '1',
      D => userrdy_i_1_n_0,
      Q => \^rst_userrdy\,
      R => \^reset_n_reg2_reg\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_sync is
  port (
    p_1_in : out STD_LOGIC;
    \out\ : out STD_LOGIC;
    p_1_in0_in : out STD_LOGIC;
    txphinitdone_reg3_reg_0 : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
    pipe_sync_fsm_rx : out STD_LOGIC_VECTOR ( 0 to 0 );
    sync_txdlyen_0 : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \FSM_onehot_txsync_fsm.fsm_tx_reg[4]_0\ : in STD_LOGIC;
    \txsync_fsm.txsync_done_reg_0\ : in STD_LOGIC;
    \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0\ : in STD_LOGIC;
    \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\ : in STD_LOGIC;
    \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1\ : in STD_LOGIC;
    rxphaligndone_s_reg2_reg_0 : in STD_LOGIC;
    rxphaligndone_s_reg2_reg_1 : in STD_LOGIC;
    SYNC_TXPHALIGNDONE : in STD_LOGIC;
    SYNC_TXSYNC_START : in STD_LOGIC;
    SYNC_MMCM_LOCK : in STD_LOGIC;
    SYNC_TXDLYSRESETDONE : in STD_LOGIC;
    SYNC_TXPHINITDONE : in STD_LOGIC;
    SYNC_GEN3 : in STD_LOGIC;
    SYNC_RATE_IDLE : in STD_LOGIC;
    PIPE_RXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    SYNC_RXCDRLOCK : in STD_LOGIC;
    SYNC_RXDLYSRESETDONE : in STD_LOGIC;
    pipe_rxphaligndone : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_sync : entity is "spec7_pcie_7x_0_pipe_sync";
end spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_sync;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_sync is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1_n_0\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal gen3_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of gen3_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of gen3_reg1 : signal is "true";
  signal gen3_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of gen3_reg2 : signal is "NO";
  attribute async_reg of gen3_reg2 : signal is "true";
  signal mmcm_lock_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of mmcm_lock_reg1 : signal is "NO";
  attribute async_reg of mmcm_lock_reg1 : signal is "true";
  signal mmcm_lock_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of mmcm_lock_reg2 : signal is "NO";
  attribute async_reg of mmcm_lock_reg2 : signal is "true";
  signal rate_idle_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_idle_reg1 : signal is "NO";
  attribute async_reg of rate_idle_reg1 : signal is "true";
  signal rate_idle_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_idle_reg2 : signal is "NO";
  attribute async_reg of rate_idle_reg2 : signal is "true";
  signal rxcdrlock_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxcdrlock_reg1 : signal is "NO";
  attribute async_reg of rxcdrlock_reg1 : signal is "true";
  signal rxcdrlock_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxcdrlock_reg2 : signal is "NO";
  attribute async_reg of rxcdrlock_reg2 : signal is "true";
  signal rxdlysresetdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxdlysresetdone_reg1 : signal is "NO";
  attribute async_reg of rxdlysresetdone_reg1 : signal is "true";
  signal rxdlysresetdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxdlysresetdone_reg2 : signal is "NO";
  attribute async_reg of rxdlysresetdone_reg2 : signal is "true";
  signal rxelecidle_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxelecidle_reg1 : signal is "NO";
  attribute async_reg of rxelecidle_reg1 : signal is "true";
  signal rxelecidle_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxelecidle_reg2 : signal is "NO";
  attribute async_reg of rxelecidle_reg2 : signal is "true";
  signal rxphaligndone_m_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxphaligndone_m_reg1 : signal is "NO";
  attribute async_reg of rxphaligndone_m_reg1 : signal is "true";
  signal rxphaligndone_m_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxphaligndone_m_reg2 : signal is "NO";
  attribute async_reg of rxphaligndone_m_reg2 : signal is "true";
  signal rxphaligndone_s_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxphaligndone_s_reg1 : signal is "NO";
  attribute async_reg of rxphaligndone_s_reg1 : signal is "true";
  signal rxphaligndone_s_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxphaligndone_s_reg2 : signal is "NO";
  attribute async_reg of rxphaligndone_s_reg2 : signal is "true";
  signal rxsync_donem_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxsync_donem_reg1 : signal is "NO";
  attribute async_reg of rxsync_donem_reg1 : signal is "true";
  signal rxsync_donem_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxsync_donem_reg2 : signal is "NO";
  attribute async_reg of rxsync_donem_reg2 : signal is "true";
  signal rxsync_start_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxsync_start_reg1 : signal is "NO";
  attribute async_reg of rxsync_start_reg1 : signal is "true";
  signal rxsync_start_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxsync_start_reg2 : signal is "NO";
  attribute async_reg of rxsync_start_reg2 : signal is "true";
  signal rxsyncdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxsyncdone_reg1 : signal is "NO";
  attribute async_reg of rxsyncdone_reg1 : signal is "true";
  signal rxsyncdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxsyncdone_reg2 : signal is "NO";
  attribute async_reg of rxsyncdone_reg2 : signal is "true";
  signal \^sync_txdlyen_0\ : STD_LOGIC;
  signal txdlysresetdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txdlysresetdone_reg1 : signal is "NO";
  attribute async_reg of txdlysresetdone_reg1 : signal is "true";
  signal txdlysresetdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txdlysresetdone_reg2 : signal is "NO";
  attribute async_reg of txdlysresetdone_reg2 : signal is "true";
  signal txdlysresetdone_reg3 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txdlysresetdone_reg3 : signal is "NO";
  attribute async_reg of txdlysresetdone_reg3 : signal is "true";
  signal txphaligndone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txphaligndone_reg1 : signal is "NO";
  attribute async_reg of txphaligndone_reg1 : signal is "true";
  signal txphaligndone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txphaligndone_reg2 : signal is "NO";
  attribute async_reg of txphaligndone_reg2 : signal is "true";
  signal txphaligndone_reg3 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txphaligndone_reg3 : signal is "NO";
  attribute async_reg of txphaligndone_reg3 : signal is "true";
  signal txphinitdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txphinitdone_reg1 : signal is "NO";
  attribute async_reg of txphinitdone_reg1 : signal is "true";
  signal txphinitdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txphinitdone_reg2 : signal is "NO";
  attribute async_reg of txphinitdone_reg2 : signal is "true";
  signal txphinitdone_reg3 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txphinitdone_reg3 : signal is "NO";
  attribute async_reg of txphinitdone_reg3 : signal is "true";
  signal \txsync_fsm.txdlyen_i_1_n_0\ : STD_LOGIC;
  signal \txsync_fsm.txsync_done_i_1_n_0\ : STD_LOGIC;
  signal txsync_start_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsync_start_reg1 : signal is "NO";
  attribute async_reg of txsync_start_reg1 : signal is "true";
  signal txsync_start_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsync_start_reg2 : signal is "NO";
  attribute async_reg of txsync_start_reg2 : signal is "true";
  signal txsync_start_reg3 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsync_start_reg3 : signal is "NO";
  attribute async_reg of txsync_start_reg3 : signal is "true";
  signal txsyncdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsyncdone_reg1 : signal is "NO";
  attribute async_reg of txsyncdone_reg1 : signal is "true";
  signal txsyncdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsyncdone_reg2 : signal is "NO";
  attribute async_reg of txsyncdone_reg2 : signal is "true";
  signal txsyncdone_reg3 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsyncdone_reg3 : signal is "NO";
  attribute async_reg of txsyncdone_reg3 : signal is "true";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[1]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[2]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[3]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[4]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[5]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[6]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of gen3_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of gen3_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of gen3_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of gen3_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of gen3_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of mmcm_lock_reg1_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of mmcm_lock_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of mmcm_lock_reg2_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of mmcm_lock_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_idle_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_idle_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxcdrlock_reg1_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxcdrlock_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxcdrlock_reg2_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxcdrlock_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxdlysresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxdlysresetdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxdlysresetdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxdlysresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxdlysresetdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxdlysresetdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxelecidle_reg1_reg : label is std.standard.true;
  attribute KEEP of rxelecidle_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxelecidle_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxelecidle_reg2_reg : label is std.standard.true;
  attribute KEEP of rxelecidle_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxelecidle_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxphaligndone_m_reg1_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_m_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxphaligndone_m_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxphaligndone_m_reg2_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_m_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxphaligndone_m_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxphaligndone_s_reg1_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_s_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxphaligndone_s_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxphaligndone_s_reg2_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_s_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxphaligndone_s_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxsync_donem_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_donem_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxsync_donem_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxsync_donem_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_donem_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxsync_donem_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxsync_start_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_start_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxsync_start_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxsync_start_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_start_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxsync_start_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxsyncdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsyncdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxsyncdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxsyncdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsyncdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxsyncdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txdlysresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txdlysresetdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txdlysresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txdlysresetdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txdlysresetdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg3_reg : label is "yes";
  attribute SHIFT_EXTRACT of txdlysresetdone_reg3_reg : label is "NO";
  attribute ASYNC_REG_boolean of txphaligndone_reg1_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txphaligndone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txphaligndone_reg2_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txphaligndone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txphaligndone_reg3_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg3_reg : label is "yes";
  attribute SHIFT_EXTRACT of txphaligndone_reg3_reg : label is "NO";
  attribute ASYNC_REG_boolean of txphinitdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txphinitdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txphinitdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txphinitdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txphinitdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg3_reg : label is "yes";
  attribute SHIFT_EXTRACT of txphinitdone_reg3_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsync_start_reg1_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsync_start_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsync_start_reg2_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsync_start_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsync_start_reg3_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg3_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsync_start_reg3_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsyncdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsyncdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsyncdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsyncdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsyncdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg3_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsyncdone_reg3_reg : label is "NO";
begin
  D(0) <= \^d\(0);
  Q(5 downto 0) <= \^q\(5 downto 0);
  \out\ <= txphaligndone_reg3;
  p_1_in <= txphaligndone_reg2;
  p_1_in0_in <= txphinitdone_reg2;
  sync_txdlyen_0 <= \^sync_txdlyen_0\;
  txphinitdone_reg3_reg_0 <= txphinitdone_reg3;
\FSM_onehot_txsync_fsm.fsm_tx[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"1D1DFF1D"
    )
        port map (
      I0 => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2_n_0\,
      I1 => \^q\(0),
      I2 => txsync_start_reg2,
      I3 => \^q\(5),
      I4 => \txsync_fsm.txsync_done_reg_0\,
      O => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1_n_0\
    );
\FSM_onehot_txsync_fsm.fsm_tx[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \^q\(3),
      I1 => \^q\(5),
      I2 => \^q\(1),
      I3 => \^q\(2),
      I4 => \^q\(4),
      O => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2_n_0\
    );
\FSM_onehot_txsync_fsm.fsm_tx[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F444"
    )
        port map (
      I0 => mmcm_lock_reg2,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => txsync_start_reg2,
      O => \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1_n_0\
    );
\FSM_onehot_txsync_fsm.fsm_tx[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFD0D0D0"
    )
        port map (
      I0 => txdlysresetdone_reg2,
      I1 => txdlysresetdone_reg3,
      I2 => \^q\(2),
      I3 => mmcm_lock_reg2,
      I4 => \^q\(1),
      O => \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1_n_0\
    );
\FSM_onehot_txsync_fsm.fsm_tx[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88F88888"
    )
        port map (
      I0 => \FSM_onehot_txsync_fsm.fsm_tx_reg[4]_0\,
      I1 => \^q\(3),
      I2 => txdlysresetdone_reg2,
      I3 => txdlysresetdone_reg3,
      I4 => \^q\(2),
      O => \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1_n_0\
    );
\FSM_onehot_txsync_fsm.fsm_tx[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8FFF8F888888888"
    )
        port map (
      I0 => \txsync_fsm.txsync_done_reg_0\,
      I1 => \^q\(4),
      I2 => \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0\,
      I3 => txphinitdone_reg3,
      I4 => txphinitdone_reg2,
      I5 => \^q\(3),
      O => \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1_n_0\
    );
\FSM_onehot_txsync_fsm.fsm_tx[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAFFEAEA2A002A2A"
    )
        port map (
      I0 => \^q\(5),
      I1 => \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\,
      I2 => \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1\,
      I3 => txphaligndone_reg3,
      I4 => txphaligndone_reg2,
      I5 => \^q\(4),
      O => \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1_n_0\
    );
\FSM_onehot_txsync_fsm.fsm_tx_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1_n_0\,
      Q => \^q\(0),
      S => rxphaligndone_s_reg2_reg_0
    );
\FSM_onehot_txsync_fsm.fsm_tx_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1_n_0\,
      Q => \^q\(1),
      R => rxphaligndone_s_reg2_reg_0
    );
\FSM_onehot_txsync_fsm.fsm_tx_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1_n_0\,
      Q => \^q\(2),
      R => rxphaligndone_s_reg2_reg_0
    );
\FSM_onehot_txsync_fsm.fsm_tx_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1_n_0\,
      Q => \^q\(3),
      R => rxphaligndone_s_reg2_reg_0
    );
\FSM_onehot_txsync_fsm.fsm_tx_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1_n_0\,
      Q => \^q\(4),
      R => rxphaligndone_s_reg2_reg_0
    );
\FSM_onehot_txsync_fsm.fsm_tx_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1_n_0\,
      Q => \^q\(5),
      R => rxphaligndone_s_reg2_reg_0
    );
gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => SYNC_GEN3,
      Q => gen3_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => gen3_reg1,
      Q => gen3_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
mmcm_lock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => SYNC_MMCM_LOCK,
      Q => mmcm_lock_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
mmcm_lock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => mmcm_lock_reg1,
      Q => mmcm_lock_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
rate_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => SYNC_RATE_IDLE,
      Q => rate_idle_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
rate_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => rate_idle_reg1,
      Q => rate_idle_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
rxcdrlock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => SYNC_RXCDRLOCK,
      Q => rxcdrlock_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
rxcdrlock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => rxcdrlock_reg1,
      Q => rxcdrlock_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
rxdlysresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => SYNC_RXDLYSRESETDONE,
      Q => rxdlysresetdone_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
rxdlysresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => rxdlysresetdone_reg1,
      Q => rxdlysresetdone_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
rxelecidle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => PIPE_RXELECIDLE(0),
      Q => rxelecidle_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
rxelecidle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => rxelecidle_reg1,
      Q => rxelecidle_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
rxphaligndone_m_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => pipe_rxphaligndone(0),
      Q => rxphaligndone_m_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
rxphaligndone_m_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => rxphaligndone_m_reg1,
      Q => rxphaligndone_m_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
rxphaligndone_s_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => pipe_rxphaligndone(1),
      Q => rxphaligndone_s_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
rxphaligndone_s_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => rxphaligndone_s_reg1,
      Q => rxphaligndone_s_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
rxsync_donem_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => '0',
      Q => rxsync_donem_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
rxsync_donem_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => rxsync_donem_reg1,
      Q => rxsync_donem_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
\rxsync_fsm_disable.fsm_rx_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => '1',
      Q => pipe_sync_fsm_rx(0),
      R => '0'
    );
rxsync_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => '0',
      Q => rxsync_start_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
rxsync_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => rxsync_start_reg1,
      Q => rxsync_start_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
rxsyncdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => '0',
      Q => rxsyncdone_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
rxsyncdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => rxsyncdone_reg1,
      Q => rxsyncdone_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
txdlysresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => SYNC_TXDLYSRESETDONE,
      Q => txdlysresetdone_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
txdlysresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => txdlysresetdone_reg1,
      Q => txdlysresetdone_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
txdlysresetdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => txdlysresetdone_reg2,
      Q => txdlysresetdone_reg3,
      R => rxphaligndone_s_reg2_reg_0
    );
txphaligndone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => SYNC_TXPHALIGNDONE,
      Q => txphaligndone_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
txphaligndone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => txphaligndone_reg1,
      Q => txphaligndone_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
txphaligndone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => txphaligndone_reg2,
      Q => txphaligndone_reg3,
      R => rxphaligndone_s_reg2_reg_0
    );
txphinitdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => SYNC_TXPHINITDONE,
      Q => txphinitdone_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
txphinitdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => txphinitdone_reg1,
      Q => txphinitdone_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
txphinitdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => txphinitdone_reg2,
      Q => txphinitdone_reg3,
      R => rxphaligndone_s_reg2_reg_0
    );
\txsync_fsm.txdlyen_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ABAAA8AA"
    )
        port map (
      I0 => \^q\(5),
      I1 => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2_n_0\,
      I2 => txsync_start_reg2,
      I3 => \^q\(0),
      I4 => \^sync_txdlyen_0\,
      O => \txsync_fsm.txdlyen_i_1_n_0\
    );
\txsync_fsm.txdlyen_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => \txsync_fsm.txdlyen_i_1_n_0\,
      Q => \^sync_txdlyen_0\,
      R => rxphaligndone_s_reg2_reg_0
    );
\txsync_fsm.txsync_done_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"222F222222202222"
    )
        port map (
      I0 => \^q\(5),
      I1 => \txsync_fsm.txsync_done_reg_0\,
      I2 => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2_n_0\,
      I3 => txsync_start_reg2,
      I4 => \^q\(0),
      I5 => \^d\(0),
      O => \txsync_fsm.txsync_done_i_1_n_0\
    );
\txsync_fsm.txsync_done_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => \txsync_fsm.txsync_done_i_1_n_0\,
      Q => \^d\(0),
      R => rxphaligndone_s_reg2_reg_0
    );
txsync_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => SYNC_TXSYNC_START,
      Q => txsync_start_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
txsync_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => txsync_start_reg1,
      Q => txsync_start_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
txsync_start_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => txsync_start_reg2,
      Q => txsync_start_reg3,
      R => rxphaligndone_s_reg2_reg_0
    );
txsyncdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => '0',
      Q => txsyncdone_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
txsyncdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => txsyncdone_reg1,
      Q => txsyncdone_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
txsyncdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => txsyncdone_reg2,
      Q => txsyncdone_reg3,
      R => rxphaligndone_s_reg2_reg_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_sync_20 is
  port (
    p_1_in0_in : out STD_LOGIC;
    \out\ : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
    pipe_sync_fsm_rx : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \FSM_onehot_txsync_fsm.fsm_tx_reg[4]_0\ : in STD_LOGIC;
    \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0\ : in STD_LOGIC;
    \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\ : in STD_LOGIC;
    \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1\ : in STD_LOGIC;
    rxphaligndone_s_reg2_reg_0 : in STD_LOGIC;
    rxphaligndone_s_reg2_reg_1 : in STD_LOGIC;
    SYNC_TXPHALIGNDONE : in STD_LOGIC;
    SYNC_TXSYNC_START : in STD_LOGIC;
    SYNC_MMCM_LOCK : in STD_LOGIC;
    SYNC_TXDLYSRESETDONE : in STD_LOGIC;
    SYNC_TXPHINITDONE : in STD_LOGIC;
    SYNC_GEN3 : in STD_LOGIC;
    SYNC_RATE_IDLE : in STD_LOGIC;
    PIPE_RXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    SYNC_RXCDRLOCK : in STD_LOGIC;
    SYNC_RXDLYSRESETDONE : in STD_LOGIC;
    pipe_rxphaligndone : in STD_LOGIC_VECTOR ( 1 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_sync_20 : entity is "spec7_pcie_7x_0_pipe_sync";
end spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_sync_20;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_sync_20 is
  signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal gen3_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of gen3_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of gen3_reg1 : signal is "true";
  signal gen3_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of gen3_reg2 : signal is "NO";
  attribute async_reg of gen3_reg2 : signal is "true";
  signal mmcm_lock_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of mmcm_lock_reg1 : signal is "NO";
  attribute async_reg of mmcm_lock_reg1 : signal is "true";
  signal mmcm_lock_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of mmcm_lock_reg2 : signal is "NO";
  attribute async_reg of mmcm_lock_reg2 : signal is "true";
  signal rate_idle_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_idle_reg1 : signal is "NO";
  attribute async_reg of rate_idle_reg1 : signal is "true";
  signal rate_idle_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_idle_reg2 : signal is "NO";
  attribute async_reg of rate_idle_reg2 : signal is "true";
  signal rxcdrlock_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxcdrlock_reg1 : signal is "NO";
  attribute async_reg of rxcdrlock_reg1 : signal is "true";
  signal rxcdrlock_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxcdrlock_reg2 : signal is "NO";
  attribute async_reg of rxcdrlock_reg2 : signal is "true";
  signal rxdlysresetdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxdlysresetdone_reg1 : signal is "NO";
  attribute async_reg of rxdlysresetdone_reg1 : signal is "true";
  signal rxdlysresetdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxdlysresetdone_reg2 : signal is "NO";
  attribute async_reg of rxdlysresetdone_reg2 : signal is "true";
  signal rxelecidle_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxelecidle_reg1 : signal is "NO";
  attribute async_reg of rxelecidle_reg1 : signal is "true";
  signal rxelecidle_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxelecidle_reg2 : signal is "NO";
  attribute async_reg of rxelecidle_reg2 : signal is "true";
  signal rxphaligndone_m_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxphaligndone_m_reg1 : signal is "NO";
  attribute async_reg of rxphaligndone_m_reg1 : signal is "true";
  signal rxphaligndone_m_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxphaligndone_m_reg2 : signal is "NO";
  attribute async_reg of rxphaligndone_m_reg2 : signal is "true";
  signal rxphaligndone_s_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxphaligndone_s_reg1 : signal is "NO";
  attribute async_reg of rxphaligndone_s_reg1 : signal is "true";
  signal rxphaligndone_s_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxphaligndone_s_reg2 : signal is "NO";
  attribute async_reg of rxphaligndone_s_reg2 : signal is "true";
  signal rxsync_donem_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxsync_donem_reg1 : signal is "NO";
  attribute async_reg of rxsync_donem_reg1 : signal is "true";
  signal rxsync_donem_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxsync_donem_reg2 : signal is "NO";
  attribute async_reg of rxsync_donem_reg2 : signal is "true";
  signal rxsync_start_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxsync_start_reg1 : signal is "NO";
  attribute async_reg of rxsync_start_reg1 : signal is "true";
  signal rxsync_start_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxsync_start_reg2 : signal is "NO";
  attribute async_reg of rxsync_start_reg2 : signal is "true";
  signal rxsyncdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxsyncdone_reg1 : signal is "NO";
  attribute async_reg of rxsyncdone_reg1 : signal is "true";
  signal rxsyncdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxsyncdone_reg2 : signal is "NO";
  attribute async_reg of rxsyncdone_reg2 : signal is "true";
  signal txdlysresetdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txdlysresetdone_reg1 : signal is "NO";
  attribute async_reg of txdlysresetdone_reg1 : signal is "true";
  signal txdlysresetdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txdlysresetdone_reg2 : signal is "NO";
  attribute async_reg of txdlysresetdone_reg2 : signal is "true";
  signal txdlysresetdone_reg3 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txdlysresetdone_reg3 : signal is "NO";
  attribute async_reg of txdlysresetdone_reg3 : signal is "true";
  signal txphaligndone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txphaligndone_reg1 : signal is "NO";
  attribute async_reg of txphaligndone_reg1 : signal is "true";
  signal txphaligndone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txphaligndone_reg2 : signal is "NO";
  attribute async_reg of txphaligndone_reg2 : signal is "true";
  signal txphaligndone_reg3 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txphaligndone_reg3 : signal is "NO";
  attribute async_reg of txphaligndone_reg3 : signal is "true";
  signal txphinitdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txphinitdone_reg1 : signal is "NO";
  attribute async_reg of txphinitdone_reg1 : signal is "true";
  signal txphinitdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txphinitdone_reg2 : signal is "NO";
  attribute async_reg of txphinitdone_reg2 : signal is "true";
  signal txphinitdone_reg3 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txphinitdone_reg3 : signal is "NO";
  attribute async_reg of txphinitdone_reg3 : signal is "true";
  signal \txsync_fsm.txsync_done_i_1__0_n_0\ : STD_LOGIC;
  signal txsync_start_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsync_start_reg1 : signal is "NO";
  attribute async_reg of txsync_start_reg1 : signal is "true";
  signal txsync_start_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsync_start_reg2 : signal is "NO";
  attribute async_reg of txsync_start_reg2 : signal is "true";
  signal txsync_start_reg3 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsync_start_reg3 : signal is "NO";
  attribute async_reg of txsync_start_reg3 : signal is "true";
  signal txsyncdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsyncdone_reg1 : signal is "NO";
  attribute async_reg of txsyncdone_reg1 : signal is "true";
  signal txsyncdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsyncdone_reg2 : signal is "NO";
  attribute async_reg of txsyncdone_reg2 : signal is "true";
  signal txsyncdone_reg3 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txsyncdone_reg3 : signal is "NO";
  attribute async_reg of txsyncdone_reg3 : signal is "true";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[1]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[2]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[3]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[4]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[5]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_txsync_fsm.fsm_tx_reg[6]\ : label is "FSM_MMCM_LOCK:0000100,FSM_TXSYNC_START:0001000,FSM_TXPHINITDONE:0010000,FSM_TXSYNC_DONE1:0100000,FSM_TXSYNC_DONE2:1000000,FSM_TXSYNC_IDLE:0000010,iSTATE:0000001";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of gen3_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of gen3_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of gen3_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of gen3_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of gen3_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of mmcm_lock_reg1_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of mmcm_lock_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of mmcm_lock_reg2_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of mmcm_lock_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_idle_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_idle_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxcdrlock_reg1_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxcdrlock_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxcdrlock_reg2_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxcdrlock_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxdlysresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxdlysresetdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxdlysresetdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxdlysresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxdlysresetdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxdlysresetdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxelecidle_reg1_reg : label is std.standard.true;
  attribute KEEP of rxelecidle_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxelecidle_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxelecidle_reg2_reg : label is std.standard.true;
  attribute KEEP of rxelecidle_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxelecidle_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxphaligndone_m_reg1_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_m_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxphaligndone_m_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxphaligndone_m_reg2_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_m_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxphaligndone_m_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxphaligndone_s_reg1_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_s_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxphaligndone_s_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxphaligndone_s_reg2_reg : label is std.standard.true;
  attribute KEEP of rxphaligndone_s_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxphaligndone_s_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxsync_donem_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_donem_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxsync_donem_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxsync_donem_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_donem_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxsync_donem_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxsync_start_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsync_start_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxsync_start_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxsync_start_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsync_start_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxsync_start_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxsyncdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxsyncdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxsyncdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxsyncdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxsyncdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxsyncdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txdlysresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txdlysresetdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txdlysresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txdlysresetdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txdlysresetdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txdlysresetdone_reg3_reg : label is "yes";
  attribute SHIFT_EXTRACT of txdlysresetdone_reg3_reg : label is "NO";
  attribute ASYNC_REG_boolean of txphaligndone_reg1_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txphaligndone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txphaligndone_reg2_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txphaligndone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txphaligndone_reg3_reg : label is std.standard.true;
  attribute KEEP of txphaligndone_reg3_reg : label is "yes";
  attribute SHIFT_EXTRACT of txphaligndone_reg3_reg : label is "NO";
  attribute ASYNC_REG_boolean of txphinitdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txphinitdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txphinitdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txphinitdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txphinitdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txphinitdone_reg3_reg : label is "yes";
  attribute SHIFT_EXTRACT of txphinitdone_reg3_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsync_start_reg1_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsync_start_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsync_start_reg2_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsync_start_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsync_start_reg3_reg : label is std.standard.true;
  attribute KEEP of txsync_start_reg3_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsync_start_reg3_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsyncdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsyncdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsyncdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsyncdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txsyncdone_reg3_reg : label is std.standard.true;
  attribute KEEP of txsyncdone_reg3_reg : label is "yes";
  attribute SHIFT_EXTRACT of txsyncdone_reg3_reg : label is "NO";
begin
  D(0) <= \^d\(0);
  Q(5 downto 0) <= \^q\(5 downto 0);
  \out\ <= txphinitdone_reg3;
  p_1_in0_in <= txphinitdone_reg2;
\FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF1D"
    )
        port map (
      I0 => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__0_n_0\,
      I1 => \^q\(0),
      I2 => txsync_start_reg2,
      I3 => \^q\(5),
      O => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__0_n_0\
    );
\FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \^q\(4),
      I1 => \^q\(3),
      I2 => \^q\(2),
      I3 => \^q\(5),
      I4 => \^q\(1),
      O => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__0_n_0\
    );
\FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F444"
    )
        port map (
      I0 => mmcm_lock_reg2,
      I1 => \^q\(1),
      I2 => \^q\(0),
      I3 => txsync_start_reg2,
      O => \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__0_n_0\
    );
\FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFD0D0D0"
    )
        port map (
      I0 => txdlysresetdone_reg2,
      I1 => txdlysresetdone_reg3,
      I2 => \^q\(2),
      I3 => mmcm_lock_reg2,
      I4 => \^q\(1),
      O => \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__0_n_0\
    );
\FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88F88888"
    )
        port map (
      I0 => \FSM_onehot_txsync_fsm.fsm_tx_reg[4]_0\,
      I1 => \^q\(3),
      I2 => txdlysresetdone_reg2,
      I3 => txdlysresetdone_reg3,
      I4 => \^q\(2),
      O => \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__0_n_0\
    );
\FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"4500FFFF45004500"
    )
        port map (
      I0 => \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0\,
      I1 => txphaligndone_reg3,
      I2 => txphaligndone_reg2,
      I3 => \^q\(4),
      I4 => \FSM_onehot_txsync_fsm.fsm_tx_reg[4]_0\,
      I5 => \^q\(3),
      O => \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__0_n_0\
    );
\FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AA080808"
    )
        port map (
      I0 => \^q\(4),
      I1 => txphaligndone_reg2,
      I2 => txphaligndone_reg3,
      I3 => \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\,
      I4 => \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1\,
      O => \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__0_n_0\
    );
\FSM_onehot_txsync_fsm.fsm_tx_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_1__0_n_0\,
      Q => \^q\(0),
      S => rxphaligndone_s_reg2_reg_0
    );
\FSM_onehot_txsync_fsm.fsm_tx_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => \FSM_onehot_txsync_fsm.fsm_tx[2]_i_1__0_n_0\,
      Q => \^q\(1),
      R => rxphaligndone_s_reg2_reg_0
    );
\FSM_onehot_txsync_fsm.fsm_tx_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => \FSM_onehot_txsync_fsm.fsm_tx[3]_i_1__0_n_0\,
      Q => \^q\(2),
      R => rxphaligndone_s_reg2_reg_0
    );
\FSM_onehot_txsync_fsm.fsm_tx_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => \FSM_onehot_txsync_fsm.fsm_tx[4]_i_1__0_n_0\,
      Q => \^q\(3),
      R => rxphaligndone_s_reg2_reg_0
    );
\FSM_onehot_txsync_fsm.fsm_tx_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => \FSM_onehot_txsync_fsm.fsm_tx[5]_i_1__0_n_0\,
      Q => \^q\(4),
      R => rxphaligndone_s_reg2_reg_0
    );
\FSM_onehot_txsync_fsm.fsm_tx_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => \FSM_onehot_txsync_fsm.fsm_tx[6]_i_1__0_n_0\,
      Q => \^q\(5),
      R => rxphaligndone_s_reg2_reg_0
    );
gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => SYNC_GEN3,
      Q => gen3_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => gen3_reg1,
      Q => gen3_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
mmcm_lock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => SYNC_MMCM_LOCK,
      Q => mmcm_lock_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
mmcm_lock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => mmcm_lock_reg1,
      Q => mmcm_lock_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
rate_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => SYNC_RATE_IDLE,
      Q => rate_idle_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
rate_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => rate_idle_reg1,
      Q => rate_idle_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
rxcdrlock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => SYNC_RXCDRLOCK,
      Q => rxcdrlock_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
rxcdrlock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => rxcdrlock_reg1,
      Q => rxcdrlock_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
rxdlysresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => SYNC_RXDLYSRESETDONE,
      Q => rxdlysresetdone_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
rxdlysresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => rxdlysresetdone_reg1,
      Q => rxdlysresetdone_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
rxelecidle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => PIPE_RXELECIDLE(0),
      Q => rxelecidle_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
rxelecidle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => rxelecidle_reg1,
      Q => rxelecidle_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
rxphaligndone_m_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => pipe_rxphaligndone(0),
      Q => rxphaligndone_m_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
rxphaligndone_m_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => rxphaligndone_m_reg1,
      Q => rxphaligndone_m_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
rxphaligndone_s_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => pipe_rxphaligndone(1),
      Q => rxphaligndone_s_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
rxphaligndone_s_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => rxphaligndone_s_reg1,
      Q => rxphaligndone_s_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
rxsync_donem_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => '0',
      Q => rxsync_donem_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
rxsync_donem_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => rxsync_donem_reg1,
      Q => rxsync_donem_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
\rxsync_fsm_disable.fsm_rx_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => '1',
      Q => pipe_sync_fsm_rx(0),
      R => '0'
    );
rxsync_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => '0',
      Q => rxsync_start_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
rxsync_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => rxsync_start_reg1,
      Q => rxsync_start_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
rxsyncdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => '0',
      Q => rxsyncdone_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
rxsyncdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => rxsyncdone_reg1,
      Q => rxsyncdone_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
txdlysresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => SYNC_TXDLYSRESETDONE,
      Q => txdlysresetdone_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
txdlysresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => txdlysresetdone_reg1,
      Q => txdlysresetdone_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
txdlysresetdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => txdlysresetdone_reg2,
      Q => txdlysresetdone_reg3,
      R => rxphaligndone_s_reg2_reg_0
    );
txphaligndone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => SYNC_TXPHALIGNDONE,
      Q => txphaligndone_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
txphaligndone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => txphaligndone_reg1,
      Q => txphaligndone_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
txphaligndone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => txphaligndone_reg2,
      Q => txphaligndone_reg3,
      R => rxphaligndone_s_reg2_reg_0
    );
txphinitdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => SYNC_TXPHINITDONE,
      Q => txphinitdone_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
txphinitdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => txphinitdone_reg1,
      Q => txphinitdone_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
txphinitdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => txphinitdone_reg2,
      Q => txphinitdone_reg3,
      R => rxphaligndone_s_reg2_reg_0
    );
\txsync_fsm.txsync_done_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ABAAA8AA"
    )
        port map (
      I0 => \^q\(5),
      I1 => \FSM_onehot_txsync_fsm.fsm_tx[1]_i_2__0_n_0\,
      I2 => txsync_start_reg2,
      I3 => \^q\(0),
      I4 => \^d\(0),
      O => \txsync_fsm.txsync_done_i_1__0_n_0\
    );
\txsync_fsm.txsync_done_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => \txsync_fsm.txsync_done_i_1__0_n_0\,
      Q => \^d\(0),
      R => rxphaligndone_s_reg2_reg_0
    );
txsync_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => SYNC_TXSYNC_START,
      Q => txsync_start_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
txsync_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => txsync_start_reg1,
      Q => txsync_start_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
txsync_start_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => txsync_start_reg2,
      Q => txsync_start_reg3,
      R => rxphaligndone_s_reg2_reg_0
    );
txsyncdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => '0',
      Q => txsyncdone_reg1,
      R => rxphaligndone_s_reg2_reg_0
    );
txsyncdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => txsyncdone_reg1,
      Q => txsyncdone_reg2,
      R => rxphaligndone_s_reg2_reg_0
    );
txsyncdone_reg3_reg: unisim.vcomponents.FDRE
     port map (
      C => rxphaligndone_s_reg2_reg_1,
      CE => '1',
      D => txsyncdone_reg2,
      Q => txsyncdone_reg3,
      R => rxphaligndone_s_reg2_reg_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_user is
  port (
    \out\ : out STD_LOGIC;
    txcompliance_reg2_reg_0 : out STD_LOGIC;
    rst_idle_reg2_reg_0 : out STD_LOGIC;
    CLKRSVD : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxvalid_q : out STD_LOGIC;
    \rxcdrlock_cnt_reg[2]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    converge_gen3_reg_0 : out STD_LOGIC;
    txcompliance_reg2_reg_1 : out STD_LOGIC;
    txcompliance_reg2_reg_2 : out STD_LOGIC;
    txelecidle_reg2_reg_0 : out STD_LOGIC;
    PIPE_PHYSTATUS : out STD_LOGIC_VECTOR ( 0 to 0 );
    resetovrd_start_reg2_reg_0 : in STD_LOGIC;
    pclk_sel_reg1_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    resetovrd_start_reg2_reg_1 : in STD_LOGIC;
    gt_txresetdone_0 : in STD_LOGIC;
    gt_rxresetdone_0 : in STD_LOGIC;
    pipe_tx0_elec_idle : in STD_LOGIC;
    pipe_tx0_compliance : in STD_LOGIC;
    gt_rxcdrlock_0 : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxvalid_0 : in STD_LOGIC;
    pipe_rxstatus : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    rate_done_reg1_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    SYNC_GEN3 : in STD_LOGIC;
    rxeq_adapt_done_reg1_reg_0 : in STD_LOGIC;
    gt_rxvalid_q_reg : in STD_LOGIC;
    gt_rxvalid_q_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxvalid_q_reg_1 : in STD_LOGIC;
    \cplllock_reg1_reg[1]\ : in STD_LOGIC;
    \cplllock_reg1_reg[1]_0\ : in STD_LOGIC;
    \cplllock_reg1_reg[1]_1\ : in STD_LOGIC;
    \FSM_onehot_txsync_fsm.fsm_tx_reg[4]\ : in STD_LOGIC;
    p_1_in0_in : in STD_LOGIC;
    \txsync_fsm.txsync_done_reg\ : in STD_LOGIC;
    p_1_in : in STD_LOGIC;
    gt_rxvalid_q_reg_2 : in STD_LOGIC;
    PIPE_RXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rx_phy_status_q_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_user : entity is "spec7_pcie_7x_0_pipe_user";
end spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_user;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_user is
  signal \converge_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_4__0_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_5__0_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_6_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_7__0_n_0\ : STD_LOGIC;
  signal converge_cnt_reg : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal \converge_cnt_reg[0]_i_3_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[0]_i_3_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[0]_i_3_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[0]_i_3_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[0]_i_3_n_4\ : STD_LOGIC;
  signal \converge_cnt_reg[0]_i_3_n_5\ : STD_LOGIC;
  signal \converge_cnt_reg[0]_i_3_n_6\ : STD_LOGIC;
  signal \converge_cnt_reg[0]_i_3_n_7\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_1_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_1_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_1_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_1_n_4\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_1_n_5\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_1_n_6\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_1_n_7\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_1_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_1_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_1_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_1_n_4\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_1_n_5\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_1_n_6\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_1_n_7\ : STD_LOGIC;
  signal \converge_cnt_reg[20]_i_1_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[20]_i_1_n_6\ : STD_LOGIC;
  signal \converge_cnt_reg[20]_i_1_n_7\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_1_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_1_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_1_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_1_n_4\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_1_n_5\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_1_n_6\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_1_n_7\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_1_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_1_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_1_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_1_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_1_n_4\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_1_n_5\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_1_n_6\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_1_n_7\ : STD_LOGIC;
  signal converge_gen3_i_1_n_0 : STD_LOGIC;
  signal converge_gen3_reg_n_0 : STD_LOGIC;
  signal \gt_rxvalid_q_i_3__0_n_0\ : STD_LOGIC;
  signal gt_rxvalid_q_i_4_n_0 : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_49_n_0\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_50_n_0\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_53_n_0\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_54_n_0\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_55_n_0\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_56_n_0\ : STD_LOGIC;
  signal oobclk_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \oobclk_div.oobclk_i_1_n_0\ : STD_LOGIC;
  signal \p_0_in__1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pclk_sel_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of pclk_sel_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of pclk_sel_reg1 : signal is "true";
  signal pclk_sel_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of pclk_sel_reg2 : signal is "NO";
  attribute async_reg of pclk_sel_reg2 : signal is "true";
  signal rate_done_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_done_reg1 : signal is "NO";
  attribute async_reg of rate_done_reg1 : signal is "true";
  signal rate_done_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_done_reg2 : signal is "NO";
  attribute async_reg of rate_done_reg2 : signal is "true";
  signal rate_gen3_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_gen3_reg1 : signal is "NO";
  attribute async_reg of rate_gen3_reg1 : signal is "true";
  signal rate_gen3_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_gen3_reg2 : signal is "NO";
  attribute async_reg of rate_gen3_reg2 : signal is "true";
  signal rate_idle_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_idle_reg1 : signal is "NO";
  attribute async_reg of rate_idle_reg1 : signal is "true";
  signal rate_idle_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_idle_reg2 : signal is "NO";
  attribute async_reg of rate_idle_reg2 : signal is "true";
  signal rate_rxsync_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_rxsync_reg1 : signal is "NO";
  attribute async_reg of rate_rxsync_reg1 : signal is "true";
  signal rate_rxsync_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_rxsync_reg2 : signal is "NO";
  attribute async_reg of rate_rxsync_reg2 : signal is "true";
  signal resetovrd_start_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of resetovrd_start_reg1 : signal is "NO";
  attribute async_reg of resetovrd_start_reg1 : signal is "true";
  signal resetovrd_start_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of resetovrd_start_reg2 : signal is "NO";
  attribute async_reg of resetovrd_start_reg2 : signal is "true";
  signal rst_idle_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rst_idle_reg1 : signal is "NO";
  attribute async_reg of rst_idle_reg1 : signal is "true";
  signal rst_idle_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rst_idle_reg2 : signal is "NO";
  attribute async_reg of rst_idle_reg2 : signal is "true";
  signal rxcdrlock_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxcdrlock_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxcdrlock_reg1 : signal is "NO";
  attribute async_reg of rxcdrlock_reg1 : signal is "true";
  signal rxcdrlock_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxcdrlock_reg2 : signal is "NO";
  attribute async_reg of rxcdrlock_reg2 : signal is "true";
  signal rxeq_adapt_done_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxeq_adapt_done_reg1 : signal is "NO";
  attribute async_reg of rxeq_adapt_done_reg1 : signal is "true";
  signal rxeq_adapt_done_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxeq_adapt_done_reg2 : signal is "NO";
  attribute async_reg of rxeq_adapt_done_reg2 : signal is "true";
  signal rxresetdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxresetdone_reg1 : signal is "NO";
  attribute async_reg of rxresetdone_reg1 : signal is "true";
  signal rxresetdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxresetdone_reg2 : signal is "NO";
  attribute async_reg of rxresetdone_reg2 : signal is "true";
  signal rxstatus_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxstatus_reg1 : signal is "NO";
  attribute async_reg of rxstatus_reg1 : signal is "true";
  signal rxstatus_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxstatus_reg2 : signal is "NO";
  attribute async_reg of rxstatus_reg2 : signal is "true";
  signal rxvalid_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxvalid_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxvalid_reg1 : signal is "NO";
  attribute async_reg of rxvalid_reg1 : signal is "true";
  signal rxvalid_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxvalid_reg2 : signal is "NO";
  attribute async_reg of rxvalid_reg2 : signal is "true";
  signal sel : STD_LOGIC;
  signal txcompliance_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txcompliance_reg1 : signal is "NO";
  attribute async_reg of txcompliance_reg1 : signal is "true";
  signal txcompliance_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txcompliance_reg2 : signal is "NO";
  attribute async_reg of txcompliance_reg2 : signal is "true";
  signal txelecidle_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txelecidle_reg1 : signal is "NO";
  attribute async_reg of txelecidle_reg1 : signal is "true";
  signal txelecidle_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txelecidle_reg2 : signal is "NO";
  attribute async_reg of txelecidle_reg2 : signal is "true";
  signal txresetdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txresetdone_reg1 : signal is "NO";
  attribute async_reg of txresetdone_reg1 : signal is "true";
  signal txresetdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txresetdone_reg2 : signal is "NO";
  attribute async_reg of txresetdone_reg2 : signal is "true";
  signal \NLW_converge_cnt_reg[20]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_converge_cnt_reg[20]_i_1_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \converge_cnt[0]_i_5__0\ : label is "soft_lutpair45";
  attribute SOFT_HLUTNM of \converge_cnt[0]_i_7__0\ : label is "soft_lutpair46";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_55\ : label is "soft_lutpair46";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_56\ : label is "soft_lutpair45";
  attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[0]_i_1\ : label is "soft_lutpair47";
  attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[1]_i_1\ : label is "soft_lutpair47";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of pclk_sel_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of pclk_sel_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of pclk_sel_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of pclk_sel_reg2_reg : label is std.standard.true;
  attribute KEEP of pclk_sel_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of pclk_sel_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_done_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_done_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_done_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_done_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_gen3_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_gen3_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_gen3_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_gen3_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_gen3_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_idle_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_idle_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_rxsync_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_rxsync_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_rxsync_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_rxsync_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_rxsync_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_rxsync_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of resetovrd_start_reg1_reg : label is std.standard.true;
  attribute KEEP of resetovrd_start_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of resetovrd_start_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of resetovrd_start_reg2_reg : label is std.standard.true;
  attribute KEEP of resetovrd_start_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of resetovrd_start_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rst_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rst_idle_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rst_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rst_idle_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxcdrlock_reg1_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxcdrlock_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxcdrlock_reg2_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxcdrlock_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxeq_adapt_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_adapt_done_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxeq_adapt_done_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxeq_adapt_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_adapt_done_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxeq_adapt_done_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxresetdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxresetdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxstatus_reg1_reg : label is std.standard.true;
  attribute KEEP of rxstatus_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxstatus_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxstatus_reg2_reg : label is std.standard.true;
  attribute KEEP of rxstatus_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxstatus_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxvalid_reg1_reg : label is std.standard.true;
  attribute KEEP of rxvalid_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxvalid_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxvalid_reg2_reg : label is std.standard.true;
  attribute KEEP of rxvalid_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxvalid_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txcompliance_reg1_reg : label is std.standard.true;
  attribute KEEP of txcompliance_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txcompliance_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txcompliance_reg2_reg : label is std.standard.true;
  attribute KEEP of txcompliance_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txcompliance_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txelecidle_reg1_reg : label is std.standard.true;
  attribute KEEP of txelecidle_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txelecidle_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txelecidle_reg2_reg : label is std.standard.true;
  attribute KEEP of txelecidle_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txelecidle_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txresetdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txresetdone_reg2_reg : label is "NO";
begin
  \out\ <= txelecidle_reg2;
  rst_idle_reg2_reg_0 <= rst_idle_reg2;
  txcompliance_reg2_reg_0 <= txcompliance_reg2;
\FSM_onehot_txsync_fsm.fsm_tx[4]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7077"
    )
        port map (
      I0 => txcompliance_reg2,
      I1 => txelecidle_reg2,
      I2 => \FSM_onehot_txsync_fsm.fsm_tx_reg[4]\,
      I3 => p_1_in0_in,
      O => txcompliance_reg2_reg_1
    );
\FSM_onehot_txsync_fsm.fsm_tx[5]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7077"
    )
        port map (
      I0 => txcompliance_reg2,
      I1 => txelecidle_reg2,
      I2 => \txsync_fsm.txsync_done_reg\,
      I3 => p_1_in,
      O => txcompliance_reg2_reg_2
    );
\FSM_onehot_txsync_fsm.fsm_tx[5]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => txelecidle_reg2,
      I1 => txcompliance_reg2,
      O => txelecidle_reg2_reg_0
    );
\converge_cnt[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF7"
    )
        port map (
      I0 => rate_idle_reg2,
      I1 => rst_idle_reg2,
      I2 => resetovrd_start_reg2_reg_0,
      I3 => rate_gen3_reg2,
      O => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt[0]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55555555FFFF55F7"
    )
        port map (
      I0 => converge_cnt_reg(21),
      I1 => converge_cnt_reg(13),
      I2 => \converge_cnt[0]_i_4__0_n_0\,
      I3 => converge_cnt_reg(14),
      I4 => \converge_cnt[0]_i_5__0_n_0\,
      I5 => converge_cnt_reg(20),
      O => sel
    );
\converge_cnt[0]_i_4__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007FFFFFFF"
    )
        port map (
      I0 => \converge_cnt[0]_i_7__0_n_0\,
      I1 => converge_cnt_reg(9),
      I2 => converge_cnt_reg(8),
      I3 => converge_cnt_reg(10),
      I4 => converge_cnt_reg(11),
      I5 => converge_cnt_reg(12),
      O => \converge_cnt[0]_i_4__0_n_0\
    );
\converge_cnt[0]_i_5__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => converge_cnt_reg(19),
      I1 => converge_cnt_reg(18),
      I2 => converge_cnt_reg(16),
      I3 => converge_cnt_reg(15),
      I4 => converge_cnt_reg(17),
      O => \converge_cnt[0]_i_5__0_n_0\
    );
\converge_cnt[0]_i_6\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => converge_cnt_reg(0),
      O => \converge_cnt[0]_i_6_n_0\
    );
\converge_cnt[0]_i_7__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => converge_cnt_reg(4),
      I1 => converge_cnt_reg(5),
      I2 => converge_cnt_reg(7),
      I3 => converge_cnt_reg(6),
      I4 => converge_cnt_reg(3),
      O => \converge_cnt[0]_i_7__0_n_0\
    );
\converge_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[0]_i_3_n_7\,
      Q => converge_cnt_reg(0),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[0]_i_3\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \converge_cnt_reg[0]_i_3_n_0\,
      CO(2) => \converge_cnt_reg[0]_i_3_n_1\,
      CO(1) => \converge_cnt_reg[0]_i_3_n_2\,
      CO(0) => \converge_cnt_reg[0]_i_3_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \converge_cnt_reg[0]_i_3_n_4\,
      O(2) => \converge_cnt_reg[0]_i_3_n_5\,
      O(1) => \converge_cnt_reg[0]_i_3_n_6\,
      O(0) => \converge_cnt_reg[0]_i_3_n_7\,
      S(3 downto 1) => converge_cnt_reg(3 downto 1),
      S(0) => \converge_cnt[0]_i_6_n_0\
    );
\converge_cnt_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[8]_i_1_n_5\,
      Q => converge_cnt_reg(10),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[8]_i_1_n_4\,
      Q => converge_cnt_reg(11),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[12]_i_1_n_7\,
      Q => converge_cnt_reg(12),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[12]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[8]_i_1_n_0\,
      CO(3) => \converge_cnt_reg[12]_i_1_n_0\,
      CO(2) => \converge_cnt_reg[12]_i_1_n_1\,
      CO(1) => \converge_cnt_reg[12]_i_1_n_2\,
      CO(0) => \converge_cnt_reg[12]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \converge_cnt_reg[12]_i_1_n_4\,
      O(2) => \converge_cnt_reg[12]_i_1_n_5\,
      O(1) => \converge_cnt_reg[12]_i_1_n_6\,
      O(0) => \converge_cnt_reg[12]_i_1_n_7\,
      S(3 downto 0) => converge_cnt_reg(15 downto 12)
    );
\converge_cnt_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[12]_i_1_n_6\,
      Q => converge_cnt_reg(13),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[12]_i_1_n_5\,
      Q => converge_cnt_reg(14),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[12]_i_1_n_4\,
      Q => converge_cnt_reg(15),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[16]_i_1_n_7\,
      Q => converge_cnt_reg(16),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[16]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[12]_i_1_n_0\,
      CO(3) => \converge_cnt_reg[16]_i_1_n_0\,
      CO(2) => \converge_cnt_reg[16]_i_1_n_1\,
      CO(1) => \converge_cnt_reg[16]_i_1_n_2\,
      CO(0) => \converge_cnt_reg[16]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \converge_cnt_reg[16]_i_1_n_4\,
      O(2) => \converge_cnt_reg[16]_i_1_n_5\,
      O(1) => \converge_cnt_reg[16]_i_1_n_6\,
      O(0) => \converge_cnt_reg[16]_i_1_n_7\,
      S(3 downto 0) => converge_cnt_reg(19 downto 16)
    );
\converge_cnt_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[16]_i_1_n_6\,
      Q => converge_cnt_reg(17),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[16]_i_1_n_5\,
      Q => converge_cnt_reg(18),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[16]_i_1_n_4\,
      Q => converge_cnt_reg(19),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[0]_i_3_n_6\,
      Q => converge_cnt_reg(1),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[20]_i_1_n_7\,
      Q => converge_cnt_reg(20),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[20]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[16]_i_1_n_0\,
      CO(3 downto 1) => \NLW_converge_cnt_reg[20]_i_1_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \converge_cnt_reg[20]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 2) => \NLW_converge_cnt_reg[20]_i_1_O_UNCONNECTED\(3 downto 2),
      O(1) => \converge_cnt_reg[20]_i_1_n_6\,
      O(0) => \converge_cnt_reg[20]_i_1_n_7\,
      S(3 downto 2) => B"00",
      S(1 downto 0) => converge_cnt_reg(21 downto 20)
    );
\converge_cnt_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[20]_i_1_n_6\,
      Q => converge_cnt_reg(21),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[0]_i_3_n_5\,
      Q => converge_cnt_reg(2),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[0]_i_3_n_4\,
      Q => converge_cnt_reg(3),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[4]_i_1_n_7\,
      Q => converge_cnt_reg(4),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[4]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[0]_i_3_n_0\,
      CO(3) => \converge_cnt_reg[4]_i_1_n_0\,
      CO(2) => \converge_cnt_reg[4]_i_1_n_1\,
      CO(1) => \converge_cnt_reg[4]_i_1_n_2\,
      CO(0) => \converge_cnt_reg[4]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \converge_cnt_reg[4]_i_1_n_4\,
      O(2) => \converge_cnt_reg[4]_i_1_n_5\,
      O(1) => \converge_cnt_reg[4]_i_1_n_6\,
      O(0) => \converge_cnt_reg[4]_i_1_n_7\,
      S(3 downto 0) => converge_cnt_reg(7 downto 4)
    );
\converge_cnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[4]_i_1_n_6\,
      Q => converge_cnt_reg(5),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[4]_i_1_n_5\,
      Q => converge_cnt_reg(6),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[4]_i_1_n_4\,
      Q => converge_cnt_reg(7),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[8]_i_1_n_7\,
      Q => converge_cnt_reg(8),
      R => \converge_cnt[0]_i_1_n_0\
    );
\converge_cnt_reg[8]_i_1\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[4]_i_1_n_0\,
      CO(3) => \converge_cnt_reg[8]_i_1_n_0\,
      CO(2) => \converge_cnt_reg[8]_i_1_n_1\,
      CO(1) => \converge_cnt_reg[8]_i_1_n_2\,
      CO(0) => \converge_cnt_reg[8]_i_1_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \converge_cnt_reg[8]_i_1_n_4\,
      O(2) => \converge_cnt_reg[8]_i_1_n_5\,
      O(1) => \converge_cnt_reg[8]_i_1_n_6\,
      O(0) => \converge_cnt_reg[8]_i_1_n_7\,
      S(3 downto 0) => converge_cnt_reg(11 downto 8)
    );
\converge_cnt_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[8]_i_1_n_6\,
      Q => converge_cnt_reg(9),
      R => \converge_cnt[0]_i_1_n_0\
    );
converge_gen3_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => rxeq_adapt_done_reg2,
      I1 => rate_gen3_reg2,
      I2 => converge_gen3_reg_n_0,
      O => converge_gen3_i_1_n_0
    );
converge_gen3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => converge_gen3_i_1_n_0,
      Q => converge_gen3_reg_n_0,
      R => resetovrd_start_reg2_reg_0
    );
\gt_rx_phy_status_q_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFE0FF"
    )
        port map (
      I0 => rate_idle_reg2,
      I1 => rate_rxsync_reg2,
      I2 => gt_rx_phy_status_q_reg(0),
      I3 => rst_idle_reg2,
      I4 => rate_done_reg2,
      O => PIPE_PHYSTATUS(0)
    );
gt_rxvalid_q_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0008000800000008"
    )
        port map (
      I0 => gt_rxvalid_q_reg,
      I1 => rxvalid_cnt_reg(3),
      I2 => \gt_rxvalid_q_i_3__0_n_0\,
      I3 => gt_rxvalid_q_i_4_n_0,
      I4 => gt_rxvalid_q_reg_0(0),
      I5 => gt_rxvalid_q_reg_1,
      O => gt_rxvalid_q
    );
\gt_rxvalid_q_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"7F"
    )
        port map (
      I0 => rxvalid_cnt_reg(1),
      I1 => rxvalid_cnt_reg(0),
      I2 => rxvalid_cnt_reg(2),
      O => \gt_rxvalid_q_i_3__0_n_0\
    );
gt_rxvalid_q_i_4: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7F77FFFF"
    )
        port map (
      I0 => rate_idle_reg2,
      I1 => rst_idle_reg2,
      I2 => gt_rxvalid_q_reg_2,
      I3 => PIPE_RXELECIDLE(0),
      I4 => gt_rxvalid_0,
      O => gt_rxvalid_q_i_4_n_0
    );
\gtx_channel.gtxe2_channel_i_i_49\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001000"
    )
        port map (
      I0 => converge_cnt_reg(0),
      I1 => converge_cnt_reg(12),
      I2 => converge_cnt_reg(10),
      I3 => converge_cnt_reg(21),
      I4 => \gtx_channel.gtxe2_channel_i_i_53_n_0\,
      O => \gtx_channel.gtxe2_channel_i_i_49_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_50\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFEFF"
    )
        port map (
      I0 => \gtx_channel.gtxe2_channel_i_i_54_n_0\,
      I1 => converge_cnt_reg(1),
      I2 => converge_cnt_reg(20),
      I3 => converge_cnt_reg(17),
      I4 => \gtx_channel.gtxe2_channel_i_i_55_n_0\,
      I5 => \gtx_channel.gtxe2_channel_i_i_56_n_0\,
      O => \gtx_channel.gtxe2_channel_i_i_50_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_53\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => converge_cnt_reg(9),
      I1 => converge_cnt_reg(8),
      I2 => converge_cnt_reg(11),
      I3 => converge_cnt_reg(13),
      O => \gtx_channel.gtxe2_channel_i_i_53_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_54\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => converge_cnt_reg(3),
      I1 => converge_cnt_reg(2),
      I2 => converge_cnt_reg(6),
      I3 => converge_cnt_reg(14),
      O => \gtx_channel.gtxe2_channel_i_i_54_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_55\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => converge_cnt_reg(7),
      I1 => converge_cnt_reg(5),
      I2 => converge_cnt_reg(4),
      O => \gtx_channel.gtxe2_channel_i_i_55_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_56\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => converge_cnt_reg(15),
      I1 => converge_cnt_reg(16),
      I2 => converge_cnt_reg(18),
      I3 => converge_cnt_reg(19),
      O => \gtx_channel.gtxe2_channel_i_i_56_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F200F2F2F200F200"
    )
        port map (
      I0 => \gtx_channel.gtxe2_channel_i_i_49_n_0\,
      I1 => \gtx_channel.gtxe2_channel_i_i_50_n_0\,
      I2 => converge_gen3_reg_n_0,
      I3 => \cplllock_reg1_reg[1]\,
      I4 => \cplllock_reg1_reg[1]_0\,
      I5 => \cplllock_reg1_reg[1]_1\,
      O => converge_gen3_reg_0
    );
\oobclk_div.oobclk_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => oobclk_cnt(0),
      O => \p_1_in__0\(0)
    );
\oobclk_div.oobclk_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => oobclk_cnt(0),
      I1 => oobclk_cnt(1),
      O => \p_1_in__0\(1)
    );
\oobclk_div.oobclk_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => \p_1_in__0\(0),
      Q => oobclk_cnt(0),
      R => resetovrd_start_reg2_reg_0
    );
\oobclk_div.oobclk_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => \p_1_in__0\(1),
      Q => oobclk_cnt(1),
      R => resetovrd_start_reg2_reg_0
    );
\oobclk_div.oobclk_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => oobclk_cnt(1),
      I1 => pclk_sel_reg2,
      I2 => oobclk_cnt(0),
      O => \oobclk_div.oobclk_i_1_n_0\
    );
\oobclk_div.oobclk_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => \oobclk_div.oobclk_i_1_n_0\,
      Q => CLKRSVD(0),
      R => resetovrd_start_reg2_reg_0
    );
pclk_sel_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => pclk_sel_reg1_reg_0(0),
      Q => pclk_sel_reg1,
      R => resetovrd_start_reg2_reg_0
    );
pclk_sel_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => pclk_sel_reg1,
      Q => pclk_sel_reg2,
      R => resetovrd_start_reg2_reg_0
    );
rate_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => rate_done_reg1_reg_0(1),
      Q => rate_done_reg1,
      R => SR(0)
    );
rate_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => rate_done_reg1,
      Q => rate_done_reg2,
      R => SR(0)
    );
rate_gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => SYNC_GEN3,
      Q => rate_gen3_reg1,
      R => SR(0)
    );
rate_gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => rate_gen3_reg1,
      Q => rate_gen3_reg2,
      R => SR(0)
    );
rate_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => rate_done_reg1_reg_0(0),
      Q => rate_idle_reg1,
      R => SR(0)
    );
rate_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => rate_idle_reg1,
      Q => rate_idle_reg2,
      R => SR(0)
    );
rate_rxsync_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => '0',
      Q => rate_rxsync_reg1,
      R => SR(0)
    );
rate_rxsync_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => rate_rxsync_reg1,
      Q => rate_rxsync_reg2,
      R => SR(0)
    );
\resetdone_reg1[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => rxresetdone_reg2,
      I1 => txresetdone_reg2,
      O => D(0)
    );
resetovrd_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => '0',
      Q => resetovrd_start_reg1,
      R => resetovrd_start_reg2_reg_0
    );
resetovrd_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => resetovrd_start_reg1,
      Q => resetovrd_start_reg2,
      R => resetovrd_start_reg2_reg_0
    );
rst_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => Q(0),
      Q => rst_idle_reg1,
      R => SR(0)
    );
rst_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => rst_idle_reg1,
      Q => rst_idle_reg2,
      R => SR(0)
    );
\rxcdrlock_cnt[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8A0A0A0A"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => rxcdrlock_cnt_reg(3),
      I2 => rxcdrlock_cnt_reg(0),
      I3 => rxcdrlock_cnt_reg(1),
      I4 => rxcdrlock_cnt_reg(2),
      O => \p_0_in__1\(0)
    );
\rxcdrlock_cnt[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8282828"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => rxcdrlock_cnt_reg(0),
      I2 => rxcdrlock_cnt_reg(1),
      I3 => rxcdrlock_cnt_reg(3),
      I4 => rxcdrlock_cnt_reg(2),
      O => \p_0_in__1\(1)
    );
\rxcdrlock_cnt[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BCCC0000"
    )
        port map (
      I0 => rxcdrlock_cnt_reg(3),
      I1 => rxcdrlock_cnt_reg(2),
      I2 => rxcdrlock_cnt_reg(1),
      I3 => rxcdrlock_cnt_reg(0),
      I4 => rxcdrlock_reg2,
      O => \p_0_in__1\(2)
    );
\rxcdrlock_cnt[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA8000"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => rxcdrlock_cnt_reg(2),
      I2 => rxcdrlock_cnt_reg(1),
      I3 => rxcdrlock_cnt_reg(0),
      I4 => rxcdrlock_cnt_reg(3),
      O => \p_0_in__1\(3)
    );
\rxcdrlock_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => \p_0_in__1\(0),
      Q => rxcdrlock_cnt_reg(0),
      R => resetovrd_start_reg2_reg_0
    );
\rxcdrlock_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => \p_0_in__1\(1),
      Q => rxcdrlock_cnt_reg(1),
      R => resetovrd_start_reg2_reg_0
    );
\rxcdrlock_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => \p_0_in__1\(2),
      Q => rxcdrlock_cnt_reg(2),
      R => resetovrd_start_reg2_reg_0
    );
\rxcdrlock_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => \p_0_in__1\(3),
      Q => rxcdrlock_cnt_reg(3),
      R => resetovrd_start_reg2_reg_0
    );
\rxcdrlock_reg1[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => gt_rxcdrlock_0,
      I1 => rxcdrlock_cnt_reg(2),
      I2 => rxcdrlock_cnt_reg(1),
      I3 => rxcdrlock_cnt_reg(0),
      I4 => rxcdrlock_cnt_reg(3),
      O => \rxcdrlock_cnt_reg[2]_0\(0)
    );
rxcdrlock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => gt_rxcdrlock_0,
      Q => rxcdrlock_reg1,
      R => resetovrd_start_reg2_reg_0
    );
rxcdrlock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => rxcdrlock_reg1,
      Q => rxcdrlock_reg2,
      R => resetovrd_start_reg2_reg_0
    );
rxeq_adapt_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => rxeq_adapt_done_reg1_reg_0,
      Q => rxeq_adapt_done_reg1,
      R => resetovrd_start_reg2_reg_0
    );
rxeq_adapt_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => rxeq_adapt_done_reg1,
      Q => rxeq_adapt_done_reg2,
      R => resetovrd_start_reg2_reg_0
    );
rxresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => gt_rxresetdone_0,
      Q => rxresetdone_reg1,
      R => resetovrd_start_reg2_reg_0
    );
rxresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => rxresetdone_reg1,
      Q => rxresetdone_reg2,
      R => resetovrd_start_reg2_reg_0
    );
rxstatus_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => pipe_rxstatus(0),
      Q => rxstatus_reg1,
      R => SR(0)
    );
rxstatus_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => rxstatus_reg1,
      Q => rxstatus_reg2,
      R => SR(0)
    );
\rxvalid_cnt[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8080000000FF0000"
    )
        port map (
      I0 => rxvalid_cnt_reg(2),
      I1 => rxvalid_cnt_reg(1),
      I2 => rxvalid_cnt_reg(3),
      I3 => rxstatus_reg2,
      I4 => rxvalid_reg2,
      I5 => rxvalid_cnt_reg(0),
      O => \p_0_in__2\(0)
    );
\rxvalid_cnt[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"808000F000F00000"
    )
        port map (
      I0 => rxvalid_cnt_reg(2),
      I1 => rxvalid_cnt_reg(3),
      I2 => rxvalid_reg2,
      I3 => rxstatus_reg2,
      I4 => rxvalid_cnt_reg(1),
      I5 => rxvalid_cnt_reg(0),
      O => \p_0_in__2\(1)
    );
\rxvalid_cnt[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"880C0C000C000C00"
    )
        port map (
      I0 => rxvalid_cnt_reg(3),
      I1 => rxvalid_reg2,
      I2 => rxstatus_reg2,
      I3 => rxvalid_cnt_reg(2),
      I4 => rxvalid_cnt_reg(0),
      I5 => rxvalid_cnt_reg(1),
      O => \p_0_in__2\(2)
    );
\rxvalid_cnt[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"C440404040404040"
    )
        port map (
      I0 => rxstatus_reg2,
      I1 => rxvalid_reg2,
      I2 => rxvalid_cnt_reg(3),
      I3 => rxvalid_cnt_reg(2),
      I4 => rxvalid_cnt_reg(0),
      I5 => rxvalid_cnt_reg(1),
      O => \p_0_in__2\(3)
    );
\rxvalid_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => \p_0_in__2\(0),
      Q => rxvalid_cnt_reg(0),
      R => SR(0)
    );
\rxvalid_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => \p_0_in__2\(1),
      Q => rxvalid_cnt_reg(1),
      R => SR(0)
    );
\rxvalid_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => \p_0_in__2\(2),
      Q => rxvalid_cnt_reg(2),
      R => SR(0)
    );
\rxvalid_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => \p_0_in__2\(3),
      Q => rxvalid_cnt_reg(3),
      R => SR(0)
    );
rxvalid_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => gt_rxvalid_0,
      Q => rxvalid_reg1,
      R => SR(0)
    );
rxvalid_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => rxvalid_reg1,
      Q => rxvalid_reg2,
      R => SR(0)
    );
txcompliance_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => pipe_tx0_compliance,
      Q => txcompliance_reg1,
      R => resetovrd_start_reg2_reg_0
    );
txcompliance_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => txcompliance_reg1,
      Q => txcompliance_reg2,
      R => resetovrd_start_reg2_reg_0
    );
txelecidle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => pipe_tx0_elec_idle,
      Q => txelecidle_reg1,
      R => resetovrd_start_reg2_reg_0
    );
txelecidle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => txelecidle_reg1,
      Q => txelecidle_reg2,
      R => resetovrd_start_reg2_reg_0
    );
txresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => gt_txresetdone_0,
      Q => txresetdone_reg1,
      R => resetovrd_start_reg2_reg_0
    );
txresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => txresetdone_reg1,
      Q => txresetdone_reg2,
      R => resetovrd_start_reg2_reg_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_user_21 is
  port (
    \out\ : out STD_LOGIC;
    txcompliance_reg2_reg_0 : out STD_LOGIC;
    CLKRSVD : out STD_LOGIC_VECTOR ( 0 to 0 );
    converge_gen3_reg_0 : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    \rxcdrlock_cnt_reg[2]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxvalid_q_reg : out STD_LOGIC;
    \converge_cnt_reg[0]_0\ : out STD_LOGIC;
    \converge_cnt_reg[11]_0\ : out STD_LOGIC;
    SYNC_TXPHINITDONE : out STD_LOGIC;
    SYNC_TXPHALIGNDONE : out STD_LOGIC;
    txcompliance_reg2_reg_1 : out STD_LOGIC;
    txelecidle_reg2_reg_0 : out STD_LOGIC;
    rst_idle_reg2_reg_0 : out STD_LOGIC;
    PIPE_PHYSTATUS : out STD_LOGIC_VECTOR ( 0 to 0 );
    resetovrd_start_reg2_reg_0 : in STD_LOGIC;
    pclk_sel_reg1_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
    resetovrd_start_reg2_reg_1 : in STD_LOGIC;
    gt_txresetdone_1 : in STD_LOGIC;
    gt_rxresetdone_1 : in STD_LOGIC;
    pipe_tx1_elec_idle : in STD_LOGIC;
    pipe_tx1_compliance : in STD_LOGIC;
    gt_rxcdrlock_1 : in STD_LOGIC;
    SR : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxvalid_1 : in STD_LOGIC;
    pipe_rxstatus : in STD_LOGIC_VECTOR ( 0 to 0 );
    Q : in STD_LOGIC_VECTOR ( 0 to 0 );
    rate_done_reg1_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rate_gen3_1 : in STD_LOGIC;
    rxeq_adapt_done_reg1_reg_0 : in STD_LOGIC;
    PIPE_RXELECIDLE : in STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxvalid_q_reg_0 : in STD_LOGIC;
    pipe_txphinitdone : in STD_LOGIC_VECTOR ( 1 downto 0 );
    txphinitdone_reg1_reg : in STD_LOGIC;
    txphinitdone_reg1_reg_0 : in STD_LOGIC;
    pipe_txphaligndone : in STD_LOGIC_VECTOR ( 1 downto 0 );
    \FSM_onehot_txsync_fsm.fsm_tx_reg[4]\ : in STD_LOGIC;
    p_1_in0_in : in STD_LOGIC;
    reg_clock_locked : in STD_LOGIC;
    phy_rdy_n_int_reg : in STD_LOGIC;
    gt_rx_phy_status_q_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_user_21 : entity is "spec7_pcie_7x_0_pipe_user";
end spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_user_21;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_user_21 is
  signal \converge_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_4_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_5_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_6__0_n_0\ : STD_LOGIC;
  signal \converge_cnt[0]_i_7_n_0\ : STD_LOGIC;
  signal converge_cnt_reg : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal \converge_cnt_reg[0]_i_3__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[0]_i_3__0_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[0]_i_3__0_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[0]_i_3__0_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[0]_i_3__0_n_4\ : STD_LOGIC;
  signal \converge_cnt_reg[0]_i_3__0_n_5\ : STD_LOGIC;
  signal \converge_cnt_reg[0]_i_3__0_n_6\ : STD_LOGIC;
  signal \converge_cnt_reg[0]_i_3__0_n_7\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_1__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_1__0_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_1__0_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_1__0_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_1__0_n_4\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_1__0_n_5\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_1__0_n_6\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_1__0_n_7\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_1__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_1__0_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_1__0_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_1__0_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_1__0_n_4\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_1__0_n_5\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_1__0_n_6\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_1__0_n_7\ : STD_LOGIC;
  signal \converge_cnt_reg[20]_i_1__0_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[20]_i_1__0_n_6\ : STD_LOGIC;
  signal \converge_cnt_reg[20]_i_1__0_n_7\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_1__0_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_1__0_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_1__0_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_1__0_n_4\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_1__0_n_5\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_1__0_n_6\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_1__0_n_7\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_1__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_1__0_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_1__0_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_1__0_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_1__0_n_4\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_1__0_n_5\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_1__0_n_6\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_1__0_n_7\ : STD_LOGIC;
  signal \converge_gen3_i_1__0_n_0\ : STD_LOGIC;
  signal \^converge_gen3_reg_0\ : STD_LOGIC;
  signal gt_rxvalid_q_i_5_n_0 : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_57_n_0\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_58_n_0\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_59_n_0\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_i_60_n_0\ : STD_LOGIC;
  signal oobclk_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \oobclk_div.oobclk_i_1__0_n_0\ : STD_LOGIC;
  signal \p_0_in__4\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_0_in__5\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \p_1_in__0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pclk_sel_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of pclk_sel_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of pclk_sel_reg1 : signal is "true";
  signal pclk_sel_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of pclk_sel_reg2 : signal is "NO";
  attribute async_reg of pclk_sel_reg2 : signal is "true";
  signal rate_done_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_done_reg1 : signal is "NO";
  attribute async_reg of rate_done_reg1 : signal is "true";
  signal rate_done_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_done_reg2 : signal is "NO";
  attribute async_reg of rate_done_reg2 : signal is "true";
  signal rate_gen3_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_gen3_reg1 : signal is "NO";
  attribute async_reg of rate_gen3_reg1 : signal is "true";
  signal rate_gen3_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_gen3_reg2 : signal is "NO";
  attribute async_reg of rate_gen3_reg2 : signal is "true";
  signal rate_idle_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_idle_reg1 : signal is "NO";
  attribute async_reg of rate_idle_reg1 : signal is "true";
  signal rate_idle_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_idle_reg2 : signal is "NO";
  attribute async_reg of rate_idle_reg2 : signal is "true";
  signal rate_rxsync_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_rxsync_reg1 : signal is "NO";
  attribute async_reg of rate_rxsync_reg1 : signal is "true";
  signal rate_rxsync_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rate_rxsync_reg2 : signal is "NO";
  attribute async_reg of rate_rxsync_reg2 : signal is "true";
  signal resetovrd_start_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of resetovrd_start_reg1 : signal is "NO";
  attribute async_reg of resetovrd_start_reg1 : signal is "true";
  signal resetovrd_start_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of resetovrd_start_reg2 : signal is "NO";
  attribute async_reg of resetovrd_start_reg2 : signal is "true";
  signal rst_idle_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rst_idle_reg1 : signal is "NO";
  attribute async_reg of rst_idle_reg1 : signal is "true";
  signal rst_idle_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rst_idle_reg2 : signal is "NO";
  attribute async_reg of rst_idle_reg2 : signal is "true";
  signal rxcdrlock_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxcdrlock_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxcdrlock_reg1 : signal is "NO";
  attribute async_reg of rxcdrlock_reg1 : signal is "true";
  signal rxcdrlock_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxcdrlock_reg2 : signal is "NO";
  attribute async_reg of rxcdrlock_reg2 : signal is "true";
  signal rxeq_adapt_done_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxeq_adapt_done_reg1 : signal is "NO";
  attribute async_reg of rxeq_adapt_done_reg1 : signal is "true";
  signal rxeq_adapt_done_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxeq_adapt_done_reg2 : signal is "NO";
  attribute async_reg of rxeq_adapt_done_reg2 : signal is "true";
  signal rxresetdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxresetdone_reg1 : signal is "NO";
  attribute async_reg of rxresetdone_reg1 : signal is "true";
  signal rxresetdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxresetdone_reg2 : signal is "NO";
  attribute async_reg of rxresetdone_reg2 : signal is "true";
  signal rxstatus_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxstatus_reg1 : signal is "NO";
  attribute async_reg of rxstatus_reg1 : signal is "true";
  signal rxstatus_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxstatus_reg2 : signal is "NO";
  attribute async_reg of rxstatus_reg2 : signal is "true";
  signal rxvalid_cnt_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal rxvalid_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxvalid_reg1 : signal is "NO";
  attribute async_reg of rxvalid_reg1 : signal is "true";
  signal rxvalid_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxvalid_reg2 : signal is "NO";
  attribute async_reg of rxvalid_reg2 : signal is "true";
  signal sel : STD_LOGIC;
  signal txcompliance_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txcompliance_reg1 : signal is "NO";
  attribute async_reg of txcompliance_reg1 : signal is "true";
  signal txcompliance_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txcompliance_reg2 : signal is "NO";
  attribute async_reg of txcompliance_reg2 : signal is "true";
  signal txelecidle_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txelecidle_reg1 : signal is "NO";
  attribute async_reg of txelecidle_reg1 : signal is "true";
  signal txelecidle_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txelecidle_reg2 : signal is "NO";
  attribute async_reg of txelecidle_reg2 : signal is "true";
  signal txresetdone_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txresetdone_reg1 : signal is "NO";
  attribute async_reg of txresetdone_reg1 : signal is "true";
  signal txresetdone_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of txresetdone_reg2 : signal is "NO";
  attribute async_reg of txresetdone_reg2 : signal is "true";
  signal \NLW_converge_cnt_reg[20]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  signal \NLW_converge_cnt_reg[20]_i_1__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \converge_cnt[0]_i_5\ : label is "soft_lutpair74";
  attribute SOFT_HLUTNM of \converge_cnt[0]_i_7\ : label is "soft_lutpair73";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_58\ : label is "soft_lutpair74";
  attribute SOFT_HLUTNM of \gtx_channel.gtxe2_channel_i_i_59\ : label is "soft_lutpair73";
  attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[0]_i_1\ : label is "soft_lutpair75";
  attribute SOFT_HLUTNM of \oobclk_div.oobclk_cnt[1]_i_1\ : label is "soft_lutpair75";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of pclk_sel_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of pclk_sel_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of pclk_sel_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of pclk_sel_reg2_reg : label is std.standard.true;
  attribute KEEP of pclk_sel_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of pclk_sel_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_done_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_done_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_done_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_done_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_gen3_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_gen3_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_gen3_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_gen3_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_gen3_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_idle_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_idle_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_idle_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_rxsync_reg1_reg : label is std.standard.true;
  attribute KEEP of rate_rxsync_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_rxsync_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rate_rxsync_reg2_reg : label is std.standard.true;
  attribute KEEP of rate_rxsync_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rate_rxsync_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of resetovrd_start_reg1_reg : label is std.standard.true;
  attribute KEEP of resetovrd_start_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of resetovrd_start_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of resetovrd_start_reg2_reg : label is std.standard.true;
  attribute KEEP of resetovrd_start_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of resetovrd_start_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rst_idle_reg1_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rst_idle_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rst_idle_reg2_reg : label is std.standard.true;
  attribute KEEP of rst_idle_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rst_idle_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxcdrlock_reg1_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxcdrlock_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxcdrlock_reg2_reg : label is std.standard.true;
  attribute KEEP of rxcdrlock_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxcdrlock_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxeq_adapt_done_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_adapt_done_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxeq_adapt_done_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxeq_adapt_done_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_adapt_done_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxeq_adapt_done_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxresetdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of rxresetdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxresetdone_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxstatus_reg1_reg : label is std.standard.true;
  attribute KEEP of rxstatus_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxstatus_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxstatus_reg2_reg : label is std.standard.true;
  attribute KEEP of rxstatus_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxstatus_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxvalid_reg1_reg : label is std.standard.true;
  attribute KEEP of rxvalid_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxvalid_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxvalid_reg2_reg : label is std.standard.true;
  attribute KEEP of rxvalid_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxvalid_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txcompliance_reg1_reg : label is std.standard.true;
  attribute KEEP of txcompliance_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txcompliance_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txcompliance_reg2_reg : label is std.standard.true;
  attribute KEEP of txcompliance_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txcompliance_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txelecidle_reg1_reg : label is std.standard.true;
  attribute KEEP of txelecidle_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txelecidle_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txelecidle_reg2_reg : label is std.standard.true;
  attribute KEEP of txelecidle_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txelecidle_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of txresetdone_reg1_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of txresetdone_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of txresetdone_reg2_reg : label is std.standard.true;
  attribute KEEP of txresetdone_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of txresetdone_reg2_reg : label is "NO";
begin
  converge_gen3_reg_0 <= \^converge_gen3_reg_0\;
  \out\ <= txelecidle_reg2;
  txcompliance_reg2_reg_0 <= txcompliance_reg2;
\FSM_onehot_txsync_fsm.fsm_tx[5]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => txelecidle_reg2,
      I1 => txcompliance_reg2,
      O => txelecidle_reg2_reg_0
    );
\FSM_onehot_txsync_fsm.fsm_tx[5]_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7077"
    )
        port map (
      I0 => txcompliance_reg2,
      I1 => txelecidle_reg2,
      I2 => \FSM_onehot_txsync_fsm.fsm_tx_reg[4]\,
      I3 => p_1_in0_in,
      O => txcompliance_reg2_reg_1
    );
\converge_cnt[0]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF7"
    )
        port map (
      I0 => rate_idle_reg2,
      I1 => rst_idle_reg2,
      I2 => resetovrd_start_reg2_reg_0,
      I3 => rate_gen3_reg2,
      O => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"55555555FFFF55F7"
    )
        port map (
      I0 => converge_cnt_reg(21),
      I1 => converge_cnt_reg(13),
      I2 => \converge_cnt[0]_i_4_n_0\,
      I3 => converge_cnt_reg(14),
      I4 => \converge_cnt[0]_i_5_n_0\,
      I5 => converge_cnt_reg(20),
      O => sel
    );
\converge_cnt[0]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000000007FFFFFFF"
    )
        port map (
      I0 => \converge_cnt[0]_i_7_n_0\,
      I1 => converge_cnt_reg(9),
      I2 => converge_cnt_reg(8),
      I3 => converge_cnt_reg(10),
      I4 => converge_cnt_reg(11),
      I5 => converge_cnt_reg(12),
      O => \converge_cnt[0]_i_4_n_0\
    );
\converge_cnt[0]_i_5\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"7FFFFFFF"
    )
        port map (
      I0 => converge_cnt_reg(19),
      I1 => converge_cnt_reg(18),
      I2 => converge_cnt_reg(16),
      I3 => converge_cnt_reg(15),
      I4 => converge_cnt_reg(17),
      O => \converge_cnt[0]_i_5_n_0\
    );
\converge_cnt[0]_i_6__0\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => converge_cnt_reg(0),
      O => \converge_cnt[0]_i_6__0_n_0\
    );
\converge_cnt[0]_i_7\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => converge_cnt_reg(4),
      I1 => converge_cnt_reg(5),
      I2 => converge_cnt_reg(7),
      I3 => converge_cnt_reg(6),
      I4 => converge_cnt_reg(3),
      O => \converge_cnt[0]_i_7_n_0\
    );
\converge_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[0]_i_3__0_n_7\,
      Q => converge_cnt_reg(0),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[0]_i_3__0\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \converge_cnt_reg[0]_i_3__0_n_0\,
      CO(2) => \converge_cnt_reg[0]_i_3__0_n_1\,
      CO(1) => \converge_cnt_reg[0]_i_3__0_n_2\,
      CO(0) => \converge_cnt_reg[0]_i_3__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0001",
      O(3) => \converge_cnt_reg[0]_i_3__0_n_4\,
      O(2) => \converge_cnt_reg[0]_i_3__0_n_5\,
      O(1) => \converge_cnt_reg[0]_i_3__0_n_6\,
      O(0) => \converge_cnt_reg[0]_i_3__0_n_7\,
      S(3 downto 1) => converge_cnt_reg(3 downto 1),
      S(0) => \converge_cnt[0]_i_6__0_n_0\
    );
\converge_cnt_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[8]_i_1__0_n_5\,
      Q => converge_cnt_reg(10),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[8]_i_1__0_n_4\,
      Q => converge_cnt_reg(11),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[12]_i_1__0_n_7\,
      Q => converge_cnt_reg(12),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[12]_i_1__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[8]_i_1__0_n_0\,
      CO(3) => \converge_cnt_reg[12]_i_1__0_n_0\,
      CO(2) => \converge_cnt_reg[12]_i_1__0_n_1\,
      CO(1) => \converge_cnt_reg[12]_i_1__0_n_2\,
      CO(0) => \converge_cnt_reg[12]_i_1__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \converge_cnt_reg[12]_i_1__0_n_4\,
      O(2) => \converge_cnt_reg[12]_i_1__0_n_5\,
      O(1) => \converge_cnt_reg[12]_i_1__0_n_6\,
      O(0) => \converge_cnt_reg[12]_i_1__0_n_7\,
      S(3 downto 0) => converge_cnt_reg(15 downto 12)
    );
\converge_cnt_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[12]_i_1__0_n_6\,
      Q => converge_cnt_reg(13),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[12]_i_1__0_n_5\,
      Q => converge_cnt_reg(14),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[12]_i_1__0_n_4\,
      Q => converge_cnt_reg(15),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[16]_i_1__0_n_7\,
      Q => converge_cnt_reg(16),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[16]_i_1__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[12]_i_1__0_n_0\,
      CO(3) => \converge_cnt_reg[16]_i_1__0_n_0\,
      CO(2) => \converge_cnt_reg[16]_i_1__0_n_1\,
      CO(1) => \converge_cnt_reg[16]_i_1__0_n_2\,
      CO(0) => \converge_cnt_reg[16]_i_1__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \converge_cnt_reg[16]_i_1__0_n_4\,
      O(2) => \converge_cnt_reg[16]_i_1__0_n_5\,
      O(1) => \converge_cnt_reg[16]_i_1__0_n_6\,
      O(0) => \converge_cnt_reg[16]_i_1__0_n_7\,
      S(3 downto 0) => converge_cnt_reg(19 downto 16)
    );
\converge_cnt_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[16]_i_1__0_n_6\,
      Q => converge_cnt_reg(17),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[16]_i_1__0_n_5\,
      Q => converge_cnt_reg(18),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[16]_i_1__0_n_4\,
      Q => converge_cnt_reg(19),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[0]_i_3__0_n_6\,
      Q => converge_cnt_reg(1),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[20]_i_1__0_n_7\,
      Q => converge_cnt_reg(20),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[20]_i_1__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[16]_i_1__0_n_0\,
      CO(3 downto 1) => \NLW_converge_cnt_reg[20]_i_1__0_CO_UNCONNECTED\(3 downto 1),
      CO(0) => \converge_cnt_reg[20]_i_1__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 2) => \NLW_converge_cnt_reg[20]_i_1__0_O_UNCONNECTED\(3 downto 2),
      O(1) => \converge_cnt_reg[20]_i_1__0_n_6\,
      O(0) => \converge_cnt_reg[20]_i_1__0_n_7\,
      S(3 downto 2) => B"00",
      S(1 downto 0) => converge_cnt_reg(21 downto 20)
    );
\converge_cnt_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[20]_i_1__0_n_6\,
      Q => converge_cnt_reg(21),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[0]_i_3__0_n_5\,
      Q => converge_cnt_reg(2),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[0]_i_3__0_n_4\,
      Q => converge_cnt_reg(3),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[4]_i_1__0_n_7\,
      Q => converge_cnt_reg(4),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[4]_i_1__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[0]_i_3__0_n_0\,
      CO(3) => \converge_cnt_reg[4]_i_1__0_n_0\,
      CO(2) => \converge_cnt_reg[4]_i_1__0_n_1\,
      CO(1) => \converge_cnt_reg[4]_i_1__0_n_2\,
      CO(0) => \converge_cnt_reg[4]_i_1__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \converge_cnt_reg[4]_i_1__0_n_4\,
      O(2) => \converge_cnt_reg[4]_i_1__0_n_5\,
      O(1) => \converge_cnt_reg[4]_i_1__0_n_6\,
      O(0) => \converge_cnt_reg[4]_i_1__0_n_7\,
      S(3 downto 0) => converge_cnt_reg(7 downto 4)
    );
\converge_cnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[4]_i_1__0_n_6\,
      Q => converge_cnt_reg(5),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[4]_i_1__0_n_5\,
      Q => converge_cnt_reg(6),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[4]_i_1__0_n_4\,
      Q => converge_cnt_reg(7),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[8]_i_1__0_n_7\,
      Q => converge_cnt_reg(8),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_cnt_reg[8]_i_1__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[4]_i_1__0_n_0\,
      CO(3) => \converge_cnt_reg[8]_i_1__0_n_0\,
      CO(2) => \converge_cnt_reg[8]_i_1__0_n_1\,
      CO(1) => \converge_cnt_reg[8]_i_1__0_n_2\,
      CO(0) => \converge_cnt_reg[8]_i_1__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3) => \converge_cnt_reg[8]_i_1__0_n_4\,
      O(2) => \converge_cnt_reg[8]_i_1__0_n_5\,
      O(1) => \converge_cnt_reg[8]_i_1__0_n_6\,
      O(0) => \converge_cnt_reg[8]_i_1__0_n_7\,
      S(3 downto 0) => converge_cnt_reg(11 downto 8)
    );
\converge_cnt_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => sel,
      D => \converge_cnt_reg[8]_i_1__0_n_6\,
      Q => converge_cnt_reg(9),
      R => \converge_cnt[0]_i_1__0_n_0\
    );
\converge_gen3_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"C8"
    )
        port map (
      I0 => rxeq_adapt_done_reg2,
      I1 => rate_gen3_reg2,
      I2 => \^converge_gen3_reg_0\,
      O => \converge_gen3_i_1__0_n_0\
    );
converge_gen3_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => \converge_gen3_i_1__0_n_0\,
      Q => \^converge_gen3_reg_0\,
      R => resetovrd_start_reg2_reg_0
    );
gt_rx_phy_status_q_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFE0FF"
    )
        port map (
      I0 => rate_idle_reg2,
      I1 => rate_rxsync_reg2,
      I2 => gt_rx_phy_status_q_reg(0),
      I3 => rst_idle_reg2,
      I4 => rate_done_reg2,
      O => PIPE_PHYSTATUS(0)
    );
\gt_rxvalid_q_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"BBFBFFFFFFFFFFFF"
    )
        port map (
      I0 => gt_rxvalid_q_i_5_n_0,
      I1 => gt_rxvalid_1,
      I2 => PIPE_RXELECIDLE(0),
      I3 => gt_rxvalid_q_reg_0,
      I4 => rst_idle_reg2,
      I5 => rate_idle_reg2,
      O => gt_rxvalid_q_reg
    );
gt_rxvalid_q_i_5: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => rxvalid_cnt_reg(2),
      I1 => rxvalid_cnt_reg(0),
      I2 => rxvalid_cnt_reg(1),
      I3 => rxvalid_cnt_reg(3),
      O => gt_rxvalid_q_i_5_n_0
    );
\gtx_channel.gtxe2_channel_i_i_51\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFB"
    )
        port map (
      I0 => \gtx_channel.gtxe2_channel_i_i_57_n_0\,
      I1 => converge_cnt_reg(11),
      I2 => converge_cnt_reg(2),
      I3 => converge_cnt_reg(20),
      I4 => \gtx_channel.gtxe2_channel_i_i_58_n_0\,
      I5 => \gtx_channel.gtxe2_channel_i_i_59_n_0\,
      O => \converge_cnt_reg[11]_0\
    );
\gtx_channel.gtxe2_channel_i_i_52\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000004"
    )
        port map (
      I0 => converge_cnt_reg(0),
      I1 => converge_cnt_reg(10),
      I2 => converge_cnt_reg(1),
      I3 => converge_cnt_reg(14),
      I4 => \gtx_channel.gtxe2_channel_i_i_60_n_0\,
      O => \converge_cnt_reg[0]_0\
    );
\gtx_channel.gtxe2_channel_i_i_57\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => converge_cnt_reg(13),
      I1 => converge_cnt_reg(3),
      I2 => converge_cnt_reg(21),
      I3 => converge_cnt_reg(17),
      O => \gtx_channel.gtxe2_channel_i_i_57_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_58\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7FFF"
    )
        port map (
      I0 => converge_cnt_reg(15),
      I1 => converge_cnt_reg(16),
      I2 => converge_cnt_reg(18),
      I3 => converge_cnt_reg(19),
      O => \gtx_channel.gtxe2_channel_i_i_58_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_59\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => converge_cnt_reg(7),
      I1 => converge_cnt_reg(5),
      I2 => converge_cnt_reg(4),
      O => \gtx_channel.gtxe2_channel_i_i_59_n_0\
    );
\gtx_channel.gtxe2_channel_i_i_60\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF7"
    )
        port map (
      I0 => converge_cnt_reg(9),
      I1 => converge_cnt_reg(8),
      I2 => converge_cnt_reg(6),
      I3 => converge_cnt_reg(12),
      O => \gtx_channel.gtxe2_channel_i_i_60_n_0\
    );
\oobclk_div.oobclk_cnt[0]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => oobclk_cnt(0),
      O => \p_1_in__0\(0)
    );
\oobclk_div.oobclk_cnt[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"6"
    )
        port map (
      I0 => oobclk_cnt(0),
      I1 => oobclk_cnt(1),
      O => \p_1_in__0\(1)
    );
\oobclk_div.oobclk_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => \p_1_in__0\(0),
      Q => oobclk_cnt(0),
      R => resetovrd_start_reg2_reg_0
    );
\oobclk_div.oobclk_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => \p_1_in__0\(1),
      Q => oobclk_cnt(1),
      R => resetovrd_start_reg2_reg_0
    );
\oobclk_div.oobclk_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"B8"
    )
        port map (
      I0 => oobclk_cnt(1),
      I1 => pclk_sel_reg2,
      I2 => oobclk_cnt(0),
      O => \oobclk_div.oobclk_i_1__0_n_0\
    );
\oobclk_div.oobclk_reg\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => \oobclk_div.oobclk_i_1__0_n_0\,
      Q => CLKRSVD(0),
      R => resetovrd_start_reg2_reg_0
    );
pclk_sel_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => pclk_sel_reg1_reg_0(0),
      Q => pclk_sel_reg1,
      R => resetovrd_start_reg2_reg_0
    );
pclk_sel_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => pclk_sel_reg1,
      Q => pclk_sel_reg2,
      R => resetovrd_start_reg2_reg_0
    );
phy_rdy_n_int_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => rst_idle_reg2,
      I1 => reg_clock_locked,
      I2 => phy_rdy_n_int_reg,
      O => rst_idle_reg2_reg_0
    );
rate_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => rate_done_reg1_reg_0(1),
      Q => rate_done_reg1,
      R => SR(0)
    );
rate_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => rate_done_reg1,
      Q => rate_done_reg2,
      R => SR(0)
    );
rate_gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => rate_gen3_1,
      Q => rate_gen3_reg1,
      R => SR(0)
    );
rate_gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => rate_gen3_reg1,
      Q => rate_gen3_reg2,
      R => SR(0)
    );
rate_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => rate_done_reg1_reg_0(0),
      Q => rate_idle_reg1,
      R => SR(0)
    );
rate_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => rate_idle_reg1,
      Q => rate_idle_reg2,
      R => SR(0)
    );
rate_rxsync_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => '0',
      Q => rate_rxsync_reg1,
      R => SR(0)
    );
rate_rxsync_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => rate_rxsync_reg1,
      Q => rate_rxsync_reg2,
      R => SR(0)
    );
\resetdone_reg1[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => rxresetdone_reg2,
      I1 => txresetdone_reg2,
      O => D(0)
    );
resetovrd_start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => '0',
      Q => resetovrd_start_reg1,
      R => resetovrd_start_reg2_reg_0
    );
resetovrd_start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => resetovrd_start_reg1,
      Q => resetovrd_start_reg2,
      R => resetovrd_start_reg2_reg_0
    );
rst_idle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => Q(0),
      Q => rst_idle_reg1,
      R => SR(0)
    );
rst_idle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => rst_idle_reg1,
      Q => rst_idle_reg2,
      R => SR(0)
    );
\rxcdrlock_cnt[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8A0A0A0A"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => rxcdrlock_cnt_reg(3),
      I2 => rxcdrlock_cnt_reg(0),
      I3 => rxcdrlock_cnt_reg(1),
      I4 => rxcdrlock_cnt_reg(2),
      O => \p_0_in__4\(0)
    );
\rxcdrlock_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8282828"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => rxcdrlock_cnt_reg(0),
      I2 => rxcdrlock_cnt_reg(1),
      I3 => rxcdrlock_cnt_reg(3),
      I4 => rxcdrlock_cnt_reg(2),
      O => \p_0_in__4\(1)
    );
\rxcdrlock_cnt[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"BCCC0000"
    )
        port map (
      I0 => rxcdrlock_cnt_reg(3),
      I1 => rxcdrlock_cnt_reg(2),
      I2 => rxcdrlock_cnt_reg(1),
      I3 => rxcdrlock_cnt_reg(0),
      I4 => rxcdrlock_reg2,
      O => \p_0_in__4\(2)
    );
\rxcdrlock_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAAA8000"
    )
        port map (
      I0 => rxcdrlock_reg2,
      I1 => rxcdrlock_cnt_reg(2),
      I2 => rxcdrlock_cnt_reg(1),
      I3 => rxcdrlock_cnt_reg(0),
      I4 => rxcdrlock_cnt_reg(3),
      O => \p_0_in__4\(3)
    );
\rxcdrlock_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => \p_0_in__4\(0),
      Q => rxcdrlock_cnt_reg(0),
      R => resetovrd_start_reg2_reg_0
    );
\rxcdrlock_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => \p_0_in__4\(1),
      Q => rxcdrlock_cnt_reg(1),
      R => resetovrd_start_reg2_reg_0
    );
\rxcdrlock_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => \p_0_in__4\(2),
      Q => rxcdrlock_cnt_reg(2),
      R => resetovrd_start_reg2_reg_0
    );
\rxcdrlock_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => \p_0_in__4\(3),
      Q => rxcdrlock_cnt_reg(3),
      R => resetovrd_start_reg2_reg_0
    );
\rxcdrlock_reg1[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"80000000"
    )
        port map (
      I0 => gt_rxcdrlock_1,
      I1 => rxcdrlock_cnt_reg(2),
      I2 => rxcdrlock_cnt_reg(1),
      I3 => rxcdrlock_cnt_reg(0),
      I4 => rxcdrlock_cnt_reg(3),
      O => \rxcdrlock_cnt_reg[2]_0\(0)
    );
rxcdrlock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => gt_rxcdrlock_1,
      Q => rxcdrlock_reg1,
      R => resetovrd_start_reg2_reg_0
    );
rxcdrlock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => rxcdrlock_reg1,
      Q => rxcdrlock_reg2,
      R => resetovrd_start_reg2_reg_0
    );
rxeq_adapt_done_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => rxeq_adapt_done_reg1_reg_0,
      Q => rxeq_adapt_done_reg1,
      R => resetovrd_start_reg2_reg_0
    );
rxeq_adapt_done_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => rxeq_adapt_done_reg1,
      Q => rxeq_adapt_done_reg2,
      R => resetovrd_start_reg2_reg_0
    );
rxresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => gt_rxresetdone_1,
      Q => rxresetdone_reg1,
      R => resetovrd_start_reg2_reg_0
    );
rxresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => rxresetdone_reg1,
      Q => rxresetdone_reg2,
      R => resetovrd_start_reg2_reg_0
    );
rxstatus_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => pipe_rxstatus(0),
      Q => rxstatus_reg1,
      R => SR(0)
    );
rxstatus_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => rxstatus_reg1,
      Q => rxstatus_reg2,
      R => SR(0)
    );
\rxvalid_cnt[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"8080000000FF0000"
    )
        port map (
      I0 => rxvalid_cnt_reg(2),
      I1 => rxvalid_cnt_reg(1),
      I2 => rxvalid_cnt_reg(3),
      I3 => rxstatus_reg2,
      I4 => rxvalid_reg2,
      I5 => rxvalid_cnt_reg(0),
      O => \p_0_in__5\(0)
    );
\rxvalid_cnt[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80000000E6660000"
    )
        port map (
      I0 => rxvalid_cnt_reg(0),
      I1 => rxvalid_cnt_reg(1),
      I2 => rxvalid_cnt_reg(3),
      I3 => rxvalid_cnt_reg(2),
      I4 => rxvalid_reg2,
      I5 => rxstatus_reg2,
      O => \p_0_in__5\(1)
    );
\rxvalid_cnt[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"80000000EA6A0000"
    )
        port map (
      I0 => rxvalid_cnt_reg(2),
      I1 => rxvalid_cnt_reg(1),
      I2 => rxvalid_cnt_reg(0),
      I3 => rxvalid_cnt_reg(3),
      I4 => rxvalid_reg2,
      I5 => rxstatus_reg2,
      O => \p_0_in__5\(2)
    );
\rxvalid_cnt[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"D555400000000000"
    )
        port map (
      I0 => rxstatus_reg2,
      I1 => rxvalid_cnt_reg(2),
      I2 => rxvalid_cnt_reg(0),
      I3 => rxvalid_cnt_reg(1),
      I4 => rxvalid_cnt_reg(3),
      I5 => rxvalid_reg2,
      O => \p_0_in__5\(3)
    );
\rxvalid_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => \p_0_in__5\(0),
      Q => rxvalid_cnt_reg(0),
      R => SR(0)
    );
\rxvalid_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => \p_0_in__5\(1),
      Q => rxvalid_cnt_reg(1),
      R => SR(0)
    );
\rxvalid_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => \p_0_in__5\(2),
      Q => rxvalid_cnt_reg(2),
      R => SR(0)
    );
\rxvalid_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => \p_0_in__5\(3),
      Q => rxvalid_cnt_reg(3),
      R => SR(0)
    );
rxvalid_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => gt_rxvalid_1,
      Q => rxvalid_reg1,
      R => SR(0)
    );
rxvalid_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => rxvalid_reg1,
      Q => rxvalid_reg2,
      R => SR(0)
    );
txcompliance_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => pipe_tx1_compliance,
      Q => txcompliance_reg1,
      R => resetovrd_start_reg2_reg_0
    );
txcompliance_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => txcompliance_reg1,
      Q => txcompliance_reg2,
      R => resetovrd_start_reg2_reg_0
    );
txelecidle_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => pipe_tx1_elec_idle,
      Q => txelecidle_reg1,
      R => resetovrd_start_reg2_reg_0
    );
txelecidle_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => txelecidle_reg1,
      Q => txelecidle_reg2,
      R => resetovrd_start_reg2_reg_0
    );
txphaligndone_reg1_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8F8F8F8F8000000"
    )
        port map (
      I0 => txelecidle_reg2,
      I1 => txcompliance_reg2,
      I2 => pipe_txphaligndone(1),
      I3 => txphinitdone_reg1_reg,
      I4 => txphinitdone_reg1_reg_0,
      I5 => pipe_txphaligndone(0),
      O => SYNC_TXPHALIGNDONE
    );
txphinitdone_reg1_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F8F8F8F8F8000000"
    )
        port map (
      I0 => txelecidle_reg2,
      I1 => txcompliance_reg2,
      I2 => pipe_txphinitdone(1),
      I3 => txphinitdone_reg1_reg,
      I4 => txphinitdone_reg1_reg_0,
      I5 => pipe_txphinitdone(0),
      O => SYNC_TXPHINITDONE
    );
txresetdone_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => gt_txresetdone_1,
      Q => txresetdone_reg1,
      R => resetovrd_start_reg2_reg_0
    );
txresetdone_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => resetovrd_start_reg2_reg_1,
      CE => '1',
      D => txresetdone_reg1,
      Q => txresetdone_reg2,
      R => resetovrd_start_reg2_reg_0
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_qpll_drp is
  port (
    QPLL_DRP_DONE : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \di_reg[15]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    qpll_drp_en : out STD_LOGIC;
    qpll_drp_we : out STD_LOGIC;
    \out\ : in STD_LOGIC;
    QRST_DRP_START : in STD_LOGIC;
    CLK : in STD_LOGIC;
    qpll_drp_rdy : in STD_LOGIC;
    QPLL_QPLLLOCK : in STD_LOGIC;
    QPLL_DRP_GEN3 : in STD_LOGIC;
    D : in STD_LOGIC_VECTOR ( 15 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_qpll_drp : entity is "spec7_pcie_7x_0_qpll_drp";
end spec7_pcie_7x_0_spec7_pcie_7x_0_qpll_drp;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_qpll_drp is
  signal \addr[0]_i_1_n_0\ : STD_LOGIC;
  signal \addr[1]_i_1_n_0\ : STD_LOGIC;
  signal \addr[2]_i_1_n_0\ : STD_LOGIC;
  signal \addr[5]_i_1_n_0\ : STD_LOGIC;
  signal \addr[7]_i_1_n_0\ : STD_LOGIC;
  signal \crscode_reg_n_0_[0]\ : STD_LOGIC;
  signal \crscode_reg_n_0_[1]\ : STD_LOGIC;
  signal \crscode_reg_n_0_[2]\ : STD_LOGIC;
  signal \crscode_reg_n_0_[3]\ : STD_LOGIC;
  signal \crscode_reg_n_0_[4]\ : STD_LOGIC;
  signal \crscode_reg_n_0_[5]\ : STD_LOGIC;
  signal di : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \di[11]_i_2_n_0\ : STD_LOGIC;
  signal \di[12]_i_2_n_0\ : STD_LOGIC;
  signal \di[13]_i_2_n_0\ : STD_LOGIC;
  signal \di[14]_i_2_n_0\ : STD_LOGIC;
  signal \di[15]_i_2_n_0\ : STD_LOGIC;
  signal do_reg1 : STD_LOGIC_VECTOR ( 15 downto 0 );
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of do_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of do_reg1 : signal is "true";
  signal do_reg2 : STD_LOGIC_VECTOR ( 15 downto 0 );
  attribute SHIFT_EXTRACT of do_reg2 : signal is "NO";
  attribute async_reg of do_reg2 : signal is "true";
  signal done : STD_LOGIC;
  signal \fsm[0]_i_2_n_0\ : STD_LOGIC;
  signal \fsm[1]_i_2_n_0\ : STD_LOGIC;
  signal \fsm_inferred__1/i___0_n_0\ : STD_LOGIC;
  signal \fsm_inferred__1/i___1_n_0\ : STD_LOGIC;
  signal \fsm_inferred__1/i__n_0\ : STD_LOGIC;
  signal \fsm_reg_n_0_[0]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[1]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[2]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[3]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[4]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[5]\ : STD_LOGIC;
  signal \fsm_reg_n_0_[6]\ : STD_LOGIC;
  signal gen3_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of gen3_reg1 : signal is "NO";
  attribute async_reg of gen3_reg1 : signal is "true";
  signal gen3_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of gen3_reg2 : signal is "NO";
  attribute async_reg of gen3_reg2 : signal is "true";
  signal \gtx_common.gtxe2_common_i_i_3_n_0\ : STD_LOGIC;
  signal \gtx_common.gtxe2_common_i_i_4_n_0\ : STD_LOGIC;
  signal index : STD_LOGIC;
  signal \index[0]_i_1_n_0\ : STD_LOGIC;
  signal \index[1]_i_1_n_0\ : STD_LOGIC;
  signal \index[2]_i_1_n_0\ : STD_LOGIC;
  signal \index[2]_i_2_n_0\ : STD_LOGIC;
  signal \index[2]_i_4_n_0\ : STD_LOGIC;
  signal \index_reg_n_0_[0]\ : STD_LOGIC;
  signal \index_reg_n_0_[1]\ : STD_LOGIC;
  signal \index_reg_n_0_[2]\ : STD_LOGIC;
  signal load_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \load_cnt[0]_i_1_n_0\ : STD_LOGIC;
  signal \load_cnt[1]_i_1_n_0\ : STD_LOGIC;
  signal \load_cnt[1]_i_2_n_0\ : STD_LOGIC;
  signal ovrd_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of ovrd_reg1 : signal is "NO";
  attribute async_reg of ovrd_reg1 : signal is "true";
  signal ovrd_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of ovrd_reg2 : signal is "NO";
  attribute async_reg of ovrd_reg2 : signal is "true";
  signal \p_0_in__0\ : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal p_1_in : STD_LOGIC;
  signal p_2_in : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal qplllock_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of qplllock_reg1 : signal is "NO";
  attribute async_reg of qplllock_reg1 : signal is "true";
  signal qplllock_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of qplllock_reg2 : signal is "NO";
  attribute async_reg of qplllock_reg2 : signal is "true";
  signal rdy_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rdy_reg1 : signal is "NO";
  attribute async_reg of rdy_reg1 : signal is "true";
  signal rdy_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rdy_reg2 : signal is "NO";
  attribute async_reg of rdy_reg2 : signal is "true";
  signal start_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of start_reg1 : signal is "NO";
  attribute async_reg of start_reg1 : signal is "true";
  signal start_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of start_reg2 : signal is "NO";
  attribute async_reg of start_reg2 : signal is "true";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \addr[0]_i_1\ : label is "soft_lutpair32";
  attribute SOFT_HLUTNM of \addr[1]_i_1\ : label is "soft_lutpair36";
  attribute SOFT_HLUTNM of \addr[2]_i_1\ : label is "soft_lutpair38";
  attribute SOFT_HLUTNM of \addr[7]_i_1\ : label is "soft_lutpair36";
  attribute SOFT_HLUTNM of \di[12]_i_2\ : label is "soft_lutpair37";
  attribute SOFT_HLUTNM of \di[13]_i_2\ : label is "soft_lutpair37";
  attribute SOFT_HLUTNM of \di[14]_i_2\ : label is "soft_lutpair33";
  attribute SOFT_HLUTNM of \di[15]_i_2\ : label is "soft_lutpair33";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \do_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \do_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[10]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[10]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[11]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[11]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[12]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[12]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[13]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[13]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[14]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[14]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[15]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[15]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[6]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[6]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[7]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[7]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[8]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[8]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg1_reg[9]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg1_reg[9]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[10]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[10]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[11]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[11]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[12]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[12]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[13]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[13]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[14]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[14]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[15]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[15]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[6]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[6]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[7]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[7]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[8]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[8]\ : label is "NO";
  attribute ASYNC_REG_boolean of \do_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \do_reg2_reg[9]\ : label is "yes";
  attribute SHIFT_EXTRACT of \do_reg2_reg[9]\ : label is "NO";
  attribute SOFT_HLUTNM of \fsm[0]_i_2\ : label is "soft_lutpair38";
  attribute SOFT_HLUTNM of \fsm[1]_i_1\ : label is "soft_lutpair30";
  attribute SOFT_HLUTNM of \fsm[2]_i_1\ : label is "soft_lutpair30";
  attribute SOFT_HLUTNM of \fsm_inferred__1/i_\ : label is "soft_lutpair35";
  attribute SOFT_HLUTNM of \fsm_inferred__1/i___0\ : label is "soft_lutpair35";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \fsm_reg[0]\ : label is "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000";
  attribute FSM_ENCODED_STATES of \fsm_reg[1]\ : label is "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000";
  attribute FSM_ENCODED_STATES of \fsm_reg[2]\ : label is "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000";
  attribute FSM_ENCODED_STATES of \fsm_reg[3]\ : label is "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000";
  attribute FSM_ENCODED_STATES of \fsm_reg[4]\ : label is "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000";
  attribute FSM_ENCODED_STATES of \fsm_reg[5]\ : label is "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000";
  attribute FSM_ENCODED_STATES of \fsm_reg[6]\ : label is "FSM_READ:000000100,FSM_QPLLRESET:010000000,FSM_LOAD:000000010,FSM_DONE:001000000,FSM_WRITE:000010000,FSM_IDLE:000000001,FSM_WRDY:000100000,FSM_RRDY:000001000,FSM_QPLLLOCK:100000000";
  attribute ASYNC_REG_boolean of gen3_reg1_reg : label is std.standard.true;
  attribute KEEP of gen3_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of gen3_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of gen3_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of gen3_reg2_reg : label is "NO";
  attribute SOFT_HLUTNM of \gtx_common.gtxe2_common_i_i_2\ : label is "soft_lutpair28";
  attribute SOFT_HLUTNM of \gtx_common.gtxe2_common_i_i_4\ : label is "soft_lutpair34";
  attribute SOFT_HLUTNM of \index[0]_i_1\ : label is "soft_lutpair31";
  attribute SOFT_HLUTNM of \index[1]_i_1\ : label is "soft_lutpair32";
  attribute SOFT_HLUTNM of \index[2]_i_1\ : label is "soft_lutpair31";
  attribute SOFT_HLUTNM of \index[2]_i_2\ : label is "soft_lutpair28";
  attribute SOFT_HLUTNM of \load_cnt[0]_i_1\ : label is "soft_lutpair29";
  attribute SOFT_HLUTNM of \load_cnt[1]_i_1\ : label is "soft_lutpair29";
  attribute SOFT_HLUTNM of \load_cnt[1]_i_2\ : label is "soft_lutpair34";
  attribute ASYNC_REG_boolean of ovrd_reg1_reg : label is std.standard.true;
  attribute KEEP of ovrd_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of ovrd_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of ovrd_reg2_reg : label is std.standard.true;
  attribute KEEP of ovrd_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of ovrd_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of qplllock_reg1_reg : label is std.standard.true;
  attribute KEEP of qplllock_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of qplllock_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of qplllock_reg2_reg : label is std.standard.true;
  attribute KEEP of qplllock_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of qplllock_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rdy_reg1_reg : label is std.standard.true;
  attribute KEEP of rdy_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rdy_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rdy_reg2_reg : label is std.standard.true;
  attribute KEEP of rdy_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rdy_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of start_reg1_reg : label is std.standard.true;
  attribute KEEP of start_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of start_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of start_reg2_reg : label is std.standard.true;
  attribute KEEP of start_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of start_reg2_reg : label is "NO";
begin
\addr[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"12"
    )
        port map (
      I0 => \index_reg_n_0_[1]\,
      I1 => \index_reg_n_0_[0]\,
      I2 => \index_reg_n_0_[2]\,
      O => \addr[0]_i_1_n_0\
    );
\addr[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"0D"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => \index_reg_n_0_[0]\,
      I2 => \index_reg_n_0_[1]\,
      O => \addr[1]_i_1_n_0\
    );
\addr[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"4D"
    )
        port map (
      I0 => \index_reg_n_0_[1]\,
      I1 => \index_reg_n_0_[2]\,
      I2 => \index_reg_n_0_[0]\,
      O => \addr[2]_i_1_n_0\
    );
\addr[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"7"
    )
        port map (
      I0 => \index_reg_n_0_[1]\,
      I1 => \index_reg_n_0_[0]\,
      O => \addr[5]_i_1_n_0\
    );
\addr[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \index_reg_n_0_[1]\,
      I1 => \index_reg_n_0_[0]\,
      I2 => \index_reg_n_0_[2]\,
      O => \addr[7]_i_1_n_0\
    );
\addr_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \addr[0]_i_1_n_0\,
      Q => Q(0),
      R => \out\
    );
\addr_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \addr[1]_i_1_n_0\,
      Q => Q(1),
      R => \out\
    );
\addr_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \addr[2]_i_1_n_0\,
      Q => Q(2),
      R => \out\
    );
\addr_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \addr[5]_i_1_n_0\,
      Q => Q(3),
      R => \out\
    );
\addr_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \addr[7]_i_1_n_0\,
      Q => Q(4),
      R => \out\
    );
\crscode[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => do_reg2(1),
      I1 => \index_reg_n_0_[2]\,
      O => p_2_in(0)
    );
\crscode[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => do_reg2(2),
      I1 => \index_reg_n_0_[2]\,
      O => p_2_in(1)
    );
\crscode[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => do_reg2(3),
      I1 => \index_reg_n_0_[2]\,
      O => p_2_in(2)
    );
\crscode[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => do_reg2(4),
      I1 => \index_reg_n_0_[2]\,
      O => p_2_in(3)
    );
\crscode[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => do_reg2(5),
      I1 => \index_reg_n_0_[2]\,
      O => p_2_in(4)
    );
\crscode[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"C080"
    )
        port map (
      I0 => ovrd_reg2,
      I1 => \index_reg_n_0_[0]\,
      I2 => \index_reg_n_0_[1]\,
      I3 => \index_reg_n_0_[2]\,
      O => p_1_in
    );
\crscode[5]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => do_reg2(6),
      I1 => \index_reg_n_0_[2]\,
      O => p_2_in(5)
    );
\crscode_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => p_1_in,
      D => p_2_in(0),
      Q => \crscode_reg_n_0_[0]\,
      R => \out\
    );
\crscode_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => p_1_in,
      D => p_2_in(1),
      Q => \crscode_reg_n_0_[1]\,
      R => \out\
    );
\crscode_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => p_1_in,
      D => p_2_in(2),
      Q => \crscode_reg_n_0_[2]\,
      R => \out\
    );
\crscode_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => p_1_in,
      D => p_2_in(3),
      Q => \crscode_reg_n_0_[3]\,
      R => \out\
    );
\crscode_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => p_1_in,
      D => p_2_in(4),
      Q => \crscode_reg_n_0_[4]\,
      R => \out\
    );
\crscode_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => p_1_in,
      D => p_2_in(5),
      Q => \crscode_reg_n_0_[5]\,
      R => \out\
    );
\di[0]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7E00"
    )
        port map (
      I0 => \index_reg_n_0_[0]\,
      I1 => \index_reg_n_0_[2]\,
      I2 => \index_reg_n_0_[1]\,
      I3 => do_reg2(0),
      O => di(0)
    );
\di[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"0CC5CCCC"
    )
        port map (
      I0 => \crscode_reg_n_0_[0]\,
      I1 => do_reg2(10),
      I2 => \index_reg_n_0_[1]\,
      I3 => \index_reg_n_0_[0]\,
      I4 => \index_reg_n_0_[2]\,
      O => di(10)
    );
\di[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAAAAAAAAAAAEBAA"
    )
        port map (
      I0 => \di[11]_i_2_n_0\,
      I1 => \crscode_reg_n_0_[0]\,
      I2 => \crscode_reg_n_0_[1]\,
      I3 => \index_reg_n_0_[2]\,
      I4 => \index_reg_n_0_[0]\,
      I5 => \index_reg_n_0_[1]\,
      O => di(11)
    );
\di[11]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"20FF2044"
    )
        port map (
      I0 => \index_reg_n_0_[0]\,
      I1 => \index_reg_n_0_[1]\,
      I2 => ovrd_reg2,
      I3 => \index_reg_n_0_[2]\,
      I4 => do_reg2(11),
      O => \di[11]_i_2_n_0\
    );
\di[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00AA0000AAAAC3AA"
    )
        port map (
      I0 => do_reg2(12),
      I1 => \di[12]_i_2_n_0\,
      I2 => \crscode_reg_n_0_[2]\,
      I3 => \index_reg_n_0_[2]\,
      I4 => \index_reg_n_0_[0]\,
      I5 => \index_reg_n_0_[1]\,
      O => di(12)
    );
\di[12]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \crscode_reg_n_0_[0]\,
      I1 => \crscode_reg_n_0_[1]\,
      O => \di[12]_i_2_n_0\
    );
\di[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F0F099F0F0FFF0"
    )
        port map (
      I0 => \crscode_reg_n_0_[3]\,
      I1 => \di[13]_i_2_n_0\,
      I2 => do_reg2(13),
      I3 => \index_reg_n_0_[1]\,
      I4 => \index_reg_n_0_[0]\,
      I5 => \index_reg_n_0_[2]\,
      O => di(13)
    );
\di[13]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \crscode_reg_n_0_[1]\,
      I1 => \crscode_reg_n_0_[0]\,
      I2 => \crscode_reg_n_0_[2]\,
      O => \di[13]_i_2_n_0\
    );
\di[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00F0F099F0F0FFF0"
    )
        port map (
      I0 => \crscode_reg_n_0_[4]\,
      I1 => \di[14]_i_2_n_0\,
      I2 => do_reg2(14),
      I3 => \index_reg_n_0_[1]\,
      I4 => \index_reg_n_0_[0]\,
      I5 => \index_reg_n_0_[2]\,
      O => di(14)
    );
\di[14]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \crscode_reg_n_0_[2]\,
      I1 => \crscode_reg_n_0_[0]\,
      I2 => \crscode_reg_n_0_[1]\,
      I3 => \crscode_reg_n_0_[3]\,
      O => \di[14]_i_2_n_0\
    );
\di[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0AACAAAA0AA3AAAA"
    )
        port map (
      I0 => do_reg2(15),
      I1 => \di[15]_i_2_n_0\,
      I2 => \index_reg_n_0_[1]\,
      I3 => \index_reg_n_0_[0]\,
      I4 => \index_reg_n_0_[2]\,
      I5 => \crscode_reg_n_0_[5]\,
      O => di(15)
    );
\di[15]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFFFFE"
    )
        port map (
      I0 => \crscode_reg_n_0_[3]\,
      I1 => \crscode_reg_n_0_[1]\,
      I2 => \crscode_reg_n_0_[0]\,
      I3 => \crscode_reg_n_0_[2]\,
      I4 => \crscode_reg_n_0_[4]\,
      O => \di[15]_i_2_n_0\
    );
\di[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7E00"
    )
        port map (
      I0 => \index_reg_n_0_[0]\,
      I1 => \index_reg_n_0_[2]\,
      I2 => \index_reg_n_0_[1]\,
      I3 => do_reg2(1),
      O => di(1)
    );
\di[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7E00"
    )
        port map (
      I0 => \index_reg_n_0_[0]\,
      I1 => \index_reg_n_0_[2]\,
      I2 => \index_reg_n_0_[1]\,
      I3 => do_reg2(2),
      O => di(2)
    );
\di[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7E00"
    )
        port map (
      I0 => \index_reg_n_0_[0]\,
      I1 => \index_reg_n_0_[2]\,
      I2 => \index_reg_n_0_[1]\,
      I3 => do_reg2(3),
      O => di(3)
    );
\di[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7E00"
    )
        port map (
      I0 => \index_reg_n_0_[0]\,
      I1 => \index_reg_n_0_[2]\,
      I2 => \index_reg_n_0_[1]\,
      I3 => do_reg2(4),
      O => di(4)
    );
\di[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2AAB"
    )
        port map (
      I0 => do_reg2(5),
      I1 => \index_reg_n_0_[1]\,
      I2 => \index_reg_n_0_[0]\,
      I3 => \index_reg_n_0_[2]\,
      O => di(5)
    );
\di[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2BA8"
    )
        port map (
      I0 => do_reg2(6),
      I1 => \index_reg_n_0_[1]\,
      I2 => \index_reg_n_0_[2]\,
      I3 => \index_reg_n_0_[0]\,
      O => di(6)
    );
\di[7]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7E00"
    )
        port map (
      I0 => \index_reg_n_0_[0]\,
      I1 => \index_reg_n_0_[2]\,
      I2 => \index_reg_n_0_[1]\,
      I3 => do_reg2(7),
      O => di(7)
    );
\di[8]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2AAB"
    )
        port map (
      I0 => do_reg2(8),
      I1 => \index_reg_n_0_[1]\,
      I2 => \index_reg_n_0_[0]\,
      I3 => \index_reg_n_0_[2]\,
      O => di(8)
    );
\di[9]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"7E00"
    )
        port map (
      I0 => \index_reg_n_0_[0]\,
      I1 => \index_reg_n_0_[2]\,
      I2 => \index_reg_n_0_[1]\,
      I3 => do_reg2(9),
      O => di(9)
    );
\di_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(0),
      Q => \di_reg[15]_0\(0),
      R => \out\
    );
\di_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(10),
      Q => \di_reg[15]_0\(10),
      R => \out\
    );
\di_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(11),
      Q => \di_reg[15]_0\(11),
      R => \out\
    );
\di_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(12),
      Q => \di_reg[15]_0\(12),
      R => \out\
    );
\di_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(13),
      Q => \di_reg[15]_0\(13),
      R => \out\
    );
\di_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(14),
      Q => \di_reg[15]_0\(14),
      R => \out\
    );
\di_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(15),
      Q => \di_reg[15]_0\(15),
      R => \out\
    );
\di_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(1),
      Q => \di_reg[15]_0\(1),
      R => \out\
    );
\di_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(2),
      Q => \di_reg[15]_0\(2),
      R => \out\
    );
\di_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(3),
      Q => \di_reg[15]_0\(3),
      R => \out\
    );
\di_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(4),
      Q => \di_reg[15]_0\(4),
      R => \out\
    );
\di_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(5),
      Q => \di_reg[15]_0\(5),
      R => \out\
    );
\di_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(6),
      Q => \di_reg[15]_0\(6),
      R => \out\
    );
\di_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(7),
      Q => \di_reg[15]_0\(7),
      R => \out\
    );
\di_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(8),
      Q => \di_reg[15]_0\(8),
      R => \out\
    );
\di_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => di(9),
      Q => \di_reg[15]_0\(9),
      R => \out\
    );
\do_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(0),
      Q => do_reg1(0),
      R => \out\
    );
\do_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(10),
      Q => do_reg1(10),
      R => \out\
    );
\do_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(11),
      Q => do_reg1(11),
      R => \out\
    );
\do_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(12),
      Q => do_reg1(12),
      R => \out\
    );
\do_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(13),
      Q => do_reg1(13),
      R => \out\
    );
\do_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(14),
      Q => do_reg1(14),
      R => \out\
    );
\do_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(15),
      Q => do_reg1(15),
      R => \out\
    );
\do_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(1),
      Q => do_reg1(1),
      R => \out\
    );
\do_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(2),
      Q => do_reg1(2),
      R => \out\
    );
\do_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(3),
      Q => do_reg1(3),
      R => \out\
    );
\do_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(4),
      Q => do_reg1(4),
      R => \out\
    );
\do_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(5),
      Q => do_reg1(5),
      R => \out\
    );
\do_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(6),
      Q => do_reg1(6),
      R => \out\
    );
\do_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(7),
      Q => do_reg1(7),
      R => \out\
    );
\do_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(8),
      Q => do_reg1(8),
      R => \out\
    );
\do_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => D(9),
      Q => do_reg1(9),
      R => \out\
    );
\do_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(0),
      Q => do_reg2(0),
      R => \out\
    );
\do_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(10),
      Q => do_reg2(10),
      R => \out\
    );
\do_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(11),
      Q => do_reg2(11),
      R => \out\
    );
\do_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(12),
      Q => do_reg2(12),
      R => \out\
    );
\do_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(13),
      Q => do_reg2(13),
      R => \out\
    );
\do_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(14),
      Q => do_reg2(14),
      R => \out\
    );
\do_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(15),
      Q => do_reg2(15),
      R => \out\
    );
\do_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(1),
      Q => do_reg2(1),
      R => \out\
    );
\do_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(2),
      Q => do_reg2(2),
      R => \out\
    );
\do_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(3),
      Q => do_reg2(3),
      R => \out\
    );
\do_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(4),
      Q => do_reg2(4),
      R => \out\
    );
\do_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(5),
      Q => do_reg2(5),
      R => \out\
    );
\do_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(6),
      Q => do_reg2(6),
      R => \out\
    );
\do_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(7),
      Q => do_reg2(7),
      R => \out\
    );
\do_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(8),
      Q => do_reg2(8),
      R => \out\
    );
\do_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => do_reg1(9),
      Q => do_reg2(9),
      R => \out\
    );
done_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000010"
    )
        port map (
      I0 => \fsm_reg_n_0_[6]\,
      I1 => start_reg2,
      I2 => \fsm_reg_n_0_[0]\,
      I3 => \fsm_reg_n_0_[1]\,
      I4 => \fsm_reg_n_0_[4]\,
      I5 => \gtx_common.gtxe2_common_i_i_4_n_0\,
      O => done
    );
done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => done,
      Q => QPLL_DRP_DONE,
      R => \out\
    );
\fsm[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"5DFF5D5D5D5D5D5D"
    )
        port map (
      I0 => \fsm_inferred__1/i___1_n_0\,
      I1 => \fsm_reg_n_0_[0]\,
      I2 => start_reg2,
      I3 => \fsm[0]_i_2_n_0\,
      I4 => \index_reg_n_0_[1]\,
      I5 => \fsm_reg_n_0_[6]\,
      O => \p_0_in__0\(0)
    );
\fsm[0]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \index_reg_n_0_[0]\,
      I1 => \index_reg_n_0_[2]\,
      O => \fsm[0]_i_2_n_0\
    );
\fsm[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF7000"
    )
        port map (
      I0 => load_cnt(0),
      I1 => load_cnt(1),
      I2 => \fsm_inferred__1/i___1_n_0\,
      I3 => \fsm_reg_n_0_[1]\,
      I4 => \fsm[1]_i_2_n_0\,
      O => \p_0_in__0\(1)
    );
\fsm[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00B000B000B000"
    )
        port map (
      I0 => \fsm[0]_i_2_n_0\,
      I1 => \index_reg_n_0_[1]\,
      I2 => \fsm_reg_n_0_[6]\,
      I3 => \fsm_inferred__1/i___1_n_0\,
      I4 => \fsm_reg_n_0_[0]\,
      I5 => start_reg2,
      O => \fsm[1]_i_2_n_0\
    );
\fsm[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8000"
    )
        port map (
      I0 => \fsm_reg_n_0_[1]\,
      I1 => \fsm_inferred__1/i___1_n_0\,
      I2 => load_cnt(1),
      I3 => load_cnt(0),
      O => \p_0_in__0\(2)
    );
\fsm[3]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88C8"
    )
        port map (
      I0 => \fsm_reg_n_0_[2]\,
      I1 => \fsm_inferred__1/i___1_n_0\,
      I2 => \fsm_reg_n_0_[3]\,
      I3 => rdy_reg2,
      O => \p_0_in__0\(3)
    );
\fsm[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => rdy_reg2,
      I1 => \fsm_reg_n_0_[3]\,
      I2 => \fsm_inferred__1/i___1_n_0\,
      O => \p_0_in__0\(4)
    );
\fsm[5]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"88C8"
    )
        port map (
      I0 => \fsm_reg_n_0_[4]\,
      I1 => \fsm_inferred__1/i___1_n_0\,
      I2 => \fsm_reg_n_0_[5]\,
      I3 => rdy_reg2,
      O => \p_0_in__0\(5)
    );
\fsm[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"80"
    )
        port map (
      I0 => rdy_reg2,
      I1 => \fsm_reg_n_0_[5]\,
      I2 => \fsm_inferred__1/i___1_n_0\,
      O => \p_0_in__0\(6)
    );
\fsm_inferred__1/i_\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0116"
    )
        port map (
      I0 => \fsm_reg_n_0_[0]\,
      I1 => \fsm_reg_n_0_[1]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[3]\,
      O => \fsm_inferred__1/i__n_0\
    );
\fsm_inferred__1/i___0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FEE8"
    )
        port map (
      I0 => \fsm_reg_n_0_[0]\,
      I1 => \fsm_reg_n_0_[1]\,
      I2 => \fsm_reg_n_0_[2]\,
      I3 => \fsm_reg_n_0_[3]\,
      O => \fsm_inferred__1/i___0_n_0\
    );
\fsm_inferred__1/i___1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000116"
    )
        port map (
      I0 => \fsm_reg_n_0_[4]\,
      I1 => \fsm_reg_n_0_[5]\,
      I2 => \fsm_reg_n_0_[6]\,
      I3 => \fsm_inferred__1/i__n_0\,
      I4 => \fsm_inferred__1/i___0_n_0\,
      O => \fsm_inferred__1/i___1_n_0\
    );
\fsm_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(0),
      Q => \fsm_reg_n_0_[0]\,
      S => \out\
    );
\fsm_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(1),
      Q => \fsm_reg_n_0_[1]\,
      R => \out\
    );
\fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(2),
      Q => \fsm_reg_n_0_[2]\,
      R => \out\
    );
\fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(3),
      Q => \fsm_reg_n_0_[3]\,
      R => \out\
    );
\fsm_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(4),
      Q => \fsm_reg_n_0_[4]\,
      R => \out\
    );
\fsm_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(5),
      Q => \fsm_reg_n_0_[5]\,
      R => \out\
    );
\fsm_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \p_0_in__0\(6),
      Q => \fsm_reg_n_0_[6]\,
      R => \out\
    );
gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => QPLL_DRP_GEN3,
      Q => gen3_reg1,
      R => \out\
    );
gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => gen3_reg1,
      Q => gen3_reg2,
      R => \out\
    );
\gtx_common.gtxe2_common_i_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000010100"
    )
        port map (
      I0 => \fsm_reg_n_0_[1]\,
      I1 => \fsm_reg_n_0_[0]\,
      I2 => \fsm_reg_n_0_[6]\,
      I3 => \fsm_reg_n_0_[4]\,
      I4 => \fsm_reg_n_0_[2]\,
      I5 => \gtx_common.gtxe2_common_i_i_3_n_0\,
      O => qpll_drp_en
    );
\gtx_common.gtxe2_common_i_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000010"
    )
        port map (
      I0 => \fsm_reg_n_0_[0]\,
      I1 => \fsm_reg_n_0_[6]\,
      I2 => \fsm_reg_n_0_[4]\,
      I3 => \fsm_reg_n_0_[1]\,
      I4 => \gtx_common.gtxe2_common_i_i_4_n_0\,
      O => qpll_drp_we
    );
\gtx_common.gtxe2_common_i_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \fsm_reg_n_0_[3]\,
      I1 => \fsm_reg_n_0_[5]\,
      O => \gtx_common.gtxe2_common_i_i_3_n_0\
    );
\gtx_common.gtxe2_common_i_i_4\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"FE"
    )
        port map (
      I0 => \fsm_reg_n_0_[5]\,
      I1 => \fsm_reg_n_0_[3]\,
      I2 => \fsm_reg_n_0_[2]\,
      O => \gtx_common.gtxe2_common_i_i_4_n_0\
    );
\index[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00FF7000"
    )
        port map (
      I0 => \index_reg_n_0_[1]\,
      I1 => \index_reg_n_0_[2]\,
      I2 => \index[2]_i_2_n_0\,
      I3 => index,
      I4 => \index_reg_n_0_[0]\,
      O => \index[0]_i_1_n_0\
    );
\index[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"10FFC000"
    )
        port map (
      I0 => \index_reg_n_0_[2]\,
      I1 => \index_reg_n_0_[0]\,
      I2 => \index[2]_i_2_n_0\,
      I3 => index,
      I4 => \index_reg_n_0_[1]\,
      O => \index[1]_i_1_n_0\
    );
\index[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"22FF8000"
    )
        port map (
      I0 => \index[2]_i_2_n_0\,
      I1 => \index_reg_n_0_[1]\,
      I2 => \index_reg_n_0_[0]\,
      I3 => index,
      I4 => \index_reg_n_0_[2]\,
      O => \index[2]_i_1_n_0\
    );
\index[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000004"
    )
        port map (
      I0 => \fsm_reg_n_0_[1]\,
      I1 => \fsm_reg_n_0_[6]\,
      I2 => \fsm_reg_n_0_[0]\,
      I3 => \gtx_common.gtxe2_common_i_i_4_n_0\,
      I4 => \fsm_reg_n_0_[4]\,
      O => \index[2]_i_2_n_0\
    );
\index[2]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEFFFEFEEB"
    )
        port map (
      I0 => \index[2]_i_4_n_0\,
      I1 => \fsm_reg_n_0_[5]\,
      I2 => \fsm_reg_n_0_[3]\,
      I3 => \fsm_reg_n_0_[2]\,
      I4 => \fsm_reg_n_0_[1]\,
      I5 => \fsm_reg_n_0_[4]\,
      O => index
    );
\index[2]_i_4\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \fsm_reg_n_0_[0]\,
      I1 => \fsm_reg_n_0_[6]\,
      O => \index[2]_i_4_n_0\
    );
\index_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \index[0]_i_1_n_0\,
      Q => \index_reg_n_0_[0]\,
      R => \out\
    );
\index_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \index[1]_i_1_n_0\,
      Q => \index_reg_n_0_[1]\,
      R => \out\
    );
\index_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \index[2]_i_1_n_0\,
      Q => \index_reg_n_0_[2]\,
      R => \out\
    );
\load_cnt[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00B00000"
    )
        port map (
      I0 => load_cnt(1),
      I1 => load_cnt(0),
      I2 => \fsm_reg_n_0_[1]\,
      I3 => \fsm_reg_n_0_[6]\,
      I4 => \load_cnt[1]_i_2_n_0\,
      O => \load_cnt[0]_i_1_n_0\
    );
\load_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00E00000"
    )
        port map (
      I0 => load_cnt(0),
      I1 => load_cnt(1),
      I2 => \fsm_reg_n_0_[1]\,
      I3 => \fsm_reg_n_0_[6]\,
      I4 => \load_cnt[1]_i_2_n_0\,
      O => \load_cnt[1]_i_1_n_0\
    );
\load_cnt[1]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \fsm_reg_n_0_[4]\,
      I1 => \fsm_reg_n_0_[5]\,
      I2 => \fsm_reg_n_0_[3]\,
      I3 => \fsm_reg_n_0_[2]\,
      I4 => \fsm_reg_n_0_[0]\,
      O => \load_cnt[1]_i_2_n_0\
    );
\load_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \load_cnt[0]_i_1_n_0\,
      Q => load_cnt(0),
      R => \out\
    );
\load_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => CLK,
      CE => '1',
      D => \load_cnt[1]_i_1_n_0\,
      Q => load_cnt(1),
      R => \out\
    );
ovrd_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => '0',
      Q => ovrd_reg1,
      R => \out\
    );
ovrd_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => ovrd_reg1,
      Q => ovrd_reg2,
      R => \out\
    );
qplllock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => QPLL_QPLLLOCK,
      Q => qplllock_reg1,
      R => \out\
    );
qplllock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => qplllock_reg1,
      Q => qplllock_reg2,
      R => \out\
    );
rdy_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => qpll_drp_rdy,
      Q => rdy_reg1,
      R => \out\
    );
rdy_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => rdy_reg1,
      Q => rdy_reg2,
      R => \out\
    );
start_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => QRST_DRP_START,
      Q => start_reg1,
      R => \out\
    );
start_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => '1',
      D => start_reg1,
      Q => start_reg2,
      R => \out\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_qpll_reset is
  port (
    Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_qrst_fsm : out STD_LOGIC_VECTOR ( 3 downto 0 );
    QPLL_QPLLRESET : out STD_LOGIC;
    QPLL_QPLLPD : out STD_LOGIC;
    SS : in STD_LOGIC_VECTOR ( 0 to 0 );
    qpllreset_reg_0 : in STD_LOGIC;
    QRST_QPLLPD_IN : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx_rate : in STD_LOGIC;
    QRST_DRP_DONE : in STD_LOGIC_VECTOR ( 0 to 0 );
    QRST_QPLLRESET_IN : in STD_LOGIC_VECTOR ( 1 downto 0 );
    QRST_QPLLLOCK : in STD_LOGIC_VECTOR ( 0 to 0 );
    QRST_CPLLLOCK : in STD_LOGIC_VECTOR ( 1 downto 0 );
    SYNC_MMCM_LOCK : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_qpll_reset : entity is "spec7_pcie_7x_0_qpll_reset";
end spec7_pcie_7x_0_spec7_pcie_7x_0_qpll_reset;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_qpll_reset is
  signal \FSM_onehot_fsm[0]_i_1__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[2]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[5]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[7]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[0]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[1]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[3]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[4]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[5]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[6]\ : STD_LOGIC;
  signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^qpll_qpllpd\ : STD_LOGIC;
  signal \^qpll_qpllreset\ : STD_LOGIC;
  signal \__3/i__n_0\ : STD_LOGIC;
  signal cplllock_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of cplllock_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of cplllock_reg1 : signal is "true";
  signal cplllock_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of cplllock_reg2 : signal is "NO";
  attribute async_reg of cplllock_reg2 : signal is "true";
  signal drp_done_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of drp_done_reg1 : signal is "NO";
  attribute async_reg of drp_done_reg1 : signal is "true";
  signal drp_done_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of drp_done_reg2 : signal is "NO";
  attribute async_reg of drp_done_reg2 : signal is "true";
  signal mmcm_lock_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of mmcm_lock_reg1 : signal is "NO";
  attribute async_reg of mmcm_lock_reg1 : signal is "true";
  signal mmcm_lock_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of mmcm_lock_reg2 : signal is "NO";
  attribute async_reg of mmcm_lock_reg2 : signal is "true";
  signal qplllock_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of qplllock_reg1 : signal is "NO";
  attribute async_reg of qplllock_reg1 : signal is "true";
  signal qplllock_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of qplllock_reg2 : signal is "NO";
  attribute async_reg of qplllock_reg2 : signal is "true";
  signal qpllpd_i_1_n_0 : STD_LOGIC;
  signal qpllpd_i_2_n_0 : STD_LOGIC;
  signal qpllpd_in_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of qpllpd_in_reg1 : signal is "NO";
  attribute async_reg of qpllpd_in_reg1 : signal is "true";
  signal qpllpd_in_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of qpllpd_in_reg2 : signal is "NO";
  attribute async_reg of qpllpd_in_reg2 : signal is "true";
  signal qpllreset_i_1_n_0 : STD_LOGIC;
  signal qpllreset_in_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of qpllreset_in_reg1 : signal is "NO";
  attribute async_reg of qpllreset_in_reg1 : signal is "true";
  signal qpllreset_in_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of qpllreset_in_reg2 : signal is "NO";
  attribute async_reg of qpllreset_in_reg2 : signal is "true";
  signal rate_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rate_reg1 : signal is "NO";
  attribute async_reg of rate_reg1 : signal is "true";
  signal rate_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rate_reg2 : signal is "NO";
  attribute async_reg of rate_reg2 : signal is "true";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_fsm[7]_i_1\ : label is "soft_lutpair84";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[0]\ : label is "FSM_MMCM_LOCK:00000010,FSM_DRP_START_NOM:00000100,FSM_WAIT_LOCK:00000001,FSM_QPLL_PD:01000000,FSM_QPLL_PDRESET:00100000,FSM_QPLLLOCK2:1010,FSM_IDLE:10000000,FSM_DRP_START_OPT:0111,FSM_QPLL_RESET:1001,FSM_QPLLLOCK:00010000,FSM_DRP_DONE_OPT:1000,FSM_DRP_DONE_NOM:00001000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[1]\ : label is "FSM_MMCM_LOCK:00000010,FSM_DRP_START_NOM:00000100,FSM_WAIT_LOCK:00000001,FSM_QPLL_PD:01000000,FSM_QPLL_PDRESET:00100000,FSM_QPLLLOCK2:1010,FSM_IDLE:10000000,FSM_DRP_START_OPT:0111,FSM_QPLL_RESET:1001,FSM_QPLLLOCK:00010000,FSM_DRP_DONE_OPT:1000,FSM_DRP_DONE_NOM:00001000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[2]\ : label is "FSM_MMCM_LOCK:00000010,FSM_DRP_START_NOM:00000100,FSM_WAIT_LOCK:00000001,FSM_QPLL_PD:01000000,FSM_QPLL_PDRESET:00100000,FSM_QPLLLOCK2:1010,FSM_IDLE:10000000,FSM_DRP_START_OPT:0111,FSM_QPLL_RESET:1001,FSM_QPLLLOCK:00010000,FSM_DRP_DONE_OPT:1000,FSM_DRP_DONE_NOM:00001000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[3]\ : label is "FSM_MMCM_LOCK:00000010,FSM_DRP_START_NOM:00000100,FSM_WAIT_LOCK:00000001,FSM_QPLL_PD:01000000,FSM_QPLL_PDRESET:00100000,FSM_QPLLLOCK2:1010,FSM_IDLE:10000000,FSM_DRP_START_OPT:0111,FSM_QPLL_RESET:1001,FSM_QPLLLOCK:00010000,FSM_DRP_DONE_OPT:1000,FSM_DRP_DONE_NOM:00001000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[4]\ : label is "FSM_MMCM_LOCK:00000010,FSM_DRP_START_NOM:00000100,FSM_WAIT_LOCK:00000001,FSM_QPLL_PD:01000000,FSM_QPLL_PDRESET:00100000,FSM_QPLLLOCK2:1010,FSM_IDLE:10000000,FSM_DRP_START_OPT:0111,FSM_QPLL_RESET:1001,FSM_QPLLLOCK:00010000,FSM_DRP_DONE_OPT:1000,FSM_DRP_DONE_NOM:00001000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[5]\ : label is "FSM_MMCM_LOCK:00000010,FSM_DRP_START_NOM:00000100,FSM_WAIT_LOCK:00000001,FSM_QPLL_PD:01000000,FSM_QPLL_PDRESET:00100000,FSM_QPLLLOCK2:1010,FSM_IDLE:10000000,FSM_DRP_START_OPT:0111,FSM_QPLL_RESET:1001,FSM_QPLLLOCK:00010000,FSM_DRP_DONE_OPT:1000,FSM_DRP_DONE_NOM:00001000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[6]\ : label is "FSM_MMCM_LOCK:00000010,FSM_DRP_START_NOM:00000100,FSM_WAIT_LOCK:00000001,FSM_QPLL_PD:01000000,FSM_QPLL_PDRESET:00100000,FSM_QPLLLOCK2:1010,FSM_IDLE:10000000,FSM_DRP_START_OPT:0111,FSM_QPLL_RESET:1001,FSM_QPLLLOCK:00010000,FSM_DRP_DONE_OPT:1000,FSM_DRP_DONE_NOM:00001000";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[7]\ : label is "FSM_MMCM_LOCK:00000010,FSM_DRP_START_NOM:00000100,FSM_WAIT_LOCK:00000001,FSM_QPLL_PD:01000000,FSM_QPLL_PDRESET:00100000,FSM_QPLLLOCK2:1010,FSM_IDLE:10000000,FSM_DRP_START_OPT:0111,FSM_QPLL_RESET:1001,FSM_QPLLLOCK:00010000,FSM_DRP_DONE_OPT:1000,FSM_DRP_DONE_NOM:00001000";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \cplllock_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \cplllock_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \cplllock_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \cplllock_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \cplllock_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \cplllock_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \cplllock_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \cplllock_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \cplllock_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \cplllock_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \drp_done_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \drp_done_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \drp_done_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \drp_done_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \drp_done_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \drp_done_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of mmcm_lock_reg1_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of mmcm_lock_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of mmcm_lock_reg2_reg : label is std.standard.true;
  attribute KEEP of mmcm_lock_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of mmcm_lock_reg2_reg : label is "NO";
  attribute SOFT_HLUTNM of \pipe_qrst_fsm[0]_INST_0\ : label is "soft_lutpair84";
  attribute SOFT_HLUTNM of \pipe_qrst_fsm[1]_INST_0\ : label is "soft_lutpair83";
  attribute SOFT_HLUTNM of \pipe_qrst_fsm[3]_INST_0\ : label is "soft_lutpair83";
  attribute ASYNC_REG_boolean of \qplllock_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \qplllock_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \qplllock_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \qplllock_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \qplllock_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \qplllock_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \qpllpd_in_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \qpllpd_in_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \qpllpd_in_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \qpllpd_in_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \qpllpd_in_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \qpllpd_in_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \qpllpd_in_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \qpllpd_in_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \qpllpd_in_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \qpllpd_in_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \qpllpd_in_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \qpllpd_in_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \qpllreset_in_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \qpllreset_in_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \qpllreset_in_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \qpllreset_in_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \qpllreset_in_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \qpllreset_in_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \qpllreset_in_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \qpllreset_in_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \qpllreset_in_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \qpllreset_in_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \qpllreset_in_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \qpllreset_in_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rate_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rate_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rate_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rate_reg2_reg[1]\ : label is "NO";
begin
  Q(1 downto 0) <= \^q\(1 downto 0);
  QPLL_QPLLPD <= \^qpll_qpllpd\;
  QPLL_QPLLRESET <= \^qpll_qpllreset\;
\FSM_onehot_fsm[0]_i_1__2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AAA8"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[0]\,
      I1 => qplllock_reg2,
      I2 => cplllock_reg2(0),
      I3 => cplllock_reg2(1),
      O => \FSM_onehot_fsm[0]_i_1__2_n_0\
    );
\FSM_onehot_fsm[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0FFFFFFF00000044"
    )
        port map (
      I0 => qplllock_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[0]\,
      I2 => mmcm_lock_reg2,
      I3 => cplllock_reg2(1),
      I4 => cplllock_reg2(0),
      I5 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => \FSM_onehot_fsm[1]_i_1_n_0\
    );
\FSM_onehot_fsm[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFF800080008000"
    )
        port map (
      I0 => mmcm_lock_reg2,
      I1 => cplllock_reg2(1),
      I2 => cplllock_reg2(0),
      I3 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I4 => drp_done_reg2,
      I5 => \^q\(0),
      O => \FSM_onehot_fsm[2]_i_1_n_0\
    );
\FSM_onehot_fsm[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"32"
    )
        port map (
      I0 => \^q\(0),
      I1 => drp_done_reg2,
      I2 => \FSM_onehot_fsm_reg_n_0_[3]\,
      O => \FSM_onehot_fsm[3]_i_1_n_0\
    );
\FSM_onehot_fsm[4]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"8F88"
    )
        port map (
      I0 => drp_done_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => qplllock_reg2,
      I3 => \FSM_onehot_fsm_reg_n_0_[4]\,
      O => \FSM_onehot_fsm[4]_i_1_n_0\
    );
\FSM_onehot_fsm[5]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => qplllock_reg2,
      O => \FSM_onehot_fsm[5]_i_1_n_0\
    );
\FSM_onehot_fsm[7]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[6]\,
      I1 => \^q\(1),
      O => \FSM_onehot_fsm[7]_i_1_n_0\
    );
\FSM_onehot_fsm_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => \FSM_onehot_fsm[0]_i_1__2_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[0]\,
      S => SS(0)
    );
\FSM_onehot_fsm_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => \FSM_onehot_fsm[1]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[1]\,
      R => SS(0)
    );
\FSM_onehot_fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => \FSM_onehot_fsm[2]_i_1_n_0\,
      Q => \^q\(0),
      R => SS(0)
    );
\FSM_onehot_fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => \FSM_onehot_fsm[3]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[3]\,
      R => SS(0)
    );
\FSM_onehot_fsm_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => \FSM_onehot_fsm[4]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[4]\,
      R => SS(0)
    );
\FSM_onehot_fsm_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => \FSM_onehot_fsm[5]_i_1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[5]\,
      R => SS(0)
    );
\FSM_onehot_fsm_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => \FSM_onehot_fsm_reg_n_0_[5]\,
      Q => \FSM_onehot_fsm_reg_n_0_[6]\,
      R => SS(0)
    );
\FSM_onehot_fsm_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => \FSM_onehot_fsm[7]_i_1_n_0\,
      Q => \^q\(1),
      R => SS(0)
    );
\__3/i_\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFB0B0B0B0B0B0B0"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      I2 => \FSM_onehot_fsm_reg_n_0_[5]\,
      I3 => qpllreset_in_reg2(0),
      I4 => qpllreset_in_reg2(1),
      I5 => \^q\(1),
      O => \__3/i__n_0\
    );
\cplllock_reg1_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => QRST_CPLLLOCK(0),
      Q => cplllock_reg1(0),
      S => SS(0)
    );
\cplllock_reg1_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => QRST_CPLLLOCK(1),
      Q => cplllock_reg1(1),
      S => SS(0)
    );
\cplllock_reg2_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => cplllock_reg1(0),
      Q => cplllock_reg2(0),
      S => SS(0)
    );
\cplllock_reg2_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => cplllock_reg1(1),
      Q => cplllock_reg2(1),
      S => SS(0)
    );
\drp_done_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => QRST_DRP_DONE(0),
      Q => drp_done_reg1,
      R => SS(0)
    );
\drp_done_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => drp_done_reg1,
      Q => drp_done_reg2,
      R => SS(0)
    );
mmcm_lock_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => SYNC_MMCM_LOCK,
      Q => mmcm_lock_reg1,
      R => SS(0)
    );
mmcm_lock_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => mmcm_lock_reg1,
      Q => mmcm_lock_reg2,
      R => SS(0)
    );
\pipe_qrst_fsm[0]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \^q\(1),
      I1 => \FSM_onehot_fsm_reg_n_0_[5]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[3]\,
      O => pipe_qrst_fsm(0)
    );
\pipe_qrst_fsm[1]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[5]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[0]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => pipe_qrst_fsm(1)
    );
\pipe_qrst_fsm[2]_INST_0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFE"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[6]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I2 => \^q\(0),
      I3 => \FSM_onehot_fsm_reg_n_0_[3]\,
      O => pipe_qrst_fsm(2)
    );
\pipe_qrst_fsm[3]_INST_0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[5]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[6]\,
      O => pipe_qrst_fsm(3)
    );
\qplllock_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => QRST_QPLLLOCK(0),
      Q => qplllock_reg1,
      R => SS(0)
    );
\qplllock_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => qplllock_reg1,
      Q => qplllock_reg2,
      R => SS(0)
    );
qpllpd_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"EAC0AAFFEAC0AA00"
    )
        port map (
      I0 => qpllpd_i_2_n_0,
      I1 => qpllpd_in_reg2(0),
      I2 => qpllpd_in_reg2(1),
      I3 => \FSM_onehot_fsm_reg_n_0_[6]\,
      I4 => \^q\(1),
      I5 => \^qpll_qpllpd\,
      O => qpllpd_i_1_n_0
    );
qpllpd_i_2: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => rate_reg2(0),
      I1 => rate_reg2(1),
      O => qpllpd_i_2_n_0
    );
\qpllpd_in_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => QRST_QPLLPD_IN(0),
      Q => qpllpd_in_reg1(0),
      R => SS(0)
    );
\qpllpd_in_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => QRST_QPLLPD_IN(1),
      Q => qpllpd_in_reg1(1),
      R => SS(0)
    );
\qpllpd_in_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => qpllpd_in_reg1(0),
      Q => qpllpd_in_reg2(0),
      R => SS(0)
    );
\qpllpd_in_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => qpllpd_in_reg1(1),
      Q => qpllpd_in_reg2(1),
      R => SS(0)
    );
qpllpd_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => qpllpd_i_1_n_0,
      Q => \^qpll_qpllpd\,
      R => SS(0)
    );
qpllreset_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAABAAA8"
    )
        port map (
      I0 => \__3/i__n_0\,
      I1 => \FSM_onehot_fsm_reg_n_0_[5]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I3 => \^q\(1),
      I4 => \^qpll_qpllreset\,
      O => qpllreset_i_1_n_0
    );
\qpllreset_in_reg1_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => QRST_QPLLRESET_IN(0),
      Q => qpllreset_in_reg1(0),
      S => SS(0)
    );
\qpllreset_in_reg1_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => QRST_QPLLRESET_IN(1),
      Q => qpllreset_in_reg1(1),
      S => SS(0)
    );
\qpllreset_in_reg2_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => qpllreset_in_reg1(0),
      Q => qpllreset_in_reg2(0),
      S => SS(0)
    );
\qpllreset_in_reg2_reg[1]\: unisim.vcomponents.FDSE
     port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => qpllreset_in_reg1(1),
      Q => qpllreset_in_reg2(1),
      S => SS(0)
    );
qpllreset_reg: unisim.vcomponents.FDSE
    generic map(
      INIT => '1'
    )
        port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => qpllreset_i_1_n_0,
      Q => \^qpll_qpllreset\,
      S => SS(0)
    );
\rate_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => pipe_tx_rate,
      Q => rate_reg1(0),
      R => SS(0)
    );
\rate_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => '0',
      Q => rate_reg1(1),
      R => SS(0)
    );
\rate_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => rate_reg1(0),
      Q => rate_reg2(0),
      R => SS(0)
    );
\rate_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => qpllreset_reg_0,
      CE => '1',
      D => rate_reg1(1),
      Q => rate_reg2(1),
      R => SS(0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_qpll_wrapper is
  port (
    qpll_drp_rdy : out STD_LOGIC;
    QPLL_QPLLLOCK : out STD_LOGIC;
    int_qplloutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    int_qplloutrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 15 downto 0 );
    CLK : in STD_LOGIC;
    qpll_drp_en : in STD_LOGIC;
    qpll_drp_we : in STD_LOGIC;
    sys_clk : in STD_LOGIC;
    QPLL_QPLLPD : in STD_LOGIC;
    QPLL_QPLLRESET : in STD_LOGIC;
    rdy_reg1_reg : in STD_LOGIC_VECTOR ( 15 downto 0 );
    Q : in STD_LOGIC_VECTOR ( 4 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_qpll_wrapper : entity is "spec7_pcie_7x_0_qpll_wrapper";
end spec7_pcie_7x_0_spec7_pcie_7x_0_qpll_wrapper;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_qpll_wrapper is
  signal \NLW_gtx_common.gtxe2_common_i_QPLLFBCLKLOST_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_common.gtxe2_common_i_QPLLREFCLKLOST_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_common.gtxe2_common_i_REFCLKOUTMONITOR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_common.gtxe2_common_i_QPLLDMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  attribute box_type : string;
  attribute box_type of \gtx_common.gtxe2_common_i\ : label is "PRIMITIVE";
begin
\gtx_common.gtxe2_common_i\: unisim.vcomponents.GTXE2_COMMON
    generic map(
      BIAS_CFG => X"0000040000001000",
      COMMON_CFG => X"00000000",
      IS_DRPCLK_INVERTED => '0',
      IS_GTGREFCLK_INVERTED => '0',
      IS_QPLLLOCKDETCLK_INVERTED => '0',
      QPLL_CFG => X"06801C1",
      QPLL_CLKOUT_CFG => B"0000",
      QPLL_COARSE_FREQ_OVRD => B"010000",
      QPLL_COARSE_FREQ_OVRD_EN => '0',
      QPLL_CP => B"0000011111",
      QPLL_CP_MONITOR_EN => '0',
      QPLL_DMONITOR_SEL => '0',
      QPLL_FBDIV => B"0100100000",
      QPLL_FBDIV_MONITOR_EN => '0',
      QPLL_FBDIV_RATIO => '1',
      QPLL_INIT_CFG => X"000006",
      QPLL_LOCK_CFG => X"21E8",
      QPLL_LPF => B"1101",
      QPLL_REFCLK_DIV => 1,
      SIM_QPLLREFCLK_SEL => B"001",
      SIM_RESET_SPEEDUP => "FALSE",
      SIM_VERSION => "3.0"
    )
        port map (
      BGBYPASSB => '1',
      BGMONITORENB => '1',
      BGPDB => '1',
      BGRCALOVRD(4 downto 0) => B"11111",
      DRPADDR(7) => Q(4),
      DRPADDR(6) => '0',
      DRPADDR(5) => Q(3),
      DRPADDR(4) => Q(3),
      DRPADDR(3) => Q(4),
      DRPADDR(2 downto 0) => Q(2 downto 0),
      DRPCLK => CLK,
      DRPDI(15 downto 0) => rdy_reg1_reg(15 downto 0),
      DRPDO(15 downto 0) => D(15 downto 0),
      DRPEN => qpll_drp_en,
      DRPRDY => qpll_drp_rdy,
      DRPWE => qpll_drp_we,
      GTGREFCLK => '0',
      GTNORTHREFCLK0 => '0',
      GTNORTHREFCLK1 => '0',
      GTREFCLK0 => sys_clk,
      GTREFCLK1 => '0',
      GTSOUTHREFCLK0 => '0',
      GTSOUTHREFCLK1 => '0',
      PMARSVD(7 downto 0) => B"00000000",
      QPLLDMONITOR(7 downto 0) => \NLW_gtx_common.gtxe2_common_i_QPLLDMONITOR_UNCONNECTED\(7 downto 0),
      QPLLFBCLKLOST => \NLW_gtx_common.gtxe2_common_i_QPLLFBCLKLOST_UNCONNECTED\,
      QPLLLOCK => QPLL_QPLLLOCK,
      QPLLLOCKDETCLK => '0',
      QPLLLOCKEN => '1',
      QPLLOUTCLK => int_qplloutclk_out(0),
      QPLLOUTREFCLK => int_qplloutrefclk_out(0),
      QPLLOUTRESET => '0',
      QPLLPD => QPLL_QPLLPD,
      QPLLREFCLKLOST => \NLW_gtx_common.gtxe2_common_i_QPLLREFCLKLOST_UNCONNECTED\,
      QPLLREFCLKSEL(2 downto 0) => B"001",
      QPLLRESET => QPLL_QPLLRESET,
      QPLLRSVD1(15 downto 0) => B"0000000000000000",
      QPLLRSVD2(4 downto 0) => B"11111",
      RCALENB => '1',
      REFCLKOUTMONITOR => \NLW_gtx_common.gtxe2_common_i_REFCLKOUTMONITOR_UNCONNECTED\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_rxeq_scan is
  port (
    adapt_done_reg_0 : out STD_LOGIC;
    new_txcoeff_done_reg_0 : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 2 downto 0 );
    rxeq_new_txcoeff_req : out STD_LOGIC;
    \out\ : in STD_LOGIC;
    \fs_reg2_reg[5]_0\ : in STD_LOGIC;
    new_txcoeff_req_reg1_reg_0 : in STD_LOGIC;
    rxeq_preset_valid : in STD_LOGIC;
    adapt_done_cnt_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxeq_adapt_done_reg_reg : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
    rxeq_adapt_done_reg_reg_0 : in STD_LOGIC;
    rxeq_adapt_done_reg_reg_1 : in STD_LOGIC;
    rxeq_adapt_done_reg : in STD_LOGIC;
    rxeq_adapt_done_reg_0 : in STD_LOGIC;
    \FSM_onehot_fsm_rx_reg[5]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \preset_reg1_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \txpreset_reg1_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \txcoeff_reg1_reg[17]_0\ : in STD_LOGIC_VECTOR ( 17 downto 0 );
    \fs_reg1_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \lf_reg1_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_rxeq_scan : entity is "spec7_pcie_7x_0_rxeq_scan";
end spec7_pcie_7x_0_spec7_pcie_7x_0_rxeq_scan;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_rxeq_scan is
  signal \FSM_onehot_fsm[1]_i_1__3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[2]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_10__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_1__2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_2__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_3__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_4__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_5__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_6__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_7__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_8__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_9__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[1]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[2]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[3]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[4]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx[6]_i_2__0_n_0\ : STD_LOGIC;
  signal adapt_done : STD_LOGIC;
  signal \adapt_done_cnt_i_1__0_n_0\ : STD_LOGIC;
  signal \adapt_done_cnt_i_2__0_n_0\ : STD_LOGIC;
  signal adapt_done_cnt_reg_n_0 : STD_LOGIC;
  signal converge_cnt : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal converge_cnt0 : STD_LOGIC_VECTOR ( 21 downto 1 );
  signal converge_cnt_0 : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal \converge_cnt_reg[12]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_2__0_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_2__0_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_2__0_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_2__0_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_2__0_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_2__0_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[20]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[20]_i_2__0_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[20]_i_2__0_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[20]_i_2__0_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_2__0_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_2__0_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_2__0_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_2__0_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_2__0_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_2__0_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_2__0_n_3\ : STD_LOGIC;
  signal fs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of fs_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of fs_reg1 : signal is "true";
  signal fs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT of fs_reg2 : signal is "NO";
  attribute async_reg of fs_reg2 : signal is "true";
  signal lf_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT of lf_reg1 : signal is "NO";
  attribute async_reg of lf_reg1 : signal is "true";
  signal lf_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT of lf_reg2 : signal is "NO";
  attribute async_reg of lf_reg2 : signal is "true";
  signal new_txcoeff_done : STD_LOGIC;
  signal new_txcoeff_req_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of new_txcoeff_req_reg1 : signal is "NO";
  attribute async_reg of new_txcoeff_req_reg1 : signal is "true";
  signal new_txcoeff_req_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of new_txcoeff_req_reg2 : signal is "NO";
  attribute async_reg of new_txcoeff_req_reg2 : signal is "true";
  signal preset_done : STD_LOGIC;
  signal preset_done_1 : STD_LOGIC;
  signal preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute SHIFT_EXTRACT of preset_reg1 : signal is "NO";
  attribute async_reg of preset_reg1 : signal is "true";
  signal preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute SHIFT_EXTRACT of preset_reg2 : signal is "NO";
  attribute async_reg of preset_reg2 : signal is "true";
  signal preset_valid_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of preset_valid_reg1 : signal is "NO";
  attribute async_reg of preset_valid_reg1 : signal is "true";
  signal preset_valid_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of preset_valid_reg2 : signal is "NO";
  attribute async_reg of preset_valid_reg2 : signal is "true";
  signal rxeqscan_adapt_done : STD_LOGIC;
  signal rxeqscan_new_txcoeff_done : STD_LOGIC;
  signal txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 );
  attribute SHIFT_EXTRACT of txcoeff_reg1 : signal is "NO";
  attribute async_reg of txcoeff_reg1 : signal is "true";
  signal txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 );
  attribute SHIFT_EXTRACT of txcoeff_reg2 : signal is "NO";
  attribute async_reg of txcoeff_reg2 : signal is "true";
  signal txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SHIFT_EXTRACT of txpreset_reg1 : signal is "NO";
  attribute async_reg of txpreset_reg1 : signal is "true";
  signal txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SHIFT_EXTRACT of txpreset_reg2 : signal is "NO";
  attribute async_reg of txpreset_reg2 : signal is "true";
  signal \NLW_converge_cnt_reg[21]_i_2__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_converge_cnt_reg[21]_i_2__0_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_fsm[3]_i_2__0\ : label is "soft_lutpair56";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[1]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[2]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[3]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[4]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001";
  attribute SOFT_HLUTNM of \FSM_onehot_fsm_rx[6]_i_2__0\ : label is "soft_lutpair57";
  attribute SOFT_HLUTNM of \converge_cnt[12]_i_1__0\ : label is "soft_lutpair56";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \fs_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \fs_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg1_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg1_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg2_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg2_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg1_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg1_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg2_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg2_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of new_txcoeff_req_reg1_reg : label is std.standard.true;
  attribute KEEP of new_txcoeff_req_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of new_txcoeff_req_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of new_txcoeff_req_reg2_reg : label is std.standard.true;
  attribute KEEP of new_txcoeff_req_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of new_txcoeff_req_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of \preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \preset_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \preset_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \preset_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \preset_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \preset_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \preset_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of preset_valid_reg1_reg : label is std.standard.true;
  attribute KEEP of preset_valid_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of preset_valid_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of preset_valid_reg2_reg : label is std.standard.true;
  attribute KEEP of preset_valid_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of preset_valid_reg2_reg : label is "NO";
  attribute SOFT_HLUTNM of rxeq_new_txcoeff_req_i_1 : label is "soft_lutpair57";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[10]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[10]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[11]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[11]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[12]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[12]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[13]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[13]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[14]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[14]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[15]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[15]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[16]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[16]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[16]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[17]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[17]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[17]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[6]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[6]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[7]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[7]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[8]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[8]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[9]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[9]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[10]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[10]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[11]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[11]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[12]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[12]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[13]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[13]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[14]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[14]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[15]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[15]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[16]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[16]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[16]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[17]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[17]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[17]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[6]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[6]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[7]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[7]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[8]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[8]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[9]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[9]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg2_reg[3]\ : label is "NO";
begin
\FSM_onehot_fsm[1]_i_1__3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001FF01AAABFFFB"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I4 => preset_valid_reg2,
      I5 => new_txcoeff_req_reg2,
      O => \FSM_onehot_fsm[1]_i_1__3_n_0\
    );
\FSM_onehot_fsm[2]_i_1__1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => preset_valid_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => \FSM_onehot_fsm[2]_i_1__1_n_0\
    );
\FSM_onehot_fsm[3]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4F444444"
    )
        port map (
      I0 => \FSM_onehot_fsm[3]_i_2__0_n_0\,
      I1 => \FSM_onehot_fsm[4]_i_2__1_n_0\,
      I2 => preset_valid_reg2,
      I3 => new_txcoeff_req_reg2,
      I4 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => \FSM_onehot_fsm[3]_i_1__1_n_0\
    );
\FSM_onehot_fsm[3]_i_2__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"04FF"
    )
        port map (
      I0 => adapt_done_cnt_reg_0(0),
      I1 => adapt_done_cnt_reg_0(1),
      I2 => adapt_done_cnt_reg_n_0,
      I3 => \FSM_onehot_fsm_reg_n_0_[3]\,
      O => \FSM_onehot_fsm[3]_i_2__0_n_0\
    );
\FSM_onehot_fsm[4]_i_10__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => converge_cnt(15),
      I1 => converge_cnt(3),
      I2 => converge_cnt(8),
      I3 => converge_cnt(13),
      O => \FSM_onehot_fsm[4]_i_10__0_n_0\
    );
\FSM_onehot_fsm[4]_i_1__2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF55750000"
    )
        port map (
      I0 => \FSM_onehot_fsm[4]_i_2__1_n_0\,
      I1 => adapt_done_cnt_reg_0(0),
      I2 => adapt_done_cnt_reg_0(1),
      I3 => adapt_done_cnt_reg_n_0,
      I4 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I5 => new_txcoeff_done,
      O => \FSM_onehot_fsm[4]_i_1__2_n_0\
    );
\FSM_onehot_fsm[4]_i_2__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CCDCFFDF"
    )
        port map (
      I0 => \FSM_onehot_fsm[4]_i_3__0_n_0\,
      I1 => \FSM_onehot_fsm[4]_i_4__0_n_0\,
      I2 => adapt_done_cnt_reg_0(1),
      I3 => adapt_done_cnt_reg_0(0),
      I4 => \FSM_onehot_fsm[4]_i_5__0_n_0\,
      O => \FSM_onehot_fsm[4]_i_2__1_n_0\
    );
\FSM_onehot_fsm[4]_i_3__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000020"
    )
        port map (
      I0 => \FSM_onehot_fsm[4]_i_6__0_n_0\,
      I1 => \FSM_onehot_fsm[4]_i_7__0_n_0\,
      I2 => converge_cnt(21),
      I3 => converge_cnt(20),
      I4 => converge_cnt(7),
      I5 => converge_cnt(0),
      O => \FSM_onehot_fsm[4]_i_3__0_n_0\
    );
\FSM_onehot_fsm[4]_i_4__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF7FF"
    )
        port map (
      I0 => converge_cnt(11),
      I1 => converge_cnt(19),
      I2 => converge_cnt(5),
      I3 => converge_cnt(17),
      I4 => \FSM_onehot_fsm[4]_i_8__0_n_0\,
      O => \FSM_onehot_fsm[4]_i_4__0_n_0\
    );
\FSM_onehot_fsm[4]_i_5__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000200000"
    )
        port map (
      I0 => \FSM_onehot_fsm[4]_i_9__0_n_0\,
      I1 => \FSM_onehot_fsm[4]_i_10__0_n_0\,
      I2 => converge_cnt(0),
      I3 => converge_cnt(21),
      I4 => converge_cnt(20),
      I5 => converge_cnt(10),
      O => \FSM_onehot_fsm[4]_i_5__0_n_0\
    );
\FSM_onehot_fsm[4]_i_6__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000040000000000"
    )
        port map (
      I0 => converge_cnt(12),
      I1 => converge_cnt(10),
      I2 => converge_cnt(6),
      I3 => converge_cnt(8),
      I4 => converge_cnt(2),
      I5 => converge_cnt(3),
      O => \FSM_onehot_fsm[4]_i_6__0_n_0\
    );
\FSM_onehot_fsm[4]_i_7__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF7"
    )
        port map (
      I0 => converge_cnt(15),
      I1 => converge_cnt(13),
      I2 => converge_cnt(4),
      I3 => converge_cnt(14),
      O => \FSM_onehot_fsm[4]_i_7__0_n_0\
    );
\FSM_onehot_fsm[4]_i_8__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FF7F"
    )
        port map (
      I0 => converge_cnt(16),
      I1 => converge_cnt(18),
      I2 => converge_cnt(9),
      I3 => converge_cnt(1),
      O => \FSM_onehot_fsm[4]_i_8__0_n_0\
    );
\FSM_onehot_fsm[4]_i_9__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001000000000000"
    )
        port map (
      I0 => converge_cnt(7),
      I1 => converge_cnt(12),
      I2 => converge_cnt(6),
      I3 => converge_cnt(4),
      I4 => converge_cnt(14),
      I5 => converge_cnt(2),
      O => \FSM_onehot_fsm[4]_i_9__0_n_0\
    );
\FSM_onehot_fsm_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[1]_i_1__3_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[1]\,
      S => \out\
    );
\FSM_onehot_fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[2]_i_1__1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[2]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[3]_i_1__1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[3]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[4]_i_1__2_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[4]\,
      R => \out\
    );
\FSM_onehot_fsm_rx[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40FF4040"
    )
        port map (
      I0 => adapt_done_cnt_reg_0(1),
      I1 => Q(0),
      I2 => adapt_done_cnt_reg_0(0),
      I3 => preset_done,
      I4 => Q(1),
      O => D(0)
    );
\FSM_onehot_fsm_rx[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F444444444444444"
    )
        port map (
      I0 => rxeqscan_new_txcoeff_done,
      I1 => Q(3),
      I2 => \FSM_onehot_fsm_rx_reg[5]\(1),
      I3 => \FSM_onehot_fsm_rx_reg[5]\(0),
      I4 => \FSM_onehot_fsm_rx_reg[5]\(2),
      I5 => Q(2),
      O => D(1)
    );
\FSM_onehot_fsm_rx[6]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFE0E0E0"
    )
        port map (
      I0 => adapt_done_cnt_reg_0(0),
      I1 => adapt_done_cnt_reg_0(1),
      I2 => Q(4),
      I3 => preset_done,
      I4 => Q(1),
      I5 => \FSM_onehot_fsm_rx[6]_i_2__0_n_0\,
      O => D(2)
    );
\FSM_onehot_fsm_rx[6]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => rxeqscan_new_txcoeff_done,
      I1 => Q(3),
      O => \FSM_onehot_fsm_rx[6]_i_2__0_n_0\
    );
\adapt_done_cnt_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000A0A0AF0F0F8F0"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_n_0,
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_0(0),
      I5 => \adapt_done_cnt_i_2__0_n_0\,
      O => \adapt_done_cnt_i_1__0_n_0\
    );
\adapt_done_cnt_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00FF0101"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I3 => new_txcoeff_req_reg2,
      I4 => \FSM_onehot_fsm_reg_n_0_[4]\,
      O => \adapt_done_cnt_i_2__0_n_0\
    );
adapt_done_cnt_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \adapt_done_cnt_i_1__0_n_0\,
      Q => adapt_done_cnt_reg_n_0,
      R => \out\
    );
\adapt_done_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F8000000"
    )
        port map (
      I0 => adapt_done_cnt_reg_0(0),
      I1 => adapt_done_cnt_reg_0(1),
      I2 => adapt_done_cnt_reg_n_0,
      I3 => new_txcoeff_req_reg2,
      I4 => \FSM_onehot_fsm_reg_n_0_[4]\,
      O => adapt_done
    );
adapt_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => adapt_done,
      Q => rxeqscan_adapt_done,
      R => \out\
    );
\converge_cnt[0]_i_1__2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44444044"
    )
        port map (
      I0 => converge_cnt(0),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_n_0,
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_0(0),
      O => converge_cnt_0(0)
    );
\converge_cnt[10]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(10),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_n_0,
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_0(0),
      O => converge_cnt_0(10)
    );
\converge_cnt[11]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(11),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_n_0,
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_0(0),
      O => converge_cnt_0(11)
    );
\converge_cnt[12]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(12),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_n_0,
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_0(0),
      O => converge_cnt_0(12)
    );
\converge_cnt[13]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(13),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_n_0,
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_0(0),
      O => converge_cnt_0(13)
    );
\converge_cnt[14]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(14),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_n_0,
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_0(0),
      O => converge_cnt_0(14)
    );
\converge_cnt[15]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(15),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_n_0,
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_0(0),
      O => converge_cnt_0(15)
    );
\converge_cnt[16]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(16),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_n_0,
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_0(0),
      O => converge_cnt_0(16)
    );
\converge_cnt[17]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(17),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_n_0,
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_0(0),
      O => converge_cnt_0(17)
    );
\converge_cnt[18]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(18),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_n_0,
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_0(0),
      O => converge_cnt_0(18)
    );
\converge_cnt[19]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(19),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_n_0,
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_0(0),
      O => converge_cnt_0(19)
    );
\converge_cnt[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(1),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_n_0,
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_0(0),
      O => converge_cnt_0(1)
    );
\converge_cnt[20]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(20),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_n_0,
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_0(0),
      O => converge_cnt_0(20)
    );
\converge_cnt[21]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(21),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_n_0,
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_0(0),
      O => converge_cnt_0(21)
    );
\converge_cnt[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(2),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_n_0,
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_0(0),
      O => converge_cnt_0(2)
    );
\converge_cnt[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(3),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_n_0,
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_0(0),
      O => converge_cnt_0(3)
    );
\converge_cnt[4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(4),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_n_0,
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_0(0),
      O => converge_cnt_0(4)
    );
\converge_cnt[5]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(5),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_n_0,
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_0(0),
      O => converge_cnt_0(5)
    );
\converge_cnt[6]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(6),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_n_0,
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_0(0),
      O => converge_cnt_0(6)
    );
\converge_cnt[7]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(7),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_n_0,
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_0(0),
      O => converge_cnt_0(7)
    );
\converge_cnt[8]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(8),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_n_0,
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_0(0),
      O => converge_cnt_0(8)
    );
\converge_cnt[9]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(9),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_n_0,
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_0(0),
      O => converge_cnt_0(9)
    );
\converge_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(0),
      Q => converge_cnt(0),
      R => \out\
    );
\converge_cnt_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(10),
      Q => converge_cnt(10),
      R => \out\
    );
\converge_cnt_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(11),
      Q => converge_cnt(11),
      R => \out\
    );
\converge_cnt_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(12),
      Q => converge_cnt(12),
      R => \out\
    );
\converge_cnt_reg[12]_i_2__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[8]_i_2__0_n_0\,
      CO(3) => \converge_cnt_reg[12]_i_2__0_n_0\,
      CO(2) => \converge_cnt_reg[12]_i_2__0_n_1\,
      CO(1) => \converge_cnt_reg[12]_i_2__0_n_2\,
      CO(0) => \converge_cnt_reg[12]_i_2__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => converge_cnt0(12 downto 9),
      S(3 downto 0) => converge_cnt(12 downto 9)
    );
\converge_cnt_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(13),
      Q => converge_cnt(13),
      R => \out\
    );
\converge_cnt_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(14),
      Q => converge_cnt(14),
      R => \out\
    );
\converge_cnt_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(15),
      Q => converge_cnt(15),
      R => \out\
    );
\converge_cnt_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(16),
      Q => converge_cnt(16),
      R => \out\
    );
\converge_cnt_reg[16]_i_2__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[12]_i_2__0_n_0\,
      CO(3) => \converge_cnt_reg[16]_i_2__0_n_0\,
      CO(2) => \converge_cnt_reg[16]_i_2__0_n_1\,
      CO(1) => \converge_cnt_reg[16]_i_2__0_n_2\,
      CO(0) => \converge_cnt_reg[16]_i_2__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => converge_cnt0(16 downto 13),
      S(3 downto 0) => converge_cnt(16 downto 13)
    );
\converge_cnt_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(17),
      Q => converge_cnt(17),
      R => \out\
    );
\converge_cnt_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(18),
      Q => converge_cnt(18),
      R => \out\
    );
\converge_cnt_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(19),
      Q => converge_cnt(19),
      R => \out\
    );
\converge_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(1),
      Q => converge_cnt(1),
      R => \out\
    );
\converge_cnt_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(20),
      Q => converge_cnt(20),
      R => \out\
    );
\converge_cnt_reg[20]_i_2__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[16]_i_2__0_n_0\,
      CO(3) => \converge_cnt_reg[20]_i_2__0_n_0\,
      CO(2) => \converge_cnt_reg[20]_i_2__0_n_1\,
      CO(1) => \converge_cnt_reg[20]_i_2__0_n_2\,
      CO(0) => \converge_cnt_reg[20]_i_2__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => converge_cnt0(20 downto 17),
      S(3 downto 0) => converge_cnt(20 downto 17)
    );
\converge_cnt_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(21),
      Q => converge_cnt(21),
      R => \out\
    );
\converge_cnt_reg[21]_i_2__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[20]_i_2__0_n_0\,
      CO(3 downto 0) => \NLW_converge_cnt_reg[21]_i_2__0_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_converge_cnt_reg[21]_i_2__0_O_UNCONNECTED\(3 downto 1),
      O(0) => converge_cnt0(21),
      S(3 downto 1) => B"000",
      S(0) => converge_cnt(21)
    );
\converge_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(2),
      Q => converge_cnt(2),
      R => \out\
    );
\converge_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(3),
      Q => converge_cnt(3),
      R => \out\
    );
\converge_cnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(4),
      Q => converge_cnt(4),
      R => \out\
    );
\converge_cnt_reg[4]_i_2__0\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \converge_cnt_reg[4]_i_2__0_n_0\,
      CO(2) => \converge_cnt_reg[4]_i_2__0_n_1\,
      CO(1) => \converge_cnt_reg[4]_i_2__0_n_2\,
      CO(0) => \converge_cnt_reg[4]_i_2__0_n_3\,
      CYINIT => converge_cnt(0),
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => converge_cnt0(4 downto 1),
      S(3 downto 0) => converge_cnt(4 downto 1)
    );
\converge_cnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(5),
      Q => converge_cnt(5),
      R => \out\
    );
\converge_cnt_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(6),
      Q => converge_cnt(6),
      R => \out\
    );
\converge_cnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(7),
      Q => converge_cnt(7),
      R => \out\
    );
\converge_cnt_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(8),
      Q => converge_cnt(8),
      R => \out\
    );
\converge_cnt_reg[8]_i_2__0\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[4]_i_2__0_n_0\,
      CO(3) => \converge_cnt_reg[8]_i_2__0_n_0\,
      CO(2) => \converge_cnt_reg[8]_i_2__0_n_1\,
      CO(1) => \converge_cnt_reg[8]_i_2__0_n_2\,
      CO(0) => \converge_cnt_reg[8]_i_2__0_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => converge_cnt0(8 downto 5),
      S(3 downto 0) => converge_cnt(8 downto 5)
    );
\converge_cnt_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(9),
      Q => converge_cnt(9),
      R => \out\
    );
\fs_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \fs_reg1_reg[5]_0\(0),
      Q => fs_reg1(0),
      R => \out\
    );
\fs_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \fs_reg1_reg[5]_0\(1),
      Q => fs_reg1(1),
      R => \out\
    );
\fs_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \fs_reg1_reg[5]_0\(2),
      Q => fs_reg1(2),
      R => \out\
    );
\fs_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \fs_reg1_reg[5]_0\(3),
      Q => fs_reg1(3),
      R => \out\
    );
\fs_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \fs_reg1_reg[5]_0\(4),
      Q => fs_reg1(4),
      R => \out\
    );
\fs_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \fs_reg1_reg[5]_0\(5),
      Q => fs_reg1(5),
      R => \out\
    );
\fs_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => fs_reg1(0),
      Q => fs_reg2(0),
      R => \out\
    );
\fs_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => fs_reg1(1),
      Q => fs_reg2(1),
      R => \out\
    );
\fs_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => fs_reg1(2),
      Q => fs_reg2(2),
      R => \out\
    );
\fs_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => fs_reg1(3),
      Q => fs_reg2(3),
      R => \out\
    );
\fs_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => fs_reg1(4),
      Q => fs_reg2(4),
      R => \out\
    );
\fs_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => fs_reg1(5),
      Q => fs_reg2(5),
      R => \out\
    );
\lf_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \lf_reg1_reg[5]_0\(0),
      Q => lf_reg1(0),
      R => \out\
    );
\lf_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \lf_reg1_reg[5]_0\(1),
      Q => lf_reg1(1),
      R => \out\
    );
\lf_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \lf_reg1_reg[5]_0\(2),
      Q => lf_reg1(2),
      R => \out\
    );
\lf_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \lf_reg1_reg[5]_0\(3),
      Q => lf_reg1(3),
      R => \out\
    );
\lf_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \lf_reg1_reg[5]_0\(4),
      Q => lf_reg1(4),
      R => \out\
    );
\lf_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \lf_reg1_reg[5]_0\(5),
      Q => lf_reg1(5),
      R => \out\
    );
\lf_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => lf_reg1(0),
      Q => lf_reg2(0),
      R => \out\
    );
\lf_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => lf_reg1(1),
      Q => lf_reg2(1),
      R => \out\
    );
\lf_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => lf_reg1(2),
      Q => lf_reg2(2),
      R => \out\
    );
\lf_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => lf_reg1(3),
      Q => lf_reg2(3),
      R => \out\
    );
\lf_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => lf_reg1(4),
      Q => lf_reg2(4),
      R => \out\
    );
\lf_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => lf_reg1(5),
      Q => lf_reg2(5),
      R => \out\
    );
\new_txcoeff_done_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => new_txcoeff_req_reg2,
      O => new_txcoeff_done
    );
new_txcoeff_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => new_txcoeff_done,
      Q => rxeqscan_new_txcoeff_done,
      R => \out\
    );
new_txcoeff_req_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => new_txcoeff_req_reg1_reg_0,
      Q => new_txcoeff_req_reg1,
      R => \out\
    );
new_txcoeff_req_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => new_txcoeff_req_reg1,
      Q => new_txcoeff_req_reg2,
      R => \out\
    );
\preset_done_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I2 => preset_valid_reg2,
      O => preset_done_1
    );
preset_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => preset_done_1,
      Q => preset_done,
      R => \out\
    );
\preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \preset_reg1_reg[2]_0\(0),
      Q => preset_reg1(0),
      R => \out\
    );
\preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \preset_reg1_reg[2]_0\(1),
      Q => preset_reg1(1),
      R => \out\
    );
\preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \preset_reg1_reg[2]_0\(2),
      Q => preset_reg1(2),
      R => \out\
    );
\preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => preset_reg1(0),
      Q => preset_reg2(0),
      R => \out\
    );
\preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => preset_reg1(1),
      Q => preset_reg2(1),
      R => \out\
    );
\preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => preset_reg1(2),
      Q => preset_reg2(2),
      R => \out\
    );
preset_valid_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => rxeq_preset_valid,
      Q => preset_valid_reg1,
      R => \out\
    );
preset_valid_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => preset_valid_reg1,
      Q => preset_valid_reg2,
      R => \out\
    );
\rxeq_adapt_done_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A800FFFFA8000000"
    )
        port map (
      I0 => rxeqscan_new_txcoeff_done,
      I1 => rxeq_adapt_done_reg_reg_1,
      I2 => rxeqscan_adapt_done,
      I3 => Q(3),
      I4 => rxeq_adapt_done_reg,
      I5 => rxeq_adapt_done_reg_0,
      O => new_txcoeff_done_reg_0
    );
\rxeq_adapt_done_reg_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00FF33AA00A800"
    )
        port map (
      I0 => rxeqscan_adapt_done,
      I1 => rxeq_adapt_done_reg_reg,
      I2 => rxeqscan_new_txcoeff_done,
      I3 => Q(3),
      I4 => rxeq_adapt_done_reg_reg_0,
      I5 => rxeq_adapt_done_reg_reg_1,
      O => adapt_done_reg_0
    );
rxeq_new_txcoeff_req_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => Q(3),
      I1 => rxeqscan_new_txcoeff_done,
      O => rxeq_new_txcoeff_req
    );
\txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(0),
      Q => txcoeff_reg1(0),
      R => \out\
    );
\txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(10),
      Q => txcoeff_reg1(10),
      R => \out\
    );
\txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(11),
      Q => txcoeff_reg1(11),
      R => \out\
    );
\txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(12),
      Q => txcoeff_reg1(12),
      R => \out\
    );
\txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(13),
      Q => txcoeff_reg1(13),
      R => \out\
    );
\txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(14),
      Q => txcoeff_reg1(14),
      R => \out\
    );
\txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(15),
      Q => txcoeff_reg1(15),
      R => \out\
    );
\txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(16),
      Q => txcoeff_reg1(16),
      R => \out\
    );
\txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(17),
      Q => txcoeff_reg1(17),
      R => \out\
    );
\txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(1),
      Q => txcoeff_reg1(1),
      R => \out\
    );
\txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(2),
      Q => txcoeff_reg1(2),
      R => \out\
    );
\txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(3),
      Q => txcoeff_reg1(3),
      R => \out\
    );
\txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(4),
      Q => txcoeff_reg1(4),
      R => \out\
    );
\txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(5),
      Q => txcoeff_reg1(5),
      R => \out\
    );
\txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(6),
      Q => txcoeff_reg1(6),
      R => \out\
    );
\txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(7),
      Q => txcoeff_reg1(7),
      R => \out\
    );
\txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(8),
      Q => txcoeff_reg1(8),
      R => \out\
    );
\txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(9),
      Q => txcoeff_reg1(9),
      R => \out\
    );
\txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(0),
      Q => txcoeff_reg2(0),
      R => \out\
    );
\txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(10),
      Q => txcoeff_reg2(10),
      R => \out\
    );
\txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(11),
      Q => txcoeff_reg2(11),
      R => \out\
    );
\txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(12),
      Q => txcoeff_reg2(12),
      R => \out\
    );
\txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(13),
      Q => txcoeff_reg2(13),
      R => \out\
    );
\txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(14),
      Q => txcoeff_reg2(14),
      R => \out\
    );
\txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(15),
      Q => txcoeff_reg2(15),
      R => \out\
    );
\txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(16),
      Q => txcoeff_reg2(16),
      R => \out\
    );
\txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(17),
      Q => txcoeff_reg2(17),
      R => \out\
    );
\txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(1),
      Q => txcoeff_reg2(1),
      R => \out\
    );
\txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(2),
      Q => txcoeff_reg2(2),
      R => \out\
    );
\txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(3),
      Q => txcoeff_reg2(3),
      R => \out\
    );
\txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(4),
      Q => txcoeff_reg2(4),
      R => \out\
    );
\txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(5),
      Q => txcoeff_reg2(5),
      R => \out\
    );
\txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(6),
      Q => txcoeff_reg2(6),
      R => \out\
    );
\txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(7),
      Q => txcoeff_reg2(7),
      R => \out\
    );
\txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(8),
      Q => txcoeff_reg2(8),
      R => \out\
    );
\txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(9),
      Q => txcoeff_reg2(9),
      R => \out\
    );
\txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txpreset_reg1_reg[3]_0\(0),
      Q => txpreset_reg1(0),
      R => \out\
    );
\txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txpreset_reg1_reg[3]_0\(1),
      Q => txpreset_reg1(1),
      R => \out\
    );
\txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txpreset_reg1_reg[3]_0\(2),
      Q => txpreset_reg1(2),
      R => \out\
    );
\txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txpreset_reg1_reg[3]_0\(3),
      Q => txpreset_reg1(3),
      R => \out\
    );
\txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txpreset_reg1(0),
      Q => txpreset_reg2(0),
      R => \out\
    );
\txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txpreset_reg1(1),
      Q => txpreset_reg2(1),
      R => \out\
    );
\txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txpreset_reg1(2),
      Q => txpreset_reg2(2),
      R => \out\
    );
\txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txpreset_reg1(3),
      Q => txpreset_reg2(3),
      R => \out\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_rxeq_scan_22 is
  port (
    adapt_done_reg_0 : out STD_LOGIC;
    new_txcoeff_done_reg_0 : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 2 downto 0 );
    rxeq_new_txcoeff_req : out STD_LOGIC;
    \out\ : in STD_LOGIC;
    \fs_reg2_reg[5]_0\ : in STD_LOGIC;
    new_txcoeff_req_reg1_reg_0 : in STD_LOGIC;
    rxeq_preset_valid : in STD_LOGIC;
    adapt_done_cnt_reg_0 : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxeq_adapt_done_reg_reg : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 4 downto 0 );
    rxeq_adapt_done_reg_reg_0 : in STD_LOGIC;
    rxeq_adapt_done_reg_reg_1 : in STD_LOGIC;
    rxeq_adapt_done_reg : in STD_LOGIC;
    rxeq_adapt_done_reg_0 : in STD_LOGIC;
    \FSM_onehot_fsm_rx_reg[5]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \preset_reg1_reg[2]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
    \txpreset_reg1_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
    \txcoeff_reg1_reg[17]_0\ : in STD_LOGIC_VECTOR ( 17 downto 0 );
    \fs_reg1_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
    \lf_reg1_reg[5]_0\ : in STD_LOGIC_VECTOR ( 5 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_rxeq_scan_22 : entity is "spec7_pcie_7x_0_rxeq_scan";
end spec7_pcie_7x_0_spec7_pcie_7x_0_rxeq_scan_22;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_rxeq_scan_22 is
  signal \FSM_onehot_fsm[1]_i_1__1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[3]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_10_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_11_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_3_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_4_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_5_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_6_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_7_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_8_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm[4]_i_9_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[1]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[2]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[3]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_reg_n_0_[4]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx[6]_i_2_n_0\ : STD_LOGIC;
  signal adapt_done : STD_LOGIC;
  signal adapt_done_cnt_i_1_n_0 : STD_LOGIC;
  signal adapt_done_cnt_i_2_n_0 : STD_LOGIC;
  signal adapt_done_cnt_reg_n_0 : STD_LOGIC;
  signal converge_cnt : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal converge_cnt0 : STD_LOGIC_VECTOR ( 21 downto 1 );
  signal converge_cnt_0 : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal \converge_cnt_reg[12]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_2_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_2_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[12]_i_2_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_2_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_2_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[16]_i_2_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[20]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[20]_i_2_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[20]_i_2_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[20]_i_2_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_2_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_2_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[4]_i_2_n_3\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_2_n_0\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_2_n_1\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_2_n_2\ : STD_LOGIC;
  signal \converge_cnt_reg[8]_i_2_n_3\ : STD_LOGIC;
  signal fs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of fs_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of fs_reg1 : signal is "true";
  signal fs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT of fs_reg2 : signal is "NO";
  attribute async_reg of fs_reg2 : signal is "true";
  signal lf_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT of lf_reg1 : signal is "NO";
  attribute async_reg of lf_reg1 : signal is "true";
  signal lf_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT of lf_reg2 : signal is "NO";
  attribute async_reg of lf_reg2 : signal is "true";
  signal new_txcoeff_done : STD_LOGIC;
  signal new_txcoeff_req_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of new_txcoeff_req_reg1 : signal is "NO";
  attribute async_reg of new_txcoeff_req_reg1 : signal is "true";
  signal new_txcoeff_req_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of new_txcoeff_req_reg2 : signal is "NO";
  attribute async_reg of new_txcoeff_req_reg2 : signal is "true";
  signal preset_done : STD_LOGIC;
  signal preset_done_1 : STD_LOGIC;
  signal preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute SHIFT_EXTRACT of preset_reg1 : signal is "NO";
  attribute async_reg of preset_reg1 : signal is "true";
  signal preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute SHIFT_EXTRACT of preset_reg2 : signal is "NO";
  attribute async_reg of preset_reg2 : signal is "true";
  signal preset_valid_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of preset_valid_reg1 : signal is "NO";
  attribute async_reg of preset_valid_reg1 : signal is "true";
  signal preset_valid_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of preset_valid_reg2 : signal is "NO";
  attribute async_reg of preset_valid_reg2 : signal is "true";
  signal rxeqscan_adapt_done : STD_LOGIC;
  signal rxeqscan_new_txcoeff_done : STD_LOGIC;
  signal txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 );
  attribute SHIFT_EXTRACT of txcoeff_reg1 : signal is "NO";
  attribute async_reg of txcoeff_reg1 : signal is "true";
  signal txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 );
  attribute SHIFT_EXTRACT of txcoeff_reg2 : signal is "NO";
  attribute async_reg of txcoeff_reg2 : signal is "true";
  signal txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SHIFT_EXTRACT of txpreset_reg1 : signal is "NO";
  attribute async_reg of txpreset_reg1 : signal is "true";
  signal txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SHIFT_EXTRACT of txpreset_reg2 : signal is "NO";
  attribute async_reg of txpreset_reg2 : signal is "true";
  signal \NLW_converge_cnt_reg[21]_i_2_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \NLW_converge_cnt_reg[21]_i_2_O_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 1 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_fsm[3]_i_2\ : label is "soft_lutpair16";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[1]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[2]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[3]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_reg[4]\ : label is "FSM_PRESET:00100,FSM_CONVERGE:01000,FSM_NEW_TXCOEFF_REQ:10000,FSM_IDLE:00010,iSTATE:00001";
  attribute SOFT_HLUTNM of \FSM_onehot_fsm_rx[6]_i_2\ : label is "soft_lutpair17";
  attribute SOFT_HLUTNM of \converge_cnt[11]_i_1\ : label is "soft_lutpair16";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \fs_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \fs_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg1_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \fs_reg1_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg1_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg2_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \fs_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \fs_reg2_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \fs_reg2_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg1_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \lf_reg1_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg1_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg2_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \lf_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \lf_reg2_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \lf_reg2_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of new_txcoeff_req_reg1_reg : label is std.standard.true;
  attribute KEEP of new_txcoeff_req_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of new_txcoeff_req_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of new_txcoeff_req_reg2_reg : label is std.standard.true;
  attribute KEEP of new_txcoeff_req_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of new_txcoeff_req_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of \preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \preset_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \preset_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \preset_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \preset_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \preset_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \preset_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \preset_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \preset_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of preset_valid_reg1_reg : label is std.standard.true;
  attribute KEEP of preset_valid_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of preset_valid_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of preset_valid_reg2_reg : label is std.standard.true;
  attribute KEEP of preset_valid_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of preset_valid_reg2_reg : label is "NO";
  attribute SOFT_HLUTNM of \rxeq_new_txcoeff_req_i_1__0\ : label is "soft_lutpair17";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[10]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[10]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[11]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[11]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[12]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[12]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[13]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[13]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[14]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[14]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[15]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[15]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[16]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[16]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[16]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[17]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[17]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[17]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[6]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[6]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[7]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[7]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[8]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[8]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg1_reg[9]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg1_reg[9]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[10]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[10]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[11]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[11]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[12]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[12]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[13]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[13]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[14]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[14]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[15]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[15]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[16]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[16]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[16]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[17]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[17]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[17]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[6]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[6]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[7]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[7]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[8]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[8]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txcoeff_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \txcoeff_reg2_reg[9]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txcoeff_reg2_reg[9]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txpreset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txpreset_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txpreset_reg2_reg[3]\ : label is "NO";
begin
\FSM_onehot_fsm[1]_i_1__1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0001FF01AAABFFFB"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I3 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I4 => preset_valid_reg2,
      I5 => new_txcoeff_req_reg2,
      O => \FSM_onehot_fsm[1]_i_1__1_n_0\
    );
\FSM_onehot_fsm[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => preset_valid_reg2,
      I1 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => \FSM_onehot_fsm[2]_i_1__0_n_0\
    );
\FSM_onehot_fsm[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"4F444444"
    )
        port map (
      I0 => \FSM_onehot_fsm[3]_i_2_n_0\,
      I1 => \FSM_onehot_fsm[4]_i_2__0_n_0\,
      I2 => preset_valid_reg2,
      I3 => new_txcoeff_req_reg2,
      I4 => \FSM_onehot_fsm_reg_n_0_[1]\,
      O => \FSM_onehot_fsm[3]_i_1__0_n_0\
    );
\FSM_onehot_fsm[3]_i_2\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"04FF"
    )
        port map (
      I0 => adapt_done_cnt_reg_n_0,
      I1 => adapt_done_cnt_reg_0(1),
      I2 => adapt_done_cnt_reg_0(0),
      I3 => \FSM_onehot_fsm_reg_n_0_[3]\,
      O => \FSM_onehot_fsm[3]_i_2_n_0\
    );
\FSM_onehot_fsm[4]_i_10\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => converge_cnt(20),
      I1 => converge_cnt(1),
      I2 => converge_cnt(21),
      I3 => converge_cnt(4),
      O => \FSM_onehot_fsm[4]_i_10_n_0\
    );
\FSM_onehot_fsm[4]_i_11\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFF7"
    )
        port map (
      I0 => converge_cnt(15),
      I1 => converge_cnt(14),
      I2 => converge_cnt(10),
      I3 => converge_cnt(13),
      O => \FSM_onehot_fsm[4]_i_11_n_0\
    );
\FSM_onehot_fsm[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFF55750000"
    )
        port map (
      I0 => \FSM_onehot_fsm[4]_i_2__0_n_0\,
      I1 => adapt_done_cnt_reg_n_0,
      I2 => adapt_done_cnt_reg_0(1),
      I3 => adapt_done_cnt_reg_0(0),
      I4 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I5 => new_txcoeff_done,
      O => \FSM_onehot_fsm[4]_i_1__0_n_0\
    );
\FSM_onehot_fsm[4]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF4FFFFFFFFFF"
    )
        port map (
      I0 => \FSM_onehot_fsm[4]_i_3_n_0\,
      I1 => \FSM_onehot_fsm[4]_i_4_n_0\,
      I2 => \FSM_onehot_fsm[4]_i_5_n_0\,
      I3 => converge_cnt(11),
      I4 => converge_cnt(5),
      I5 => converge_cnt(16),
      O => \FSM_onehot_fsm[4]_i_2__0_n_0\
    );
\FSM_onehot_fsm[4]_i_3\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000020000000000"
    )
        port map (
      I0 => \FSM_onehot_fsm[4]_i_6_n_0\,
      I1 => \FSM_onehot_fsm[4]_i_7_n_0\,
      I2 => \FSM_onehot_fsm[4]_i_8_n_0\,
      I3 => converge_cnt(15),
      I4 => converge_cnt(1),
      I5 => converge_cnt(3),
      O => \FSM_onehot_fsm[4]_i_3_n_0\
    );
\FSM_onehot_fsm[4]_i_4\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFFFFFE"
    )
        port map (
      I0 => \FSM_onehot_fsm[4]_i_9_n_0\,
      I1 => \FSM_onehot_fsm[4]_i_10_n_0\,
      I2 => \FSM_onehot_fsm[4]_i_11_n_0\,
      I3 => converge_cnt(12),
      I4 => converge_cnt(8),
      I5 => converge_cnt(3),
      O => \FSM_onehot_fsm[4]_i_4_n_0\
    );
\FSM_onehot_fsm[4]_i_5\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"DFFF"
    )
        port map (
      I0 => converge_cnt(17),
      I1 => converge_cnt(7),
      I2 => converge_cnt(18),
      I3 => converge_cnt(9),
      O => \FSM_onehot_fsm[4]_i_5_n_0\
    );
\FSM_onehot_fsm[4]_i_6\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000400000000000"
    )
        port map (
      I0 => adapt_done_cnt_reg_0(0),
      I1 => adapt_done_cnt_reg_0(1),
      I2 => converge_cnt(13),
      I3 => converge_cnt(21),
      I4 => converge_cnt(6),
      I5 => converge_cnt(19),
      O => \FSM_onehot_fsm[4]_i_6_n_0\
    );
\FSM_onehot_fsm[4]_i_7\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFEF"
    )
        port map (
      I0 => converge_cnt(20),
      I1 => converge_cnt(0),
      I2 => converge_cnt(8),
      I3 => converge_cnt(14),
      O => \FSM_onehot_fsm[4]_i_7_n_0\
    );
\FSM_onehot_fsm[4]_i_8\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"FFFD"
    )
        port map (
      I0 => converge_cnt(10),
      I1 => converge_cnt(2),
      I2 => converge_cnt(12),
      I3 => converge_cnt(4),
      O => \FSM_onehot_fsm[4]_i_8_n_0\
    );
\FSM_onehot_fsm[4]_i_9\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F4FFFFFFFFFFFFFF"
    )
        port map (
      I0 => adapt_done_cnt_reg_0(0),
      I1 => adapt_done_cnt_reg_0(1),
      I2 => converge_cnt(6),
      I3 => converge_cnt(19),
      I4 => converge_cnt(2),
      I5 => converge_cnt(0),
      O => \FSM_onehot_fsm[4]_i_9_n_0\
    );
\FSM_onehot_fsm_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[1]_i_1__1_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[1]\,
      S => \out\
    );
\FSM_onehot_fsm_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[2]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[2]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[3]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[3]\,
      R => \out\
    );
\FSM_onehot_fsm_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \FSM_onehot_fsm[4]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_reg_n_0_[4]\,
      R => \out\
    );
\FSM_onehot_fsm_rx[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"40FF4040"
    )
        port map (
      I0 => adapt_done_cnt_reg_0(1),
      I1 => Q(0),
      I2 => adapt_done_cnt_reg_0(0),
      I3 => preset_done,
      I4 => Q(1),
      O => D(0)
    );
\FSM_onehot_fsm_rx[5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"F444444444444444"
    )
        port map (
      I0 => rxeqscan_new_txcoeff_done,
      I1 => Q(3),
      I2 => \FSM_onehot_fsm_rx_reg[5]\(1),
      I3 => \FSM_onehot_fsm_rx_reg[5]\(0),
      I4 => \FSM_onehot_fsm_rx_reg[5]\(2),
      I5 => Q(2),
      O => D(1)
    );
\FSM_onehot_fsm_rx[6]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFE0E0E0"
    )
        port map (
      I0 => adapt_done_cnt_reg_0(0),
      I1 => adapt_done_cnt_reg_0(1),
      I2 => Q(4),
      I3 => preset_done,
      I4 => Q(1),
      I5 => \FSM_onehot_fsm_rx[6]_i_2_n_0\,
      O => D(2)
    );
\FSM_onehot_fsm_rx[6]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => rxeqscan_new_txcoeff_done,
      I1 => Q(3),
      O => \FSM_onehot_fsm_rx[6]_i_2_n_0\
    );
adapt_done_cnt_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00000AAAFFFF0800"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_0(0),
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_n_0,
      I5 => adapt_done_cnt_i_2_n_0,
      O => adapt_done_cnt_i_1_n_0
    );
adapt_done_cnt_i_2: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00FF0101"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I3 => new_txcoeff_req_reg2,
      I4 => \FSM_onehot_fsm_reg_n_0_[4]\,
      O => adapt_done_cnt_i_2_n_0
    );
adapt_done_cnt_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => adapt_done_cnt_i_1_n_0,
      Q => adapt_done_cnt_reg_n_0,
      R => \out\
    );
adapt_done_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"F8000000"
    )
        port map (
      I0 => adapt_done_cnt_reg_0(0),
      I1 => adapt_done_cnt_reg_0(1),
      I2 => adapt_done_cnt_reg_n_0,
      I3 => new_txcoeff_req_reg2,
      I4 => \FSM_onehot_fsm_reg_n_0_[4]\,
      O => adapt_done
    );
adapt_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => adapt_done,
      Q => rxeqscan_adapt_done,
      R => \out\
    );
\converge_cnt[0]_i_1__1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"44444044"
    )
        port map (
      I0 => converge_cnt(0),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_0(0),
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt_0(0)
    );
\converge_cnt[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(10),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_0(0),
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt_0(10)
    );
\converge_cnt[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(11),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_0(0),
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt_0(11)
    );
\converge_cnt[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(12),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_0(0),
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt_0(12)
    );
\converge_cnt[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(13),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_0(0),
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt_0(13)
    );
\converge_cnt[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(14),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_0(0),
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt_0(14)
    );
\converge_cnt[15]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(15),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_0(0),
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt_0(15)
    );
\converge_cnt[16]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(16),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_0(0),
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt_0(16)
    );
\converge_cnt[17]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(17),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_0(0),
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt_0(17)
    );
\converge_cnt[18]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(18),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_0(0),
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt_0(18)
    );
\converge_cnt[19]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(19),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_0(0),
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt_0(19)
    );
\converge_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(1),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_0(0),
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt_0(1)
    );
\converge_cnt[20]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(20),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_0(0),
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt_0(20)
    );
\converge_cnt[21]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(21),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_0(0),
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt_0(21)
    );
\converge_cnt[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(2),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_0(0),
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt_0(2)
    );
\converge_cnt[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(3),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_0(0),
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt_0(3)
    );
\converge_cnt[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(4),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_0(0),
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt_0(4)
    );
\converge_cnt[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(5),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_0(0),
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt_0(5)
    );
\converge_cnt[6]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(6),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_0(0),
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt_0(6)
    );
\converge_cnt[7]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(7),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_0(0),
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt_0(7)
    );
\converge_cnt[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(8),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_0(0),
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt_0(8)
    );
\converge_cnt[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"88888088"
    )
        port map (
      I0 => converge_cnt0(9),
      I1 => \FSM_onehot_fsm_reg_n_0_[3]\,
      I2 => adapt_done_cnt_reg_0(0),
      I3 => adapt_done_cnt_reg_0(1),
      I4 => adapt_done_cnt_reg_n_0,
      O => converge_cnt_0(9)
    );
\converge_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(0),
      Q => converge_cnt(0),
      R => \out\
    );
\converge_cnt_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(10),
      Q => converge_cnt(10),
      R => \out\
    );
\converge_cnt_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(11),
      Q => converge_cnt(11),
      R => \out\
    );
\converge_cnt_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(12),
      Q => converge_cnt(12),
      R => \out\
    );
\converge_cnt_reg[12]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[8]_i_2_n_0\,
      CO(3) => \converge_cnt_reg[12]_i_2_n_0\,
      CO(2) => \converge_cnt_reg[12]_i_2_n_1\,
      CO(1) => \converge_cnt_reg[12]_i_2_n_2\,
      CO(0) => \converge_cnt_reg[12]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => converge_cnt0(12 downto 9),
      S(3 downto 0) => converge_cnt(12 downto 9)
    );
\converge_cnt_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(13),
      Q => converge_cnt(13),
      R => \out\
    );
\converge_cnt_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(14),
      Q => converge_cnt(14),
      R => \out\
    );
\converge_cnt_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(15),
      Q => converge_cnt(15),
      R => \out\
    );
\converge_cnt_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(16),
      Q => converge_cnt(16),
      R => \out\
    );
\converge_cnt_reg[16]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[12]_i_2_n_0\,
      CO(3) => \converge_cnt_reg[16]_i_2_n_0\,
      CO(2) => \converge_cnt_reg[16]_i_2_n_1\,
      CO(1) => \converge_cnt_reg[16]_i_2_n_2\,
      CO(0) => \converge_cnt_reg[16]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => converge_cnt0(16 downto 13),
      S(3 downto 0) => converge_cnt(16 downto 13)
    );
\converge_cnt_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(17),
      Q => converge_cnt(17),
      R => \out\
    );
\converge_cnt_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(18),
      Q => converge_cnt(18),
      R => \out\
    );
\converge_cnt_reg[19]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(19),
      Q => converge_cnt(19),
      R => \out\
    );
\converge_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(1),
      Q => converge_cnt(1),
      R => \out\
    );
\converge_cnt_reg[20]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(20),
      Q => converge_cnt(20),
      R => \out\
    );
\converge_cnt_reg[20]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[16]_i_2_n_0\,
      CO(3) => \converge_cnt_reg[20]_i_2_n_0\,
      CO(2) => \converge_cnt_reg[20]_i_2_n_1\,
      CO(1) => \converge_cnt_reg[20]_i_2_n_2\,
      CO(0) => \converge_cnt_reg[20]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => converge_cnt0(20 downto 17),
      S(3 downto 0) => converge_cnt(20 downto 17)
    );
\converge_cnt_reg[21]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(21),
      Q => converge_cnt(21),
      R => \out\
    );
\converge_cnt_reg[21]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[20]_i_2_n_0\,
      CO(3 downto 0) => \NLW_converge_cnt_reg[21]_i_2_CO_UNCONNECTED\(3 downto 0),
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 1) => \NLW_converge_cnt_reg[21]_i_2_O_UNCONNECTED\(3 downto 1),
      O(0) => converge_cnt0(21),
      S(3 downto 1) => B"000",
      S(0) => converge_cnt(21)
    );
\converge_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(2),
      Q => converge_cnt(2),
      R => \out\
    );
\converge_cnt_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(3),
      Q => converge_cnt(3),
      R => \out\
    );
\converge_cnt_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(4),
      Q => converge_cnt(4),
      R => \out\
    );
\converge_cnt_reg[4]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => '0',
      CO(3) => \converge_cnt_reg[4]_i_2_n_0\,
      CO(2) => \converge_cnt_reg[4]_i_2_n_1\,
      CO(1) => \converge_cnt_reg[4]_i_2_n_2\,
      CO(0) => \converge_cnt_reg[4]_i_2_n_3\,
      CYINIT => converge_cnt(0),
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => converge_cnt0(4 downto 1),
      S(3 downto 0) => converge_cnt(4 downto 1)
    );
\converge_cnt_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(5),
      Q => converge_cnt(5),
      R => \out\
    );
\converge_cnt_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(6),
      Q => converge_cnt(6),
      R => \out\
    );
\converge_cnt_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(7),
      Q => converge_cnt(7),
      R => \out\
    );
\converge_cnt_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(8),
      Q => converge_cnt(8),
      R => \out\
    );
\converge_cnt_reg[8]_i_2\: unisim.vcomponents.CARRY4
     port map (
      CI => \converge_cnt_reg[4]_i_2_n_0\,
      CO(3) => \converge_cnt_reg[8]_i_2_n_0\,
      CO(2) => \converge_cnt_reg[8]_i_2_n_1\,
      CO(1) => \converge_cnt_reg[8]_i_2_n_2\,
      CO(0) => \converge_cnt_reg[8]_i_2_n_3\,
      CYINIT => '0',
      DI(3 downto 0) => B"0000",
      O(3 downto 0) => converge_cnt0(8 downto 5),
      S(3 downto 0) => converge_cnt(8 downto 5)
    );
\converge_cnt_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => converge_cnt_0(9),
      Q => converge_cnt(9),
      R => \out\
    );
\fs_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \fs_reg1_reg[5]_0\(0),
      Q => fs_reg1(0),
      R => \out\
    );
\fs_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \fs_reg1_reg[5]_0\(1),
      Q => fs_reg1(1),
      R => \out\
    );
\fs_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \fs_reg1_reg[5]_0\(2),
      Q => fs_reg1(2),
      R => \out\
    );
\fs_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \fs_reg1_reg[5]_0\(3),
      Q => fs_reg1(3),
      R => \out\
    );
\fs_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \fs_reg1_reg[5]_0\(4),
      Q => fs_reg1(4),
      R => \out\
    );
\fs_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \fs_reg1_reg[5]_0\(5),
      Q => fs_reg1(5),
      R => \out\
    );
\fs_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => fs_reg1(0),
      Q => fs_reg2(0),
      R => \out\
    );
\fs_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => fs_reg1(1),
      Q => fs_reg2(1),
      R => \out\
    );
\fs_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => fs_reg1(2),
      Q => fs_reg2(2),
      R => \out\
    );
\fs_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => fs_reg1(3),
      Q => fs_reg2(3),
      R => \out\
    );
\fs_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => fs_reg1(4),
      Q => fs_reg2(4),
      R => \out\
    );
\fs_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => fs_reg1(5),
      Q => fs_reg2(5),
      R => \out\
    );
\lf_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \lf_reg1_reg[5]_0\(0),
      Q => lf_reg1(0),
      R => \out\
    );
\lf_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \lf_reg1_reg[5]_0\(1),
      Q => lf_reg1(1),
      R => \out\
    );
\lf_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \lf_reg1_reg[5]_0\(2),
      Q => lf_reg1(2),
      R => \out\
    );
\lf_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \lf_reg1_reg[5]_0\(3),
      Q => lf_reg1(3),
      R => \out\
    );
\lf_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \lf_reg1_reg[5]_0\(4),
      Q => lf_reg1(4),
      R => \out\
    );
\lf_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \lf_reg1_reg[5]_0\(5),
      Q => lf_reg1(5),
      R => \out\
    );
\lf_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => lf_reg1(0),
      Q => lf_reg2(0),
      R => \out\
    );
\lf_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => lf_reg1(1),
      Q => lf_reg2(1),
      R => \out\
    );
\lf_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => lf_reg1(2),
      Q => lf_reg2(2),
      R => \out\
    );
\lf_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => lf_reg1(3),
      Q => lf_reg2(3),
      R => \out\
    );
\lf_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => lf_reg1(4),
      Q => lf_reg2(4),
      R => \out\
    );
\lf_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => lf_reg1(5),
      Q => lf_reg2(5),
      R => \out\
    );
new_txcoeff_done_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[4]\,
      I1 => new_txcoeff_req_reg2,
      O => new_txcoeff_done
    );
new_txcoeff_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => new_txcoeff_done,
      Q => rxeqscan_new_txcoeff_done,
      R => \out\
    );
new_txcoeff_req_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => new_txcoeff_req_reg1_reg_0,
      Q => new_txcoeff_req_reg1,
      R => \out\
    );
new_txcoeff_req_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => new_txcoeff_req_reg1,
      Q => new_txcoeff_req_reg2,
      R => \out\
    );
preset_done_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"EA"
    )
        port map (
      I0 => \FSM_onehot_fsm_reg_n_0_[2]\,
      I1 => \FSM_onehot_fsm_reg_n_0_[1]\,
      I2 => preset_valid_reg2,
      O => preset_done_1
    );
preset_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => preset_done_1,
      Q => preset_done,
      R => \out\
    );
\preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \preset_reg1_reg[2]_0\(0),
      Q => preset_reg1(0),
      R => \out\
    );
\preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \preset_reg1_reg[2]_0\(1),
      Q => preset_reg1(1),
      R => \out\
    );
\preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \preset_reg1_reg[2]_0\(2),
      Q => preset_reg1(2),
      R => \out\
    );
\preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => preset_reg1(0),
      Q => preset_reg2(0),
      R => \out\
    );
\preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => preset_reg1(1),
      Q => preset_reg2(1),
      R => \out\
    );
\preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => preset_reg1(2),
      Q => preset_reg2(2),
      R => \out\
    );
preset_valid_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => rxeq_preset_valid,
      Q => preset_valid_reg1,
      R => \out\
    );
preset_valid_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => preset_valid_reg1,
      Q => preset_valid_reg2,
      R => \out\
    );
rxeq_adapt_done_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A800FFFFA8000000"
    )
        port map (
      I0 => rxeqscan_new_txcoeff_done,
      I1 => rxeq_adapt_done_reg_reg_1,
      I2 => rxeqscan_adapt_done,
      I3 => Q(3),
      I4 => rxeq_adapt_done_reg,
      I5 => rxeq_adapt_done_reg_0,
      O => new_txcoeff_done_reg_0
    );
rxeq_adapt_done_reg_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FF00FF33AA00A800"
    )
        port map (
      I0 => rxeqscan_adapt_done,
      I1 => rxeq_adapt_done_reg_reg,
      I2 => rxeqscan_new_txcoeff_done,
      I3 => Q(3),
      I4 => rxeq_adapt_done_reg_reg_0,
      I5 => rxeq_adapt_done_reg_reg_1,
      O => adapt_done_reg_0
    );
\rxeq_new_txcoeff_req_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => Q(3),
      I1 => rxeqscan_new_txcoeff_done,
      O => rxeq_new_txcoeff_req
    );
\txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(0),
      Q => txcoeff_reg1(0),
      R => \out\
    );
\txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(10),
      Q => txcoeff_reg1(10),
      R => \out\
    );
\txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(11),
      Q => txcoeff_reg1(11),
      R => \out\
    );
\txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(12),
      Q => txcoeff_reg1(12),
      R => \out\
    );
\txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(13),
      Q => txcoeff_reg1(13),
      R => \out\
    );
\txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(14),
      Q => txcoeff_reg1(14),
      R => \out\
    );
\txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(15),
      Q => txcoeff_reg1(15),
      R => \out\
    );
\txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(16),
      Q => txcoeff_reg1(16),
      R => \out\
    );
\txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(17),
      Q => txcoeff_reg1(17),
      R => \out\
    );
\txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(1),
      Q => txcoeff_reg1(1),
      R => \out\
    );
\txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(2),
      Q => txcoeff_reg1(2),
      R => \out\
    );
\txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(3),
      Q => txcoeff_reg1(3),
      R => \out\
    );
\txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(4),
      Q => txcoeff_reg1(4),
      R => \out\
    );
\txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(5),
      Q => txcoeff_reg1(5),
      R => \out\
    );
\txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(6),
      Q => txcoeff_reg1(6),
      R => \out\
    );
\txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(7),
      Q => txcoeff_reg1(7),
      R => \out\
    );
\txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(8),
      Q => txcoeff_reg1(8),
      R => \out\
    );
\txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txcoeff_reg1_reg[17]_0\(9),
      Q => txcoeff_reg1(9),
      R => \out\
    );
\txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(0),
      Q => txcoeff_reg2(0),
      R => \out\
    );
\txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(10),
      Q => txcoeff_reg2(10),
      R => \out\
    );
\txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(11),
      Q => txcoeff_reg2(11),
      R => \out\
    );
\txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(12),
      Q => txcoeff_reg2(12),
      R => \out\
    );
\txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(13),
      Q => txcoeff_reg2(13),
      R => \out\
    );
\txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(14),
      Q => txcoeff_reg2(14),
      R => \out\
    );
\txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(15),
      Q => txcoeff_reg2(15),
      R => \out\
    );
\txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(16),
      Q => txcoeff_reg2(16),
      R => \out\
    );
\txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(17),
      Q => txcoeff_reg2(17),
      R => \out\
    );
\txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(1),
      Q => txcoeff_reg2(1),
      R => \out\
    );
\txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(2),
      Q => txcoeff_reg2(2),
      R => \out\
    );
\txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(3),
      Q => txcoeff_reg2(3),
      R => \out\
    );
\txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(4),
      Q => txcoeff_reg2(4),
      R => \out\
    );
\txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(5),
      Q => txcoeff_reg2(5),
      R => \out\
    );
\txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(6),
      Q => txcoeff_reg2(6),
      R => \out\
    );
\txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(7),
      Q => txcoeff_reg2(7),
      R => \out\
    );
\txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(8),
      Q => txcoeff_reg2(8),
      R => \out\
    );
\txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txcoeff_reg1(9),
      Q => txcoeff_reg2(9),
      R => \out\
    );
\txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txpreset_reg1_reg[3]_0\(0),
      Q => txpreset_reg1(0),
      R => \out\
    );
\txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txpreset_reg1_reg[3]_0\(1),
      Q => txpreset_reg1(1),
      R => \out\
    );
\txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txpreset_reg1_reg[3]_0\(2),
      Q => txpreset_reg1(2),
      R => \out\
    );
\txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => \txpreset_reg1_reg[3]_0\(3),
      Q => txpreset_reg1(3),
      R => \out\
    );
\txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txpreset_reg1(0),
      Q => txpreset_reg2(0),
      R => \out\
    );
\txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txpreset_reg1(1),
      Q => txpreset_reg2(1),
      R => \out\
    );
\txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txpreset_reg1(2),
      Q => txpreset_reg2(2),
      R => \out\
    );
\txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]_0\,
      CE => '1',
      D => txpreset_reg1(3),
      Q => txpreset_reg2(3),
      R => \out\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO is
  port (
    rdata : out STD_LOGIC_VECTOR ( 14 downto 0 );
    CLK : in STD_LOGIC;
    mim_tx_wen : in STD_LOGIC;
    mim_tx_ren : in STD_LOGIC;
    MIMTXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMTXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    wdata : in STD_LOGIC_VECTOR ( 14 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO : entity is "unimacro_BRAM_TDP_MACRO";
end spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO;

architecture STRUCTURE of spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO is
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_52\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_53\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_74\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute box_type : string;
  attribute box_type of \ramb_bl.ramb36_dp_bl.ram36_bl\ : label is "PRIMITIVE";
begin
\ramb_bl.ramb36_dp_bl.ram36_bl\: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      IS_CLKARDCLK_INVERTED => '0',
      IS_CLKBWRCLK_INVERTED => '0',
      IS_ENARDEN_INVERTED => '0',
      IS_ENBWREN_INVERTED => '0',
      IS_RSTRAMARSTRAM_INVERTED => '0',
      IS_RSTRAMB_INVERTED => '0',
      IS_RSTREGARSTREG_INVERTED => '0',
      IS_RSTREGB_INVERTED => '0',
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 18,
      READ_WIDTH_B => 18,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "NO_CHANGE",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 18,
      WRITE_WIDTH_B => 18
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14 downto 4) => MIMTXWADDR(10 downto 0),
      ADDRARDADDR(3 downto 0) => B"1111",
      ADDRBWRADDR(15) => '1',
      ADDRBWRADDR(14 downto 4) => MIMTXRADDR(10 downto 0),
      ADDRBWRADDR(3 downto 0) => B"1111",
      CASCADEINA => '0',
      CASCADEINB => '0',
      CASCADEOUTA => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\,
      CASCADEOUTB => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\,
      CLKARDCLK => CLK,
      CLKBWRCLK => CLK,
      DBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\,
      DIADI(31 downto 14) => B"000000000000000000",
      DIADI(13 downto 8) => wdata(14 downto 9),
      DIADI(7 downto 0) => wdata(7 downto 0),
      DIBDI(31 downto 0) => B"00000000000000000000000000000000",
      DIPADIP(3 downto 1) => B"000",
      DIPADIP(0) => wdata(8),
      DIPBDIP(3 downto 0) => B"0000",
      DOADO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\(31 downto 16),
      DOADO(15) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\,
      DOADO(14) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\,
      DOADO(13) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\,
      DOADO(12) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\,
      DOADO(11) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\,
      DOADO(10) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\,
      DOADO(9) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\,
      DOADO(8) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\,
      DOADO(7) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\,
      DOADO(6) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\,
      DOADO(5) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\,
      DOADO(4) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\,
      DOADO(3) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\,
      DOADO(2) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\,
      DOADO(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\,
      DOADO(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\,
      DOBDO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\(31 downto 16),
      DOBDO(15) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_52\,
      DOBDO(14) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_53\,
      DOBDO(13 downto 8) => rdata(14 downto 9),
      DOBDO(7 downto 0) => rdata(7 downto 0),
      DOPADOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\(3 downto 2),
      DOPADOP(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\,
      DOPADOP(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\,
      DOPBDOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\(3 downto 2),
      DOPBDOP(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_74\,
      DOPBDOP(0) => rdata(8),
      ECCPARITY(7 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\(7 downto 0),
      ENARDEN => mim_tx_wen,
      ENBWREN => mim_tx_ren,
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '0',
      REGCEB => '1',
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\,
      WEA(3 downto 0) => B"1111",
      WEBWE(7 downto 0) => B"00000000"
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_11 is
  port (
    \ramb_bl.ramb36_dp_bl.ram36_bl_0\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
    CLK : in STD_LOGIC;
    mim_rx_wen : in STD_LOGIC;
    mim_rx_ren : in STD_LOGIC;
    MIMRXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMRXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_1\ : in STD_LOGIC_VECTOR ( 13 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_11 : entity is "unimacro_BRAM_TDP_MACRO";
end spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_11;

architecture STRUCTURE of spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_11 is
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_52\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_53\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_54\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_74\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute box_type : string;
  attribute box_type of \ramb_bl.ramb36_dp_bl.ram36_bl\ : label is "PRIMITIVE";
begin
\ramb_bl.ramb36_dp_bl.ram36_bl\: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      IS_CLKARDCLK_INVERTED => '0',
      IS_CLKBWRCLK_INVERTED => '0',
      IS_ENARDEN_INVERTED => '0',
      IS_ENBWREN_INVERTED => '0',
      IS_RSTRAMARSTRAM_INVERTED => '0',
      IS_RSTRAMB_INVERTED => '0',
      IS_RSTREGARSTREG_INVERTED => '0',
      IS_RSTREGB_INVERTED => '0',
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 18,
      READ_WIDTH_B => 18,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "NO_CHANGE",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 18,
      WRITE_WIDTH_B => 18
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14 downto 4) => MIMRXWADDR(10 downto 0),
      ADDRARDADDR(3 downto 0) => B"1111",
      ADDRBWRADDR(15) => '1',
      ADDRBWRADDR(14 downto 4) => MIMRXRADDR(10 downto 0),
      ADDRBWRADDR(3 downto 0) => B"1111",
      CASCADEINA => '0',
      CASCADEINB => '0',
      CASCADEOUTA => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\,
      CASCADEOUTB => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\,
      CLKARDCLK => CLK,
      CLKBWRCLK => CLK,
      DBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\,
      DIADI(31 downto 13) => B"0000000000000000000",
      DIADI(12 downto 8) => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(13 downto 9),
      DIADI(7 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(7 downto 0),
      DIBDI(31 downto 0) => B"00000000000000000000000000000000",
      DIPADIP(3 downto 1) => B"000",
      DIPADIP(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(8),
      DIPBDIP(3 downto 0) => B"0000",
      DOADO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\(31 downto 16),
      DOADO(15) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\,
      DOADO(14) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\,
      DOADO(13) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\,
      DOADO(12) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\,
      DOADO(11) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\,
      DOADO(10) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\,
      DOADO(9) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\,
      DOADO(8) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\,
      DOADO(7) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\,
      DOADO(6) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\,
      DOADO(5) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\,
      DOADO(4) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\,
      DOADO(3) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\,
      DOADO(2) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\,
      DOADO(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\,
      DOADO(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\,
      DOBDO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\(31 downto 16),
      DOBDO(15) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_52\,
      DOBDO(14) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_53\,
      DOBDO(13) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_54\,
      DOBDO(12 downto 8) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(13 downto 9),
      DOBDO(7 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(7 downto 0),
      DOPADOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\(3 downto 2),
      DOPADOP(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\,
      DOPADOP(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\,
      DOPBDOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\(3 downto 2),
      DOPBDOP(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_74\,
      DOPBDOP(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(8),
      ECCPARITY(7 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\(7 downto 0),
      ENARDEN => mim_rx_wen,
      ENBWREN => mim_rx_ren,
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '0',
      REGCEB => '1',
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\,
      WEA(3 downto 0) => B"1111",
      WEBWE(7 downto 0) => B"00000000"
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_12 is
  port (
    \ramb_bl.ramb36_dp_bl.ram36_bl_0\ : out STD_LOGIC_VECTOR ( 17 downto 0 );
    CLK : in STD_LOGIC;
    mim_rx_wen : in STD_LOGIC;
    mim_rx_ren : in STD_LOGIC;
    MIMRXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMRXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_1\ : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_12 : entity is "unimacro_BRAM_TDP_MACRO";
end spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_12;

architecture STRUCTURE of spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_12 is
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute box_type : string;
  attribute box_type of \ramb_bl.ramb36_dp_bl.ram36_bl\ : label is "PRIMITIVE";
begin
\ramb_bl.ramb36_dp_bl.ram36_bl\: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      IS_CLKARDCLK_INVERTED => '0',
      IS_CLKBWRCLK_INVERTED => '0',
      IS_ENARDEN_INVERTED => '0',
      IS_ENBWREN_INVERTED => '0',
      IS_RSTRAMARSTRAM_INVERTED => '0',
      IS_RSTRAMB_INVERTED => '0',
      IS_RSTREGARSTREG_INVERTED => '0',
      IS_RSTREGB_INVERTED => '0',
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 18,
      READ_WIDTH_B => 18,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "NO_CHANGE",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 18,
      WRITE_WIDTH_B => 18
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14 downto 4) => MIMRXWADDR(10 downto 0),
      ADDRARDADDR(3 downto 0) => B"1111",
      ADDRBWRADDR(15) => '1',
      ADDRBWRADDR(14 downto 4) => MIMRXRADDR(10 downto 0),
      ADDRBWRADDR(3 downto 0) => B"1111",
      CASCADEINA => '0',
      CASCADEINB => '0',
      CASCADEOUTA => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\,
      CASCADEOUTB => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\,
      CLKARDCLK => CLK,
      CLKBWRCLK => CLK,
      DBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\,
      DIADI(31 downto 16) => B"0000000000000000",
      DIADI(15 downto 8) => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(16 downto 9),
      DIADI(7 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(7 downto 0),
      DIBDI(31 downto 0) => B"00000000000000000000000000000000",
      DIPADIP(3 downto 2) => B"00",
      DIPADIP(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(17),
      DIPADIP(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(8),
      DIPBDIP(3 downto 0) => B"0000",
      DOADO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\(31 downto 16),
      DOADO(15) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\,
      DOADO(14) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\,
      DOADO(13) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\,
      DOADO(12) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\,
      DOADO(11) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\,
      DOADO(10) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\,
      DOADO(9) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\,
      DOADO(8) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\,
      DOADO(7) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\,
      DOADO(6) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\,
      DOADO(5) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\,
      DOADO(4) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\,
      DOADO(3) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\,
      DOADO(2) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\,
      DOADO(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\,
      DOADO(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\,
      DOBDO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\(31 downto 16),
      DOBDO(15 downto 8) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(16 downto 9),
      DOBDO(7 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(7 downto 0),
      DOPADOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\(3 downto 2),
      DOPADOP(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\,
      DOPADOP(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\,
      DOPBDOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\(3 downto 2),
      DOPBDOP(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(17),
      DOPBDOP(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(8),
      ECCPARITY(7 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\(7 downto 0),
      ENARDEN => mim_rx_wen,
      ENBWREN => mim_rx_ren,
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '0',
      REGCEB => '1',
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\,
      WEA(3 downto 0) => B"1111",
      WEBWE(7 downto 0) => B"00000000"
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_13 is
  port (
    \ramb_bl.ramb36_dp_bl.ram36_bl_0\ : out STD_LOGIC_VECTOR ( 17 downto 0 );
    CLK : in STD_LOGIC;
    mim_rx_wen : in STD_LOGIC;
    mim_rx_ren : in STD_LOGIC;
    MIMRXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMRXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_1\ : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_13 : entity is "unimacro_BRAM_TDP_MACRO";
end spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_13;

architecture STRUCTURE of spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_13 is
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute box_type : string;
  attribute box_type of \ramb_bl.ramb36_dp_bl.ram36_bl\ : label is "PRIMITIVE";
begin
\ramb_bl.ramb36_dp_bl.ram36_bl\: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      IS_CLKARDCLK_INVERTED => '0',
      IS_CLKBWRCLK_INVERTED => '0',
      IS_ENARDEN_INVERTED => '0',
      IS_ENBWREN_INVERTED => '0',
      IS_RSTRAMARSTRAM_INVERTED => '0',
      IS_RSTRAMB_INVERTED => '0',
      IS_RSTREGARSTREG_INVERTED => '0',
      IS_RSTREGB_INVERTED => '0',
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 18,
      READ_WIDTH_B => 18,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "NO_CHANGE",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 18,
      WRITE_WIDTH_B => 18
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14 downto 4) => MIMRXWADDR(10 downto 0),
      ADDRARDADDR(3 downto 0) => B"1111",
      ADDRBWRADDR(15) => '1',
      ADDRBWRADDR(14 downto 4) => MIMRXRADDR(10 downto 0),
      ADDRBWRADDR(3 downto 0) => B"1111",
      CASCADEINA => '0',
      CASCADEINB => '0',
      CASCADEOUTA => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\,
      CASCADEOUTB => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\,
      CLKARDCLK => CLK,
      CLKBWRCLK => CLK,
      DBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\,
      DIADI(31 downto 16) => B"0000000000000000",
      DIADI(15 downto 8) => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(16 downto 9),
      DIADI(7 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(7 downto 0),
      DIBDI(31 downto 0) => B"00000000000000000000000000000000",
      DIPADIP(3 downto 2) => B"00",
      DIPADIP(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(17),
      DIPADIP(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(8),
      DIPBDIP(3 downto 0) => B"0000",
      DOADO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\(31 downto 16),
      DOADO(15) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\,
      DOADO(14) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\,
      DOADO(13) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\,
      DOADO(12) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\,
      DOADO(11) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\,
      DOADO(10) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\,
      DOADO(9) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\,
      DOADO(8) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\,
      DOADO(7) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\,
      DOADO(6) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\,
      DOADO(5) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\,
      DOADO(4) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\,
      DOADO(3) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\,
      DOADO(2) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\,
      DOADO(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\,
      DOADO(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\,
      DOBDO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\(31 downto 16),
      DOBDO(15 downto 8) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(16 downto 9),
      DOBDO(7 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(7 downto 0),
      DOPADOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\(3 downto 2),
      DOPADOP(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\,
      DOPADOP(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\,
      DOPBDOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\(3 downto 2),
      DOPBDOP(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(17),
      DOPBDOP(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(8),
      ECCPARITY(7 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\(7 downto 0),
      ENARDEN => mim_rx_wen,
      ENBWREN => mim_rx_ren,
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '0',
      REGCEB => '1',
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\,
      WEA(3 downto 0) => B"1111",
      WEBWE(7 downto 0) => B"00000000"
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_14 is
  port (
    \ramb_bl.ramb36_dp_bl.ram36_bl_0\ : out STD_LOGIC_VECTOR ( 17 downto 0 );
    CLK : in STD_LOGIC;
    mim_rx_wen : in STD_LOGIC;
    mim_rx_ren : in STD_LOGIC;
    MIMRXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMRXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_1\ : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_14 : entity is "unimacro_BRAM_TDP_MACRO";
end spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_14;

architecture STRUCTURE of spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_14 is
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute box_type : string;
  attribute box_type of \ramb_bl.ramb36_dp_bl.ram36_bl\ : label is "PRIMITIVE";
begin
\ramb_bl.ramb36_dp_bl.ram36_bl\: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      IS_CLKARDCLK_INVERTED => '0',
      IS_CLKBWRCLK_INVERTED => '0',
      IS_ENARDEN_INVERTED => '0',
      IS_ENBWREN_INVERTED => '0',
      IS_RSTRAMARSTRAM_INVERTED => '0',
      IS_RSTRAMB_INVERTED => '0',
      IS_RSTREGARSTREG_INVERTED => '0',
      IS_RSTREGB_INVERTED => '0',
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 18,
      READ_WIDTH_B => 18,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "NO_CHANGE",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 18,
      WRITE_WIDTH_B => 18
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14 downto 4) => MIMRXWADDR(10 downto 0),
      ADDRARDADDR(3 downto 0) => B"1111",
      ADDRBWRADDR(15) => '1',
      ADDRBWRADDR(14 downto 4) => MIMRXRADDR(10 downto 0),
      ADDRBWRADDR(3 downto 0) => B"1111",
      CASCADEINA => '0',
      CASCADEINB => '0',
      CASCADEOUTA => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\,
      CASCADEOUTB => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\,
      CLKARDCLK => CLK,
      CLKBWRCLK => CLK,
      DBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\,
      DIADI(31 downto 16) => B"0000000000000000",
      DIADI(15 downto 8) => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(16 downto 9),
      DIADI(7 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(7 downto 0),
      DIBDI(31 downto 0) => B"00000000000000000000000000000000",
      DIPADIP(3 downto 2) => B"00",
      DIPADIP(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(17),
      DIPADIP(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_1\(8),
      DIPBDIP(3 downto 0) => B"0000",
      DOADO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\(31 downto 16),
      DOADO(15) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\,
      DOADO(14) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\,
      DOADO(13) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\,
      DOADO(12) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\,
      DOADO(11) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\,
      DOADO(10) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\,
      DOADO(9) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\,
      DOADO(8) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\,
      DOADO(7) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\,
      DOADO(6) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\,
      DOADO(5) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\,
      DOADO(4) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\,
      DOADO(3) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\,
      DOADO(2) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\,
      DOADO(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\,
      DOADO(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\,
      DOBDO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\(31 downto 16),
      DOBDO(15 downto 8) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(16 downto 9),
      DOBDO(7 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(7 downto 0),
      DOPADOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\(3 downto 2),
      DOPADOP(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\,
      DOPADOP(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\,
      DOPBDOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\(3 downto 2),
      DOPBDOP(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(17),
      DOPBDOP(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(8),
      ECCPARITY(7 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\(7 downto 0),
      ENARDEN => mim_rx_wen,
      ENBWREN => mim_rx_ren,
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '0',
      REGCEB => '1',
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\,
      WEA(3 downto 0) => B"1111",
      WEBWE(7 downto 0) => B"00000000"
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_4 is
  port (
    rdata : out STD_LOGIC_VECTOR ( 17 downto 0 );
    CLK : in STD_LOGIC;
    mim_tx_wen : in STD_LOGIC;
    mim_tx_ren : in STD_LOGIC;
    MIMTXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMTXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    wdata : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_4 : entity is "unimacro_BRAM_TDP_MACRO";
end spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_4;

architecture STRUCTURE of spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_4 is
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute box_type : string;
  attribute box_type of \ramb_bl.ramb36_dp_bl.ram36_bl\ : label is "PRIMITIVE";
begin
\ramb_bl.ramb36_dp_bl.ram36_bl\: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      IS_CLKARDCLK_INVERTED => '0',
      IS_CLKBWRCLK_INVERTED => '0',
      IS_ENARDEN_INVERTED => '0',
      IS_ENBWREN_INVERTED => '0',
      IS_RSTRAMARSTRAM_INVERTED => '0',
      IS_RSTRAMB_INVERTED => '0',
      IS_RSTREGARSTREG_INVERTED => '0',
      IS_RSTREGB_INVERTED => '0',
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 18,
      READ_WIDTH_B => 18,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "NO_CHANGE",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 18,
      WRITE_WIDTH_B => 18
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14 downto 4) => MIMTXWADDR(10 downto 0),
      ADDRARDADDR(3 downto 0) => B"1111",
      ADDRBWRADDR(15) => '1',
      ADDRBWRADDR(14 downto 4) => MIMTXRADDR(10 downto 0),
      ADDRBWRADDR(3 downto 0) => B"1111",
      CASCADEINA => '0',
      CASCADEINB => '0',
      CASCADEOUTA => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\,
      CASCADEOUTB => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\,
      CLKARDCLK => CLK,
      CLKBWRCLK => CLK,
      DBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\,
      DIADI(31 downto 16) => B"0000000000000000",
      DIADI(15 downto 8) => wdata(16 downto 9),
      DIADI(7 downto 0) => wdata(7 downto 0),
      DIBDI(31 downto 0) => B"00000000000000000000000000000000",
      DIPADIP(3 downto 2) => B"00",
      DIPADIP(1) => wdata(17),
      DIPADIP(0) => wdata(8),
      DIPBDIP(3 downto 0) => B"0000",
      DOADO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\(31 downto 16),
      DOADO(15) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\,
      DOADO(14) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\,
      DOADO(13) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\,
      DOADO(12) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\,
      DOADO(11) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\,
      DOADO(10) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\,
      DOADO(9) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\,
      DOADO(8) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\,
      DOADO(7) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\,
      DOADO(6) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\,
      DOADO(5) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\,
      DOADO(4) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\,
      DOADO(3) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\,
      DOADO(2) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\,
      DOADO(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\,
      DOADO(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\,
      DOBDO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\(31 downto 16),
      DOBDO(15 downto 8) => rdata(16 downto 9),
      DOBDO(7 downto 0) => rdata(7 downto 0),
      DOPADOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\(3 downto 2),
      DOPADOP(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\,
      DOPADOP(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\,
      DOPBDOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\(3 downto 2),
      DOPBDOP(1) => rdata(17),
      DOPBDOP(0) => rdata(8),
      ECCPARITY(7 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\(7 downto 0),
      ENARDEN => mim_tx_wen,
      ENBWREN => mim_tx_ren,
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '0',
      REGCEB => '1',
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\,
      WEA(3 downto 0) => B"1111",
      WEBWE(7 downto 0) => B"00000000"
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_5 is
  port (
    rdata : out STD_LOGIC_VECTOR ( 17 downto 0 );
    CLK : in STD_LOGIC;
    mim_tx_wen : in STD_LOGIC;
    mim_tx_ren : in STD_LOGIC;
    MIMTXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMTXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    wdata : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_5 : entity is "unimacro_BRAM_TDP_MACRO";
end spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_5;

architecture STRUCTURE of spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_5 is
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute box_type : string;
  attribute box_type of \ramb_bl.ramb36_dp_bl.ram36_bl\ : label is "PRIMITIVE";
begin
\ramb_bl.ramb36_dp_bl.ram36_bl\: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      IS_CLKARDCLK_INVERTED => '0',
      IS_CLKBWRCLK_INVERTED => '0',
      IS_ENARDEN_INVERTED => '0',
      IS_ENBWREN_INVERTED => '0',
      IS_RSTRAMARSTRAM_INVERTED => '0',
      IS_RSTRAMB_INVERTED => '0',
      IS_RSTREGARSTREG_INVERTED => '0',
      IS_RSTREGB_INVERTED => '0',
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 18,
      READ_WIDTH_B => 18,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "NO_CHANGE",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 18,
      WRITE_WIDTH_B => 18
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14 downto 4) => MIMTXWADDR(10 downto 0),
      ADDRARDADDR(3 downto 0) => B"1111",
      ADDRBWRADDR(15) => '1',
      ADDRBWRADDR(14 downto 4) => MIMTXRADDR(10 downto 0),
      ADDRBWRADDR(3 downto 0) => B"1111",
      CASCADEINA => '0',
      CASCADEINB => '0',
      CASCADEOUTA => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\,
      CASCADEOUTB => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\,
      CLKARDCLK => CLK,
      CLKBWRCLK => CLK,
      DBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\,
      DIADI(31 downto 16) => B"0000000000000000",
      DIADI(15 downto 8) => wdata(16 downto 9),
      DIADI(7 downto 0) => wdata(7 downto 0),
      DIBDI(31 downto 0) => B"00000000000000000000000000000000",
      DIPADIP(3 downto 2) => B"00",
      DIPADIP(1) => wdata(17),
      DIPADIP(0) => wdata(8),
      DIPBDIP(3 downto 0) => B"0000",
      DOADO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\(31 downto 16),
      DOADO(15) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\,
      DOADO(14) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\,
      DOADO(13) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\,
      DOADO(12) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\,
      DOADO(11) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\,
      DOADO(10) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\,
      DOADO(9) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\,
      DOADO(8) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\,
      DOADO(7) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\,
      DOADO(6) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\,
      DOADO(5) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\,
      DOADO(4) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\,
      DOADO(3) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\,
      DOADO(2) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\,
      DOADO(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\,
      DOADO(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\,
      DOBDO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\(31 downto 16),
      DOBDO(15 downto 8) => rdata(16 downto 9),
      DOBDO(7 downto 0) => rdata(7 downto 0),
      DOPADOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\(3 downto 2),
      DOPADOP(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\,
      DOPADOP(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\,
      DOPBDOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\(3 downto 2),
      DOPBDOP(1) => rdata(17),
      DOPBDOP(0) => rdata(8),
      ECCPARITY(7 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\(7 downto 0),
      ENARDEN => mim_tx_wen,
      ENBWREN => mim_tx_ren,
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '0',
      REGCEB => '1',
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\,
      WEA(3 downto 0) => B"1111",
      WEBWE(7 downto 0) => B"00000000"
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_6 is
  port (
    rdata : out STD_LOGIC_VECTOR ( 17 downto 0 );
    CLK : in STD_LOGIC;
    mim_tx_wen : in STD_LOGIC;
    mim_tx_ren : in STD_LOGIC;
    MIMTXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMTXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    wdata : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_6 : entity is "unimacro_BRAM_TDP_MACRO";
end spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_6;

architecture STRUCTURE of spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_6 is
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\ : STD_LOGIC;
  signal \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
  attribute box_type : string;
  attribute box_type of \ramb_bl.ramb36_dp_bl.ram36_bl\ : label is "PRIMITIVE";
begin
\ramb_bl.ramb36_dp_bl.ram36_bl\: unisim.vcomponents.RAMB36E1
    generic map(
      DOA_REG => 0,
      DOB_REG => 1,
      EN_ECC_READ => false,
      EN_ECC_WRITE => false,
      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_40 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_41 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_42 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_43 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_44 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_46 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_47 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_48 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_49 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_4F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_50 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_51 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_52 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_53 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_54 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_55 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_56 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_57 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_58 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_5F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_60 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_61 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_62 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_63 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_A => X"000000000",
      INIT_B => X"000000000",
      INIT_FILE => "NONE",
      IS_CLKARDCLK_INVERTED => '0',
      IS_CLKBWRCLK_INVERTED => '0',
      IS_ENARDEN_INVERTED => '0',
      IS_ENBWREN_INVERTED => '0',
      IS_RSTRAMARSTRAM_INVERTED => '0',
      IS_RSTRAMB_INVERTED => '0',
      IS_RSTREGARSTREG_INVERTED => '0',
      IS_RSTREGB_INVERTED => '0',
      RAM_EXTENSION_A => "NONE",
      RAM_EXTENSION_B => "NONE",
      RAM_MODE => "TDP",
      RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE",
      READ_WIDTH_A => 18,
      READ_WIDTH_B => 18,
      RSTREG_PRIORITY_A => "RSTREG",
      RSTREG_PRIORITY_B => "RSTREG",
      SIM_COLLISION_CHECK => "ALL",
      SIM_DEVICE => "7SERIES",
      SRVAL_A => X"000000000",
      SRVAL_B => X"000000000",
      WRITE_MODE_A => "NO_CHANGE",
      WRITE_MODE_B => "WRITE_FIRST",
      WRITE_WIDTH_A => 18,
      WRITE_WIDTH_B => 18
    )
        port map (
      ADDRARDADDR(15) => '1',
      ADDRARDADDR(14 downto 4) => MIMTXWADDR(10 downto 0),
      ADDRARDADDR(3 downto 0) => B"1111",
      ADDRBWRADDR(15) => '1',
      ADDRBWRADDR(14 downto 4) => MIMTXRADDR(10 downto 0),
      ADDRBWRADDR(3 downto 0) => B"1111",
      CASCADEINA => '0',
      CASCADEINB => '0',
      CASCADEOUTA => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTA_UNCONNECTED\,
      CASCADEOUTB => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_CASCADEOUTB_UNCONNECTED\,
      CLKARDCLK => CLK,
      CLKBWRCLK => CLK,
      DBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DBITERR_UNCONNECTED\,
      DIADI(31 downto 16) => B"0000000000000000",
      DIADI(15 downto 8) => wdata(16 downto 9),
      DIADI(7 downto 0) => wdata(7 downto 0),
      DIBDI(31 downto 0) => B"00000000000000000000000000000000",
      DIPADIP(3 downto 2) => B"00",
      DIPADIP(1) => wdata(17),
      DIPADIP(0) => wdata(8),
      DIPBDIP(3 downto 0) => B"0000",
      DOADO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOADO_UNCONNECTED\(31 downto 16),
      DOADO(15) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_20\,
      DOADO(14) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_21\,
      DOADO(13) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_22\,
      DOADO(12) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_23\,
      DOADO(11) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_24\,
      DOADO(10) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_25\,
      DOADO(9) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_26\,
      DOADO(8) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_27\,
      DOADO(7) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_28\,
      DOADO(6) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_29\,
      DOADO(5) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_30\,
      DOADO(4) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_31\,
      DOADO(3) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_32\,
      DOADO(2) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_33\,
      DOADO(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_34\,
      DOADO(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_35\,
      DOBDO(31 downto 16) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOBDO_UNCONNECTED\(31 downto 16),
      DOBDO(15 downto 8) => rdata(16 downto 9),
      DOBDO(7 downto 0) => rdata(7 downto 0),
      DOPADOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPADOP_UNCONNECTED\(3 downto 2),
      DOPADOP(1) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_70\,
      DOPADOP(0) => \ramb_bl.ramb36_dp_bl.ram36_bl_n_71\,
      DOPBDOP(3 downto 2) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_DOPBDOP_UNCONNECTED\(3 downto 2),
      DOPBDOP(1) => rdata(17),
      DOPBDOP(0) => rdata(8),
      ECCPARITY(7 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_ECCPARITY_UNCONNECTED\(7 downto 0),
      ENARDEN => mim_tx_wen,
      ENBWREN => mim_tx_ren,
      INJECTDBITERR => '0',
      INJECTSBITERR => '0',
      RDADDRECC(8 downto 0) => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_RDADDRECC_UNCONNECTED\(8 downto 0),
      REGCEAREGCE => '0',
      REGCEB => '1',
      RSTRAMARSTRAM => '0',
      RSTRAMB => '0',
      RSTREGARSTREG => '0',
      RSTREGB => '0',
      SBITERR => \NLW_ramb_bl.ramb36_dp_bl.ram36_bl_SBITERR_UNCONNECTED\,
      WEA(3 downto 0) => B"1111",
      WEBWE(7 downto 0) => B"00000000"
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_xpm_cdc_single is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of spec7_pcie_7x_0_xpm_cdc_single : entity is 2;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of spec7_pcie_7x_0_xpm_cdc_single : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_xpm_cdc_single : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of spec7_pcie_7x_0_xpm_cdc_single : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of spec7_pcie_7x_0_xpm_cdc_single : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of spec7_pcie_7x_0_xpm_cdc_single : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of spec7_pcie_7x_0_xpm_cdc_single : entity is "TRUE";
  attribute xpm_cdc : string;
  attribute xpm_cdc of spec7_pcie_7x_0_xpm_cdc_single : entity is "SINGLE";
end spec7_pcie_7x_0_xpm_cdc_single;

architecture STRUCTURE of spec7_pcie_7x_0_xpm_cdc_single is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(1);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \spec7_pcie_7x_0_xpm_cdc_single__2\ is
  port (
    src_clk : in STD_LOGIC;
    src_in : in STD_LOGIC;
    dest_clk : in STD_LOGIC;
    dest_out : out STD_LOGIC
  );
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of \spec7_pcie_7x_0_xpm_cdc_single__2\ : entity is 2;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of \spec7_pcie_7x_0_xpm_cdc_single__2\ : entity is 0;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of \spec7_pcie_7x_0_xpm_cdc_single__2\ : entity is "xpm_cdc_single";
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of \spec7_pcie_7x_0_xpm_cdc_single__2\ : entity is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of \spec7_pcie_7x_0_xpm_cdc_single__2\ : entity is 0;
  attribute VERSION : integer;
  attribute VERSION of \spec7_pcie_7x_0_xpm_cdc_single__2\ : entity is 0;
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of \spec7_pcie_7x_0_xpm_cdc_single__2\ : entity is "TRUE";
  attribute xpm_cdc : string;
  attribute xpm_cdc of \spec7_pcie_7x_0_xpm_cdc_single__2\ : entity is "SINGLE";
end \spec7_pcie_7x_0_xpm_cdc_single__2\;

architecture STRUCTURE of \spec7_pcie_7x_0_xpm_cdc_single__2\ is
  signal syncstages_ff : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of syncstages_ff : signal is "true";
  attribute async_reg : string;
  attribute async_reg of syncstages_ff : signal is "true";
  attribute xpm_cdc of syncstages_ff : signal is "SINGLE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[0]\ : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of \syncstages_ff_reg[0]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[0]\ : label is "SINGLE";
  attribute ASYNC_REG_boolean of \syncstages_ff_reg[1]\ : label is std.standard.true;
  attribute KEEP of \syncstages_ff_reg[1]\ : label is "true";
  attribute XPM_CDC of \syncstages_ff_reg[1]\ : label is "SINGLE";
begin
  dest_out <= syncstages_ff(1);
\syncstages_ff_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => src_in,
      Q => syncstages_ff(0),
      R => '0'
    );
\syncstages_ff_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => dest_clk,
      CE => '1',
      D => syncstages_ff(0),
      Q => syncstages_ff(1),
      R => '0'
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_rx is
  port (
    trn_rsrc_dsc_d : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axis_rx_tvalid_xhdl2_reg : out STD_LOGIC;
    m_axis_rx_tlast : out STD_LOGIC;
    trn_in_packet : out STD_LOGIC;
    reg_dsc_detect_reg : out STD_LOGIC;
    m_axis_rx_tuser : out STD_LOGIC_VECTOR ( 12 downto 0 );
    m_axis_rx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_rx_tkeep : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \trn_rbar_hit_prev_reg[0]\ : in STD_LOGIC;
    CLK : in STD_LOGIC;
    trn_rsrc_dsc : in STD_LOGIC;
    rsrc_rdy_filtered6_out : in STD_LOGIC;
    trn_rrem : in STD_LOGIC_VECTOR ( 0 to 0 );
    trn_reof : in STD_LOGIC;
    trn_rsrc_dsc_prev0 : in STD_LOGIC;
    trn_rsof : in STD_LOGIC;
    trn_recrc_err : in STD_LOGIC;
    trn_rerrfwd : in STD_LOGIC;
    trn_in_packet_reg : in STD_LOGIC;
    m_axis_rx_tready : in STD_LOGIC;
    dsc_detect : in STD_LOGIC;
    trn_rd : in STD_LOGIC_VECTOR ( 63 downto 0 );
    trn_rbar_hit : in STD_LOGIC_VECTOR ( 6 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_rx : entity is "spec7_pcie_7x_0_axi_basic_rx";
end spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_rx;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_rx is
  signal \^m_axis_rx_tuser\ : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal m_axis_rx_tuser_xhdl1 : STD_LOGIC_VECTOR ( 21 to 21 );
  signal \^m_axis_rx_tvalid_xhdl2_reg\ : STD_LOGIC;
  signal null_mux_sel : STD_LOGIC;
  signal payload_len : STD_LOGIC_VECTOR ( 9 downto 5 );
  signal pkt_len_counter : STD_LOGIC_VECTOR ( 1 to 1 );
  signal plusOp : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal rx_null_gen_inst_n_1 : STD_LOGIC;
  signal rx_null_gen_inst_n_2 : STD_LOGIC;
  signal rx_null_gen_inst_n_4 : STD_LOGIC;
  signal rx_null_gen_inst_n_5 : STD_LOGIC;
  signal rx_null_gen_inst_n_6 : STD_LOGIC;
  signal rx_pipeline_inst_n_7 : STD_LOGIC;
  signal rx_pipeline_inst_n_8 : STD_LOGIC;
  signal rx_pipeline_inst_n_9 : STD_LOGIC;
begin
  m_axis_rx_tuser(12 downto 0) <= \^m_axis_rx_tuser\(12 downto 0);
  m_axis_rx_tvalid_xhdl2_reg <= \^m_axis_rx_tvalid_xhdl2_reg\;
rx_null_gen_inst: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_rx_null_gen
     port map (
      CLK => CLK,
      D(1) => m_axis_rx_tuser_xhdl1(21),
      D(0) => rx_null_gen_inst_n_1,
      cur_state_reg_0 => \^m_axis_rx_tvalid_xhdl2_reg\,
      in0(4 downto 0) => plusOp(4 downto 0),
      m_axis_rx_tready => m_axis_rx_tready,
      m_axis_rx_tuser(0) => \^m_axis_rx_tuser\(12),
      \m_axis_rx_tuser_xhdl1_reg[19]\ => rx_pipeline_inst_n_9,
      \m_axis_rx_tuser_xhdl1_reg[21]\ => rx_pipeline_inst_n_8,
      null_mux_sel => null_mux_sel,
      null_mux_sel_reg => rx_null_gen_inst_n_4,
      null_mux_sel_reg_0 => rx_null_gen_inst_n_5,
      null_mux_sel_reg_1 => rx_null_gen_inst_n_6,
      null_mux_sel_reg_2 => rx_pipeline_inst_n_7,
      \reg_pkt_len_counter_reg[0]_0\ => \trn_rbar_hit_prev_reg[0]\,
      \reg_pkt_len_counter_reg[3]_0\(0) => pkt_len_counter(1),
      \reg_pkt_len_counter_reg[9]_0\(4 downto 0) => payload_len(9 downto 5),
      \reg_tkeep[7]_i_7_0\ => rx_null_gen_inst_n_2
    );
rx_pipeline_inst: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_rx_pipeline
     port map (
      CLK => CLK,
      D(1) => m_axis_rx_tuser_xhdl1(21),
      D(0) => rx_null_gen_inst_n_1,
      E(0) => E(0),
      data_prev_reg_0 => rx_pipeline_inst_n_8,
      data_prev_reg_1 => rx_pipeline_inst_n_9,
      dsc_detect => dsc_detect,
      in0(4 downto 0) => plusOp(4 downto 0),
      m_axis_rx_tdata(63 downto 0) => m_axis_rx_tdata(63 downto 0),
      \m_axis_rx_tdata_xhdl0_reg[30]_0\(4 downto 0) => payload_len(9 downto 5),
      m_axis_rx_tkeep(1 downto 0) => m_axis_rx_tkeep(1 downto 0),
      m_axis_rx_tlast => m_axis_rx_tlast,
      m_axis_rx_tready => m_axis_rx_tready,
      m_axis_rx_tuser(12 downto 0) => \^m_axis_rx_tuser\(12 downto 0),
      m_axis_rx_tvalid_xhdl2_reg_0 => \^m_axis_rx_tvalid_xhdl2_reg\,
      null_mux_sel => null_mux_sel,
      null_mux_sel_reg_0 => rx_null_gen_inst_n_4,
      reg_dsc_detect_reg_0 => reg_dsc_detect_reg,
      \reg_tkeep_reg[7]_0\(0) => pkt_len_counter(1),
      reg_tlast_reg_0 => rx_null_gen_inst_n_5,
      rsrc_rdy_filtered6_out => rsrc_rdy_filtered6_out,
      trn_in_packet => trn_in_packet,
      trn_in_packet_reg_0 => trn_in_packet_reg,
      trn_rbar_hit(6 downto 0) => trn_rbar_hit(6 downto 0),
      \trn_rbar_hit_prev_reg[0]_0\ => \trn_rbar_hit_prev_reg[0]\,
      trn_rd(63 downto 0) => trn_rd(63 downto 0),
      trn_rdst_rdy_xhdl4_reg_0 => rx_null_gen_inst_n_2,
      trn_rdst_rdy_xhdl4_reg_1 => rx_null_gen_inst_n_6,
      trn_recrc_err => trn_recrc_err,
      trn_reof => trn_reof,
      trn_rerrfwd => trn_rerrfwd,
      trn_rrem(0) => trn_rrem(0),
      trn_rsof => trn_rsof,
      trn_rsrc_dsc => trn_rsrc_dsc,
      trn_rsrc_dsc_d => trn_rsrc_dsc_d,
      trn_rsrc_dsc_prev0 => trn_rsrc_dsc_prev0,
      user_reset_out_reg => rx_pipeline_inst_n_7
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_tx is
  port (
    trn_teof : out STD_LOGIC;
    trn_tsrc_rdy : out STD_LOGIC;
    trn_trem : out STD_LOGIC_VECTOR ( 0 to 0 );
    reg_tcfg_gnt : out STD_LOGIC;
    tready_thrtl_xhdl1_reg : out STD_LOGIC;
    ppm_L1_thrtl : out STD_LOGIC;
    \xhdl12.xhdl14.xhdl15.reg_to_turnoff_reg\ : out STD_LOGIC;
    lnk_up_thrtl : out STD_LOGIC;
    cfg_pm_turnoff_ok_n : out STD_LOGIC;
    trn_tcfg_gnt : out STD_LOGIC;
    trn_tsof : out STD_LOGIC;
    ppm_L1_trig : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \xhdl12.reg_tuser_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \tbuf_gap_cnt_reg[0]\ : in STD_LOGIC;
    s_axis_tx_tlast : in STD_LOGIC;
    CLK : in STD_LOGIC;
    s_axis_tx_tvalid : in STD_LOGIC;
    s_axis_tx_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
    tx_cfg_gnt : in STD_LOGIC;
    trn_tdst_rdy : in STD_LOGIC;
    trn_tcfg_req : in STD_LOGIC;
    cfg_turnoff_ok : in STD_LOGIC;
    tbuf_av_min_trig : in STD_LOGIC;
    ppm_L1_thrtl_reg : in STD_LOGIC;
    \xhdl12.xhdl14.xhdl15.reg_to_turnoff_reg_0\ : in STD_LOGIC;
    lnk_up_thrtl_reg : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axis_tx_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
    tready_thrtl_xhdl1_i_4 : in STD_LOGIC;
    trn_tbuf_av : in STD_LOGIC_VECTOR ( 5 downto 0 );
    tcfg_req_trig : in STD_LOGIC;
    cfg_pcie_link_state : in STD_LOGIC_VECTOR ( 2 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_tx : entity is "spec7_pcie_7x_0_axi_basic_tx";
end spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_tx;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_tx is
  signal axi_in_packet : STD_LOGIC;
  signal reg_disable_trn : STD_LOGIC;
  signal reg_tsrc_rdy0 : STD_LOGIC;
  signal \^tready_thrtl_xhdl1_reg\ : STD_LOGIC;
  signal \xhdl12.tx_thrl_ctl_inst_n_5\ : STD_LOGIC;
begin
  tready_thrtl_xhdl1_reg <= \^tready_thrtl_xhdl1_reg\;
tx_pipeline_inst: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_tx_pipeline
     port map (
      CLK => CLK,
      Q(63 downto 0) => Q(63 downto 0),
      \TNRTL_CTL_TRN_FLUSH.reg_disable_trn_reg_0\ => \^tready_thrtl_xhdl1_reg\,
      axi_in_packet => axi_in_packet,
      axi_in_packet_reg_0 => \xhdl12.tx_thrl_ctl_inst_n_5\,
      \out\ => \out\,
      reg_disable_trn => reg_disable_trn,
      reg_tsrc_rdy0 => reg_tsrc_rdy0,
      s_axis_tx_tdata(63 downto 0) => s_axis_tx_tdata(63 downto 0),
      s_axis_tx_tkeep(0) => s_axis_tx_tkeep(0),
      s_axis_tx_tlast => s_axis_tx_tlast,
      s_axis_tx_tuser(3 downto 0) => s_axis_tx_tuser(3 downto 0),
      s_axis_tx_tvalid => s_axis_tx_tvalid,
      trn_tdst_rdy => trn_tdst_rdy,
      trn_teof => trn_teof,
      trn_trem(0) => trn_trem(0),
      trn_tsof => trn_tsof,
      trn_tsrc_rdy => trn_tsrc_rdy,
      \xhdl12.reg_tuser_reg[0]_0\ => \tbuf_gap_cnt_reg[0]\,
      \xhdl12.reg_tuser_reg[3]_0\(3 downto 0) => \xhdl12.reg_tuser_reg[3]\(3 downto 0)
    );
\xhdl12.tx_thrl_ctl_inst\: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_tx_thrtl_ctl
     port map (
      CLK => CLK,
      axi_in_packet => axi_in_packet,
      cfg_pcie_link_state(2 downto 0) => cfg_pcie_link_state(2 downto 0),
      cfg_pm_turnoff_ok_n => cfg_pm_turnoff_ok_n,
      cfg_turnoff_ok => cfg_turnoff_ok,
      lnk_up_thrtl => lnk_up_thrtl,
      lnk_up_thrtl_reg_0 => lnk_up_thrtl_reg,
      \out\ => \out\,
      ppm_L1_thrtl => ppm_L1_thrtl,
      ppm_L1_thrtl_reg_0 => ppm_L1_thrtl_reg,
      ppm_L1_trig => ppm_L1_trig,
      reg_disable_trn => reg_disable_trn,
      reg_tcfg_gnt => reg_tcfg_gnt,
      reg_tsrc_rdy0 => reg_tsrc_rdy0,
      s_axis_tx_tdata(3 downto 2) => s_axis_tx_tdata(30 downto 29),
      s_axis_tx_tdata(1) => s_axis_tx_tdata(15),
      s_axis_tx_tdata(0) => s_axis_tx_tdata(0),
      s_axis_tx_tlast => s_axis_tx_tlast,
      s_axis_tx_tlast_0 => \xhdl12.tx_thrl_ctl_inst_n_5\,
      s_axis_tx_tuser(0) => s_axis_tx_tuser(0),
      s_axis_tx_tvalid => s_axis_tx_tvalid,
      tbuf_av_min_trig => tbuf_av_min_trig,
      \tbuf_gap_cnt_reg[0]_0\ => \tbuf_gap_cnt_reg[0]\,
      tcfg_req_trig => tcfg_req_trig,
      tready_thrtl_xhdl1_i_4_0 => tready_thrtl_xhdl1_i_4,
      tready_thrtl_xhdl1_reg_0 => \^tready_thrtl_xhdl1_reg\,
      trn_tbuf_av(5 downto 0) => trn_tbuf_av(5 downto 0),
      trn_tcfg_gnt => trn_tcfg_gnt,
      trn_tcfg_req => trn_tcfg_req,
      trn_tdst_rdy => trn_tdst_rdy,
      tx_cfg_gnt => tx_cfg_gnt,
      \xhdl12.xhdl14.xhdl15.reg_to_turnoff_reg_0\ => \xhdl12.xhdl14.xhdl15.reg_to_turnoff_reg\,
      \xhdl12.xhdl14.xhdl15.reg_to_turnoff_reg_1\ => \xhdl12.xhdl14.xhdl15.reg_to_turnoff_reg_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_gt_common is
  port (
    QPLL_QPLLLOCK : out STD_LOGIC;
    int_qplloutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    int_qplloutrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    QPLL_DRP_DONE : out STD_LOGIC;
    \out\ : in STD_LOGIC;
    CLK : in STD_LOGIC;
    sys_clk : in STD_LOGIC;
    QPLL_QPLLPD : in STD_LOGIC;
    QPLL_QPLLRESET : in STD_LOGIC;
    QRST_DRP_START : in STD_LOGIC;
    QPLL_DRP_GEN3 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_gt_common : entity is "spec7_pcie_7x_0_gt_common";
end spec7_pcie_7x_0_spec7_pcie_7x_0_gt_common;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_gt_common is
  signal \^qpll_qplllock\ : STD_LOGIC;
  signal qpll_drp_addr : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal qpll_drp_di : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal qpll_drp_do : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal qpll_drp_en : STD_LOGIC;
  signal qpll_drp_rdy : STD_LOGIC;
  signal qpll_drp_we : STD_LOGIC;
begin
  QPLL_QPLLLOCK <= \^qpll_qplllock\;
qpll_drp_i: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_qpll_drp
     port map (
      CLK => CLK,
      D(15 downto 0) => qpll_drp_do(15 downto 0),
      Q(4) => qpll_drp_addr(7),
      Q(3) => qpll_drp_addr(5),
      Q(2 downto 0) => qpll_drp_addr(2 downto 0),
      QPLL_DRP_DONE => QPLL_DRP_DONE,
      QPLL_DRP_GEN3 => QPLL_DRP_GEN3,
      QPLL_QPLLLOCK => \^qpll_qplllock\,
      QRST_DRP_START => QRST_DRP_START,
      \di_reg[15]_0\(15 downto 0) => qpll_drp_di(15 downto 0),
      \out\ => \out\,
      qpll_drp_en => qpll_drp_en,
      qpll_drp_rdy => qpll_drp_rdy,
      qpll_drp_we => qpll_drp_we
    );
qpll_wrapper_i: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_qpll_wrapper
     port map (
      CLK => CLK,
      D(15 downto 0) => qpll_drp_do(15 downto 0),
      Q(4) => qpll_drp_addr(7),
      Q(3) => qpll_drp_addr(5),
      Q(2 downto 0) => qpll_drp_addr(2 downto 0),
      QPLL_QPLLLOCK => \^qpll_qplllock\,
      QPLL_QPLLPD => QPLL_QPLLPD,
      QPLL_QPLLRESET => QPLL_QPLLRESET,
      int_qplloutclk_out(0) => int_qplloutclk_out(0),
      int_qplloutrefclk_out(0) => int_qplloutrefclk_out(0),
      qpll_drp_en => qpll_drp_en,
      qpll_drp_rdy => qpll_drp_rdy,
      qpll_drp_we => qpll_drp_we,
      rdy_reg1_reg(15 downto 0) => qpll_drp_di(15 downto 0),
      sys_clk => sys_clk
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_gt_wrapper is
  port (
    cpllrst : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    ext_ch_gt_drprdy : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_eyescandataerror : out STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_txn : out STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_txp : out STD_LOGIC_VECTOR ( 0 to 0 );
    sys_clk_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxcdrlock_0 : out STD_LOGIC;
    pipe_rx0_chanisaligned : out STD_LOGIC;
    pipe_rxcommadet : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxdlysresetdone : out STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_RXELECIDLE : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxphaligndone : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxprbserr : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxratedone_0 : out STD_LOGIC;
    gt_rxresetdone_0 : out STD_LOGIC;
    gt_rxvalid_0 : out STD_LOGIC;
    pipe_txdlysresetdone : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_txoutclk_out : out STD_LOGIC;
    pipe_txphaligndone : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_txphinitdone : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_txratedone_0 : out STD_LOGIC;
    gt_txresetdone_0 : out STD_LOGIC;
    ext_ch_gt_drpdo : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_rxbufstatus : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_rxstatus : out STD_LOGIC_VECTOR ( 2 downto 0 );
    RXCHBONDO : out STD_LOGIC_VECTOR ( 4 downto 0 );
    sys_clk_1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_dmonitorout : out STD_LOGIC_VECTOR ( 7 downto 0 );
    sys_clk_2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxdisperr : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_rxnotintable : out STD_LOGIC_VECTOR ( 7 downto 0 );
    SYNC_TXDLYSRESETDONE : out STD_LOGIC;
    SYNC_RXDLYSRESETDONE : out STD_LOGIC;
    gt_rxvalid_q_reg : out STD_LOGIC_VECTOR ( 2 downto 0 );
    gt_cpllpdrefclk : in STD_LOGIC;
    CPLLRESET0 : in STD_LOGIC;
    CLK : in STD_LOGIC;
    drp_mux_en_0 : in STD_LOGIC;
    drp_mux_we_0 : in STD_LOGIC;
    sys_clk : in STD_LOGIC;
    rst_gtreset : in STD_LOGIC;
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 0 to 0 );
    int_qplloutclk_out : in STD_LOGIC_VECTOR ( 0 to 0 );
    int_qplloutrefclk_out : in STD_LOGIC_VECTOR ( 0 to 0 );
    rxchbonden_0 : in STD_LOGIC;
    \cplllock_reg1_reg[0]\ : in STD_LOGIC;
    rate_rxpmareset_0 : in STD_LOGIC;
    pipe_rx0_polarity : in STD_LOGIC;
    rst_userrdy : in STD_LOGIC;
    \cplllock_reg1_reg[0]_0\ : in STD_LOGIC;
    pipe_tx_deemph : in STD_LOGIC;
    pipe_tx_rcvr_det : in STD_LOGIC;
    sync_txdlyen_0 : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_tx0_elec_idle : in STD_LOGIC;
    pipe_txinhibit : in STD_LOGIC_VECTOR ( 0 to 0 );
    DRPDI : in STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_tx0_powerdown : in STD_LOGIC_VECTOR ( 1 downto 0 );
    RXSYSCLKSEL : in STD_LOGIC_VECTOR ( 0 to 0 );
    RXRATE : in STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_tx_margin : in STD_LOGIC_VECTOR ( 2 downto 0 );
    CLKRSVD : in STD_LOGIC_VECTOR ( 0 to 0 );
    TXPOSTCURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 );
    TXPRECURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 );
    pipe_tx0_data : in STD_LOGIC_VECTOR ( 15 downto 0 );
    TXMAINCURSOR : in STD_LOGIC_VECTOR ( 6 downto 0 );
    pipe_tx0_compliance : in STD_LOGIC;
    pipe_tx0_char_is_k : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DRPADDR : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rate_cpllpd_0 : in STD_LOGIC;
    txdlysresetdone_reg1_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    rxdlysresetdone_reg1_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gt_rx_status_q_reg[2]\ : in STD_LOGIC;
    \gt_rx_status_q_reg[0]\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_gt_wrapper : entity is "spec7_pcie_7x_0_gt_wrapper";
end spec7_pcie_7x_0_spec7_pcie_7x_0_gt_wrapper;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_gt_wrapper is
  signal CPLLPD0 : STD_LOGIC;
  signal PIPE_RXDATA : STD_LOGIC_VECTOR ( 31 downto 16 );
  signal PIPE_RXDATAK : STD_LOGIC_VECTOR ( 3 downto 2 );
  signal \gtx_channel.gtxe2_channel_i_n_10\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_189\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_190\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_191\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_192\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_9\ : STD_LOGIC;
  signal \^pipe_rxdlysresetdone\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^pipe_rxstatus\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \^pipe_txdlysresetdone\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 32 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \gt_rx_status_q[0]_i_1__0\ : label is "soft_lutpair8";
  attribute SOFT_HLUTNM of \gt_rx_status_q[1]_i_1__0\ : label is "soft_lutpair8";
  attribute box_type : string;
  attribute box_type of \gtx_channel.gtxe2_channel_i\ : label is "PRIMITIVE";
begin
  pipe_rxdlysresetdone(0) <= \^pipe_rxdlysresetdone\(0);
  pipe_rxstatus(2 downto 0) <= \^pipe_rxstatus\(2 downto 0);
  pipe_txdlysresetdone(0) <= \^pipe_txdlysresetdone\(0);
cpllPDInst: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_gtx_cpllpd_ovrd_23
     port map (
      CPLLPD0 => CPLLPD0,
      cpllrst => cpllrst,
      gt_cpllpdrefclk => gt_cpllpdrefclk,
      rate_cpllpd_0 => rate_cpllpd_0
    );
\gt_rx_status_q[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \^pipe_rxstatus\(0),
      I1 => \gt_rx_status_q_reg[2]\,
      I2 => \gt_rx_status_q_reg[0]\,
      O => gt_rxvalid_q_reg(0)
    );
\gt_rx_status_q[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \^pipe_rxstatus\(1),
      I1 => \gt_rx_status_q_reg[2]\,
      I2 => \gt_rx_status_q_reg[0]\,
      O => gt_rxvalid_q_reg(1)
    );
\gt_rx_status_q[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \^pipe_rxstatus\(2),
      I1 => \gt_rx_status_q_reg[2]\,
      I2 => \gt_rx_status_q_reg[0]\,
      O => gt_rxvalid_q_reg(2)
    );
\gtx_channel.gtxe2_channel_i\: unisim.vcomponents.GTXE2_CHANNEL
    generic map(
      ALIGN_COMMA_DOUBLE => "FALSE",
      ALIGN_COMMA_ENABLE => B"1111111111",
      ALIGN_COMMA_WORD => 1,
      ALIGN_MCOMMA_DET => "TRUE",
      ALIGN_MCOMMA_VALUE => B"1010000011",
      ALIGN_PCOMMA_DET => "TRUE",
      ALIGN_PCOMMA_VALUE => B"0101111100",
      CBCC_DATA_SOURCE_SEL => "DECODED",
      CHAN_BOND_KEEP_ALIGN => "TRUE",
      CHAN_BOND_MAX_SKEW => 7,
      CHAN_BOND_SEQ_1_1 => B"0001001010",
      CHAN_BOND_SEQ_1_2 => B"0001001010",
      CHAN_BOND_SEQ_1_3 => B"0001001010",
      CHAN_BOND_SEQ_1_4 => B"0110111100",
      CHAN_BOND_SEQ_1_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_1 => B"0001000101",
      CHAN_BOND_SEQ_2_2 => B"0001000101",
      CHAN_BOND_SEQ_2_3 => B"0001000101",
      CHAN_BOND_SEQ_2_4 => B"0110111100",
      CHAN_BOND_SEQ_2_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_USE => "TRUE",
      CHAN_BOND_SEQ_LEN => 4,
      CLK_CORRECT_USE => "TRUE",
      CLK_COR_KEEP_IDLE => "TRUE",
      CLK_COR_MAX_LAT => 20,
      CLK_COR_MIN_LAT => 18,
      CLK_COR_PRECEDENCE => "TRUE",
      CLK_COR_REPEAT_WAIT => 0,
      CLK_COR_SEQ_1_1 => B"0100011100",
      CLK_COR_SEQ_1_2 => B"0000000000",
      CLK_COR_SEQ_1_3 => B"0000000000",
      CLK_COR_SEQ_1_4 => B"0000000000",
      CLK_COR_SEQ_1_ENABLE => B"1111",
      CLK_COR_SEQ_2_1 => B"0000000000",
      CLK_COR_SEQ_2_2 => B"0000000000",
      CLK_COR_SEQ_2_3 => B"0000000000",
      CLK_COR_SEQ_2_4 => B"0000000000",
      CLK_COR_SEQ_2_ENABLE => B"0000",
      CLK_COR_SEQ_2_USE => "FALSE",
      CLK_COR_SEQ_LEN => 1,
      CPLL_CFG => X"A407CC",
      CPLL_FBDIV => 5,
      CPLL_FBDIV_45 => 5,
      CPLL_INIT_CFG => X"00001E",
      CPLL_LOCK_CFG => X"01E8",
      CPLL_REFCLK_DIV => 1,
      DEC_MCOMMA_DETECT => "TRUE",
      DEC_PCOMMA_DETECT => "TRUE",
      DEC_VALID_COMMA_ONLY => "FALSE",
      DMONITOR_CFG => X"000B01",
      ES_CONTROL => B"000000",
      ES_ERRDET_EN => "FALSE",
      ES_EYE_SCAN_EN => "FALSE",
      ES_HORZ_OFFSET => X"000",
      ES_PMA_CFG => B"0000000000",
      ES_PRESCALE => B"00000",
      ES_QUALIFIER => X"00000000000000000000",
      ES_QUAL_MASK => X"00000000000000000000",
      ES_SDATA_MASK => X"00000000000000000000",
      ES_VERT_OFFSET => B"000000000",
      FTS_DESKEW_SEQ_ENABLE => B"1111",
      FTS_LANE_DESKEW_CFG => B"1111",
      FTS_LANE_DESKEW_EN => "TRUE",
      GEARBOX_MODE => B"000",
      IS_CPLLLOCKDETCLK_INVERTED => '0',
      IS_DRPCLK_INVERTED => '0',
      IS_GTGREFCLK_INVERTED => '0',
      IS_RXUSRCLK2_INVERTED => '0',
      IS_RXUSRCLK_INVERTED => '0',
      IS_TXPHDLYTSTCLK_INVERTED => '0',
      IS_TXUSRCLK2_INVERTED => '0',
      IS_TXUSRCLK_INVERTED => '0',
      OUTREFCLK_SEL_INV => B"11",
      PCS_PCIE_EN => "TRUE",
      PCS_RSVD_ATTR => X"0000000001CF",
      PD_TRANS_TIME_FROM_P2 => X"03C",
      PD_TRANS_TIME_NONE_P2 => X"09",
      PD_TRANS_TIME_TO_P2 => X"64",
      PMA_RSV => X"00018480",
      PMA_RSV2 => X"2050",
      PMA_RSV3 => B"00",
      PMA_RSV4 => X"00000000",
      RXBUFRESET_TIME => B"00001",
      RXBUF_ADDR_MODE => "FULL",
      RXBUF_EIDLE_HI_CNT => B"0100",
      RXBUF_EIDLE_LO_CNT => B"0000",
      RXBUF_EN => "TRUE",
      RXBUF_RESET_ON_CB_CHANGE => "TRUE",
      RXBUF_RESET_ON_COMMAALIGN => "FALSE",
      RXBUF_RESET_ON_EIDLE => "TRUE",
      RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      RXBUF_THRESH_OVFLW => 61,
      RXBUF_THRESH_OVRD => "FALSE",
      RXBUF_THRESH_UNDFLW => 4,
      RXCDRFREQRESET_TIME => B"00001",
      RXCDRPHRESET_TIME => B"00001",
      RXCDR_CFG => X"03000023FF10200020",
      RXCDR_FR_RESET_ON_EIDLE => '0',
      RXCDR_HOLD_DURING_EIDLE => '1',
      RXCDR_LOCK_CFG => B"010101",
      RXCDR_PH_RESET_ON_EIDLE => '0',
      RXDFELPMRESET_TIME => B"0001111",
      RXDLY_CFG => X"001F",
      RXDLY_LCFG => X"030",
      RXDLY_TAP_CFG => X"0000",
      RXGEARBOX_EN => "FALSE",
      RXISCANRESET_TIME => B"00001",
      RXLPM_HF_CFG => B"00000011110000",
      RXLPM_LF_CFG => B"00000011110000",
      RXOOB_CFG => B"0000110",
      RXOUT_DIV => 2,
      RXPCSRESET_TIME => B"00001",
      RXPHDLY_CFG => X"004020",
      RXPH_CFG => X"000000",
      RXPH_MONITOR_SEL => B"00000",
      RXPMARESET_TIME => B"00011",
      RXPRBS_ERR_LOOPBACK => '0',
      RXSLIDE_AUTO_WAIT => 7,
      RXSLIDE_MODE => "PMA",
      RX_BIAS_CFG => B"000000000100",
      RX_BUFFER_CFG => B"000000",
      RX_CLK25_DIV => 4,
      RX_CLKMUX_PD => '1',
      RX_CM_SEL => B"11",
      RX_CM_TRIM => B"010",
      RX_DATA_WIDTH => 20,
      RX_DDI_SEL => B"000000",
      RX_DEBUG_CFG => B"000000000000",
      RX_DEFER_RESET_BUF_EN => "TRUE",
      RX_DFE_GAIN_CFG => X"020FEA",
      RX_DFE_H2_CFG => B"000000000000",
      RX_DFE_H3_CFG => B"000001000000",
      RX_DFE_H4_CFG => B"00011110000",
      RX_DFE_H5_CFG => B"00011100000",
      RX_DFE_KL_CFG => B"0000011111110",
      RX_DFE_KL_CFG2 => X"3290D86C",
      RX_DFE_LPM_CFG => X"0954",
      RX_DFE_LPM_HOLD_DURING_EIDLE => '1',
      RX_DFE_UT_CFG => B"10001111000000000",
      RX_DFE_VP_CFG => B"00011111100000011",
      RX_DFE_XYD_CFG => B"0000000000000",
      RX_DISPERR_SEQ_MATCH => "TRUE",
      RX_INT_DATAWIDTH => 0,
      RX_OS_CFG => B"0000010000000",
      RX_SIG_VALID_DLY => 4,
      RX_XCLK_SEL => "RXREC",
      SAS_MAX_COM => 64,
      SAS_MIN_COM => 36,
      SATA_BURST_SEQ_LEN => B"1111",
      SATA_BURST_VAL => B"100",
      SATA_CPLL_CFG => "VCO_3000MHZ",
      SATA_EIDLE_VAL => B"100",
      SATA_MAX_BURST => 8,
      SATA_MAX_INIT => 21,
      SATA_MAX_WAKE => 7,
      SATA_MIN_BURST => 4,
      SATA_MIN_INIT => 12,
      SATA_MIN_WAKE => 4,
      SHOW_REALIGN_COMMA => "FALSE",
      SIM_CPLLREFCLK_SEL => B"001",
      SIM_RECEIVER_DETECT_PASS => "TRUE",
      SIM_RESET_SPEEDUP => "FALSE",
      SIM_TX_EIDLE_DRIVE_LEVEL => "1",
      SIM_VERSION => "3.0",
      TERM_RCAL_CFG => B"10000",
      TERM_RCAL_OVRD => '0',
      TRANS_TIME_RATE => X"0E",
      TST_RSV => X"00000000",
      TXBUF_EN => "FALSE",
      TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      TXDLY_CFG => X"001F",
      TXDLY_LCFG => X"030",
      TXDLY_TAP_CFG => X"0000",
      TXGEARBOX_EN => "FALSE",
      TXOUT_DIV => 2,
      TXPCSRESET_TIME => B"00001",
      TXPHDLY_CFG => X"084020",
      TXPH_CFG => X"0780",
      TXPH_MONITOR_SEL => B"00000",
      TXPMARESET_TIME => B"00011",
      TX_CLK25_DIV => 4,
      TX_CLKMUX_PD => '1',
      TX_DATA_WIDTH => 20,
      TX_DEEMPH0 => B"10100",
      TX_DEEMPH1 => B"01011",
      TX_DRIVE_MODE => "PIPE",
      TX_EIDLE_ASSERT_DELAY => B"010",
      TX_EIDLE_DEASSERT_DELAY => B"100",
      TX_INT_DATAWIDTH => 0,
      TX_LOOPBACK_DRIVE_HIZ => "FALSE",
      TX_MAINCURSOR_SEL => '0',
      TX_MARGIN_FULL_0 => B"1001111",
      TX_MARGIN_FULL_1 => B"1001110",
      TX_MARGIN_FULL_2 => B"1001101",
      TX_MARGIN_FULL_3 => B"1001100",
      TX_MARGIN_FULL_4 => B"1000011",
      TX_MARGIN_LOW_0 => B"1000101",
      TX_MARGIN_LOW_1 => B"1000110",
      TX_MARGIN_LOW_2 => B"1000011",
      TX_MARGIN_LOW_3 => B"1000010",
      TX_MARGIN_LOW_4 => B"1000000",
      TX_PREDRIVER_MODE => '0',
      TX_QPI_STATUS_EN => '0',
      TX_RXDETECT_CFG => X"0064",
      TX_RXDETECT_REF => B"011",
      TX_XCLK_SEL => "TXUSR",
      UCODEER_CLR => '0'
    )
        port map (
      CFGRESET => '0',
      CLKRSVD(3 downto 1) => B"000",
      CLKRSVD(0) => CLKRSVD(0),
      CPLLFBCLKLOST => \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED\,
      CPLLLOCK => D(0),
      CPLLLOCKDETCLK => '0',
      CPLLLOCKEN => '1',
      CPLLPD => CPLLPD0,
      CPLLREFCLKLOST => \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED\,
      CPLLREFCLKSEL(2 downto 0) => B"001",
      CPLLRESET => CPLLRESET0,
      DMONITOROUT(7 downto 0) => pipe_dmonitorout(7 downto 0),
      DRPADDR(8 downto 0) => DRPADDR(8 downto 0),
      DRPCLK => CLK,
      DRPDI(15 downto 0) => DRPDI(15 downto 0),
      DRPDO(15 downto 0) => ext_ch_gt_drpdo(15 downto 0),
      DRPEN => drp_mux_en_0,
      DRPRDY => ext_ch_gt_drprdy(0),
      DRPWE => drp_mux_we_0,
      EYESCANDATAERROR => pipe_eyescandataerror(0),
      EYESCANMODE => '0',
      EYESCANRESET => '0',
      EYESCANTRIGGER => '0',
      GTGREFCLK => '0',
      GTNORTHREFCLK0 => '0',
      GTNORTHREFCLK1 => '0',
      GTREFCLK0 => sys_clk,
      GTREFCLK1 => '0',
      GTREFCLKMONITOR => \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED\,
      GTRESETSEL => '0',
      GTRSVD(15 downto 0) => B"0000000000000000",
      GTRXRESET => rst_gtreset,
      GTSOUTHREFCLK0 => '0',
      GTSOUTHREFCLK1 => '0',
      GTTXRESET => rst_gtreset,
      GTXRXN => pci_exp_rxn(0),
      GTXRXP => pci_exp_rxp(0),
      GTXTXN => pci_exp_txn(0),
      GTXTXP => pci_exp_txp(0),
      LOOPBACK(2 downto 0) => B"000",
      PCSRSVDIN(15 downto 0) => B"0000000000000000",
      PCSRSVDIN2(4 downto 0) => B"00000",
      PCSRSVDOUT(15 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED\(15 downto 0),
      PHYSTATUS => sys_clk_0(0),
      PMARSVDIN(4 downto 0) => B"00000",
      PMARSVDIN2(4 downto 0) => B"00000",
      QPLLCLK => int_qplloutclk_out(0),
      QPLLREFCLK => int_qplloutrefclk_out(0),
      RESETOVRD => '0',
      RX8B10BEN => rxchbonden_0,
      RXBUFRESET => '0',
      RXBUFSTATUS(2 downto 0) => pipe_rxbufstatus(2 downto 0),
      RXBYTEISALIGNED => \gtx_channel.gtxe2_channel_i_n_9\,
      RXBYTEREALIGN => \gtx_channel.gtxe2_channel_i_n_10\,
      RXCDRFREQRESET => '0',
      RXCDRHOLD => '0',
      RXCDRLOCK => gt_rxcdrlock_0,
      RXCDROVRDEN => '0',
      RXCDRRESET => '0',
      RXCDRRESETRSV => '0',
      RXCHANBONDSEQ => \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\,
      RXCHANISALIGNED => pipe_rx0_chanisaligned,
      RXCHANREALIGN => \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED\,
      RXCHARISCOMMA(7 downto 4) => \NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED\(7 downto 4),
      RXCHARISCOMMA(3) => \gtx_channel.gtxe2_channel_i_n_189\,
      RXCHARISCOMMA(2) => \gtx_channel.gtxe2_channel_i_n_190\,
      RXCHARISCOMMA(1) => \gtx_channel.gtxe2_channel_i_n_191\,
      RXCHARISCOMMA(0) => \gtx_channel.gtxe2_channel_i_n_192\,
      RXCHARISK(7 downto 4) => \NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED\(7 downto 4),
      RXCHARISK(3 downto 2) => PIPE_RXDATAK(3 downto 2),
      RXCHARISK(1 downto 0) => sys_clk_2(1 downto 0),
      RXCHBONDEN => rxchbonden_0,
      RXCHBONDI(4 downto 0) => B"00000",
      RXCHBONDLEVEL(2 downto 0) => B"001",
      RXCHBONDMASTER => rxchbonden_0,
      RXCHBONDO(4 downto 0) => RXCHBONDO(4 downto 0),
      RXCHBONDSLAVE => '0',
      RXCLKCORCNT(1 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED\(1 downto 0),
      RXCOMINITDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED\,
      RXCOMMADET => pipe_rxcommadet(0),
      RXCOMMADETEN => '1',
      RXCOMSASDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED\,
      RXCOMWAKEDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED\,
      RXDATA(63 downto 32) => \NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED\(63 downto 32),
      RXDATA(31 downto 16) => PIPE_RXDATA(31 downto 16),
      RXDATA(15 downto 0) => sys_clk_1(15 downto 0),
      RXDATAVALID => \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED\,
      RXDDIEN => '0',
      RXDFEAGCHOLD => \cplllock_reg1_reg[0]\,
      RXDFEAGCOVRDEN => '0',
      RXDFECM1EN => '0',
      RXDFELFHOLD => '0',
      RXDFELFOVRDEN => '1',
      RXDFELPMRESET => '0',
      RXDFETAP2HOLD => '0',
      RXDFETAP2OVRDEN => '0',
      RXDFETAP3HOLD => '0',
      RXDFETAP3OVRDEN => '0',
      RXDFETAP4HOLD => '0',
      RXDFETAP4OVRDEN => '0',
      RXDFETAP5HOLD => '0',
      RXDFETAP5OVRDEN => '0',
      RXDFEUTHOLD => '0',
      RXDFEUTOVRDEN => '0',
      RXDFEVPHOLD => '0',
      RXDFEVPOVRDEN => '0',
      RXDFEVSEN => '0',
      RXDFEXYDEN => '0',
      RXDFEXYDHOLD => '0',
      RXDFEXYDOVRDEN => '0',
      RXDISPERR(7 downto 0) => pipe_rxdisperr(7 downto 0),
      RXDLYBYPASS => '1',
      RXDLYEN => '0',
      RXDLYOVRDEN => '0',
      RXDLYSRESET => '0',
      RXDLYSRESETDONE => \^pipe_rxdlysresetdone\(0),
      RXELECIDLE => PIPE_RXELECIDLE(0),
      RXELECIDLEMODE(1 downto 0) => B"00",
      RXGEARBOXSLIP => '0',
      RXHEADER(2 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED\(2 downto 0),
      RXHEADERVALID => \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED\,
      RXLPMEN => rxchbonden_0,
      RXLPMHFHOLD => '0',
      RXLPMHFOVRDEN => '0',
      RXLPMLFHOLD => '0',
      RXLPMLFKLOVRDEN => '0',
      RXMCOMMAALIGNEN => rxchbonden_0,
      RXMONITOROUT(6 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED\(6 downto 0),
      RXMONITORSEL(1 downto 0) => B"00",
      RXNOTINTABLE(7 downto 0) => pipe_rxnotintable(7 downto 0),
      RXOOBRESET => '0',
      RXOSHOLD => '0',
      RXOSOVRDEN => '0',
      RXOUTCLK => pipe_rxoutclk_out(0),
      RXOUTCLKFABRIC => \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\,
      RXOUTCLKPCS => \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED\,
      RXOUTCLKSEL(2 downto 0) => B"000",
      RXPCOMMAALIGNEN => rxchbonden_0,
      RXPCSRESET => '0',
      RXPD(1 downto 0) => pipe_tx0_powerdown(1 downto 0),
      RXPHALIGN => '0',
      RXPHALIGNDONE => pipe_rxphaligndone(0),
      RXPHALIGNEN => '0',
      RXPHDLYPD => '0',
      RXPHDLYRESET => '0',
      RXPHMONITOR(4 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED\(4 downto 0),
      RXPHOVRDEN => '0',
      RXPHSLIPMONITOR(4 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\(4 downto 0),
      RXPMARESET => rate_rxpmareset_0,
      RXPOLARITY => pipe_rx0_polarity,
      RXPRBSCNTRESET => '0',
      RXPRBSERR => pipe_rxprbserr(0),
      RXPRBSSEL(2 downto 0) => B"000",
      RXQPIEN => '0',
      RXQPISENN => \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED\,
      RXQPISENP => \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED\,
      RXRATE(2 downto 1) => B"00",
      RXRATE(0) => RXRATE(0),
      RXRATEDONE => gt_rxratedone_0,
      RXRESETDONE => gt_rxresetdone_0,
      RXSLIDE => '0',
      RXSTARTOFSEQ => \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\,
      RXSTATUS(2 downto 0) => \^pipe_rxstatus\(2 downto 0),
      RXSYSCLKSEL(1) => '0',
      RXSYSCLKSEL(0) => RXSYSCLKSEL(0),
      RXUSERRDY => rst_userrdy,
      RXUSRCLK => \cplllock_reg1_reg[0]_0\,
      RXUSRCLK2 => \cplllock_reg1_reg[0]_0\,
      RXVALID => gt_rxvalid_0,
      SETERRSTATUS => '0',
      TSTIN(19 downto 0) => B"11111111111111111111",
      TSTOUT(9 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED\(9 downto 0),
      TX8B10BBYPASS(7 downto 0) => B"00000000",
      TX8B10BEN => rxchbonden_0,
      TXBUFDIFFCTRL(2 downto 0) => B"100",
      TXBUFSTATUS(1 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED\(1 downto 0),
      TXCHARDISPMODE(7 downto 1) => B"0000000",
      TXCHARDISPMODE(0) => pipe_tx0_compliance,
      TXCHARDISPVAL(7 downto 0) => B"00000000",
      TXCHARISK(7 downto 2) => B"000000",
      TXCHARISK(1 downto 0) => pipe_tx0_char_is_k(1 downto 0),
      TXCOMFINISH => \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED\,
      TXCOMINIT => '0',
      TXCOMSAS => '0',
      TXCOMWAKE => '0',
      TXDATA(63 downto 16) => B"000000000000000000000000000000000000000000000000",
      TXDATA(15 downto 0) => pipe_tx0_data(15 downto 0),
      TXDEEMPH => pipe_tx_deemph,
      TXDETECTRX => pipe_tx_rcvr_det,
      TXDIFFCTRL(3 downto 0) => B"1100",
      TXDIFFPD => '0',
      TXDLYBYPASS => '0',
      TXDLYEN => sync_txdlyen_0,
      TXDLYHOLD => '0',
      TXDLYOVRDEN => '0',
      TXDLYSRESET => Q(0),
      TXDLYSRESETDONE => \^pipe_txdlysresetdone\(0),
      TXDLYUPDOWN => '0',
      TXELECIDLE => pipe_tx0_elec_idle,
      TXGEARBOXREADY => \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED\,
      TXHEADER(2 downto 0) => B"000",
      TXINHIBIT => pipe_txinhibit(0),
      TXMAINCURSOR(6 downto 0) => TXMAINCURSOR(6 downto 0),
      TXMARGIN(2 downto 0) => pipe_tx_margin(2 downto 0),
      TXOUTCLK => pipe_txoutclk_out,
      TXOUTCLKFABRIC => \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\,
      TXOUTCLKPCS => \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED\,
      TXOUTCLKSEL(2 downto 0) => B"011",
      TXPCSRESET => '0',
      TXPD(1 downto 0) => pipe_tx0_powerdown(1 downto 0),
      TXPDELECIDLEMODE => '0',
      TXPHALIGN => Q(2),
      TXPHALIGNDONE => pipe_txphaligndone(0),
      TXPHALIGNEN => '1',
      TXPHDLYPD => '0',
      TXPHDLYRESET => '0',
      TXPHDLYTSTCLK => '0',
      TXPHINIT => Q(1),
      TXPHINITDONE => pipe_txphinitdone(0),
      TXPHOVRDEN => '0',
      TXPISOPD => '0',
      TXPMARESET => rate_rxpmareset_0,
      TXPOLARITY => '0',
      TXPOSTCURSOR(4 downto 0) => TXPOSTCURSOR(4 downto 0),
      TXPOSTCURSORINV => '0',
      TXPRBSFORCEERR => '0',
      TXPRBSSEL(2 downto 0) => B"000",
      TXPRECURSOR(4 downto 0) => TXPRECURSOR(4 downto 0),
      TXPRECURSORINV => '0',
      TXQPIBIASEN => '0',
      TXQPISENN => \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED\,
      TXQPISENP => \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED\,
      TXQPISTRONGPDOWN => '0',
      TXQPIWEAKPUP => '0',
      TXRATE(2 downto 1) => B"00",
      TXRATE(0) => RXRATE(0),
      TXRATEDONE => gt_txratedone_0,
      TXRESETDONE => gt_txresetdone_0,
      TXSEQUENCE(6 downto 0) => B"0000000",
      TXSTARTSEQ => '0',
      TXSWING => '0',
      TXSYSCLKSEL(1) => '0',
      TXSYSCLKSEL(0) => RXSYSCLKSEL(0),
      TXUSERRDY => rst_userrdy,
      TXUSRCLK => \cplllock_reg1_reg[0]_0\,
      TXUSRCLK2 => \cplllock_reg1_reg[0]_0\
    );
rxdlysresetdone_reg1_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^pipe_rxdlysresetdone\(0),
      I1 => rxdlysresetdone_reg1_reg(0),
      O => SYNC_RXDLYSRESETDONE
    );
txdlysresetdone_reg1_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^pipe_txdlysresetdone\(0),
      I1 => txdlysresetdone_reg1_reg(0),
      O => SYNC_TXDLYSRESETDONE
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_gt_wrapper_16 is
  port (
    cpllrst : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 0 to 0 );
    ext_ch_gt_drprdy : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_eyescandataerror : out STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_txn : out STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_txp : out STD_LOGIC_VECTOR ( 0 to 0 );
    sys_clk_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxcdrlock_1 : out STD_LOGIC;
    pipe_rx1_chanisaligned : out STD_LOGIC;
    pipe_rxcommadet : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxdlysresetdone : out STD_LOGIC_VECTOR ( 0 to 0 );
    PIPE_RXELECIDLE : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxphaligndone : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxprbserr : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_rxratedone_1 : out STD_LOGIC;
    gt_rxresetdone_1 : out STD_LOGIC;
    gt_rxvalid_1 : out STD_LOGIC;
    pipe_txdlysresetdone : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_txphaligndone : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_txphinitdone : out STD_LOGIC_VECTOR ( 0 to 0 );
    gt_txratedone_1 : out STD_LOGIC;
    gt_txresetdone_1 : out STD_LOGIC;
    ext_ch_gt_drpdo : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_rxbufstatus : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_rxstatus : out STD_LOGIC_VECTOR ( 2 downto 0 );
    sys_clk_1 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_dmonitorout : out STD_LOGIC_VECTOR ( 7 downto 0 );
    sys_clk_2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxdisperr : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_rxnotintable : out STD_LOGIC_VECTOR ( 7 downto 0 );
    gt_rxvalid_q_reg : out STD_LOGIC_VECTOR ( 2 downto 0 );
    gt_cpllpdrefclk : in STD_LOGIC;
    CPLLRESET0 : in STD_LOGIC;
    CLK : in STD_LOGIC;
    drp_mux_en_1 : in STD_LOGIC;
    drp_mux_we_1 : in STD_LOGIC;
    sys_clk : in STD_LOGIC;
    rst_gtreset : in STD_LOGIC;
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 0 to 0 );
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 0 to 0 );
    int_qplloutclk_out : in STD_LOGIC_VECTOR ( 0 to 0 );
    int_qplloutrefclk_out : in STD_LOGIC_VECTOR ( 0 to 0 );
    rxchbonden_1 : in STD_LOGIC;
    \cplllock_reg1_reg[1]\ : in STD_LOGIC;
    rate_rxpmareset_1 : in STD_LOGIC;
    pipe_rx1_polarity : in STD_LOGIC;
    rst_userrdy : in STD_LOGIC;
    \cplllock_reg1_reg[1]_0\ : in STD_LOGIC;
    pipe_tx_deemph : in STD_LOGIC;
    pipe_tx_rcvr_det : in STD_LOGIC;
    Q : in STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_tx1_elec_idle : in STD_LOGIC;
    pipe_txinhibit : in STD_LOGIC_VECTOR ( 0 to 0 );
    DRPDI : in STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_tx1_powerdown : in STD_LOGIC_VECTOR ( 1 downto 0 );
    RXSYSCLKSEL : in STD_LOGIC_VECTOR ( 0 to 0 );
    RXRATE : in STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_tx_margin : in STD_LOGIC_VECTOR ( 2 downto 0 );
    CLKRSVD : in STD_LOGIC_VECTOR ( 0 to 0 );
    RXCHBONDO : in STD_LOGIC_VECTOR ( 4 downto 0 );
    TXPOSTCURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 );
    TXPRECURSOR : in STD_LOGIC_VECTOR ( 4 downto 0 );
    pipe_tx1_data : in STD_LOGIC_VECTOR ( 15 downto 0 );
    TXMAINCURSOR : in STD_LOGIC_VECTOR ( 6 downto 0 );
    pipe_tx1_compliance : in STD_LOGIC;
    pipe_tx1_char_is_k : in STD_LOGIC_VECTOR ( 1 downto 0 );
    DRPADDR : in STD_LOGIC_VECTOR ( 8 downto 0 );
    rate_cpllpd_1 : in STD_LOGIC;
    \gt_rx_status_q_reg[2]\ : in STD_LOGIC;
    \gt_rx_status_q_reg[0]\ : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_gt_wrapper_16 : entity is "spec7_pcie_7x_0_gt_wrapper";
end spec7_pcie_7x_0_spec7_pcie_7x_0_gt_wrapper_16;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_gt_wrapper_16 is
  signal CPLLPD0 : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_10\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_138\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_139\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_140\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_141\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_142\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_143\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_144\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_145\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_146\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_147\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_148\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_149\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_150\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_151\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_152\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_153\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_189\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_190\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_191\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_192\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_197\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_198\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_37\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_9\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_91\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_92\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_93\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_94\ : STD_LOGIC;
  signal \gtx_channel.gtxe2_channel_i_n_95\ : STD_LOGIC;
  signal \^pipe_rxstatus\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED\ : STD_LOGIC;
  signal \NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 4 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED\ : STD_LOGIC_VECTOR ( 63 downto 32 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal \NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \gt_rx_status_q[0]_i_1\ : label is "soft_lutpair48";
  attribute SOFT_HLUTNM of \gt_rx_status_q[1]_i_1\ : label is "soft_lutpair48";
  attribute box_type : string;
  attribute box_type of \gtx_channel.gtxe2_channel_i\ : label is "PRIMITIVE";
begin
  pipe_rxstatus(2 downto 0) <= \^pipe_rxstatus\(2 downto 0);
cpllPDInst: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_gtx_cpllpd_ovrd
     port map (
      CPLLPD0 => CPLLPD0,
      cpllrst => cpllrst,
      gt_cpllpdrefclk => gt_cpllpdrefclk,
      rate_cpllpd_1 => rate_cpllpd_1
    );
\gt_rx_status_q[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \^pipe_rxstatus\(0),
      I1 => \gt_rx_status_q_reg[2]\,
      I2 => \gt_rx_status_q_reg[0]\,
      O => gt_rxvalid_q_reg(0)
    );
\gt_rx_status_q[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \^pipe_rxstatus\(1),
      I1 => \gt_rx_status_q_reg[2]\,
      I2 => \gt_rx_status_q_reg[0]\,
      O => gt_rxvalid_q_reg(1)
    );
\gt_rx_status_q[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \^pipe_rxstatus\(2),
      I1 => \gt_rx_status_q_reg[2]\,
      I2 => \gt_rx_status_q_reg[0]\,
      O => gt_rxvalid_q_reg(2)
    );
\gtx_channel.gtxe2_channel_i\: unisim.vcomponents.GTXE2_CHANNEL
    generic map(
      ALIGN_COMMA_DOUBLE => "FALSE",
      ALIGN_COMMA_ENABLE => B"1111111111",
      ALIGN_COMMA_WORD => 1,
      ALIGN_MCOMMA_DET => "TRUE",
      ALIGN_MCOMMA_VALUE => B"1010000011",
      ALIGN_PCOMMA_DET => "TRUE",
      ALIGN_PCOMMA_VALUE => B"0101111100",
      CBCC_DATA_SOURCE_SEL => "DECODED",
      CHAN_BOND_KEEP_ALIGN => "TRUE",
      CHAN_BOND_MAX_SKEW => 7,
      CHAN_BOND_SEQ_1_1 => B"0001001010",
      CHAN_BOND_SEQ_1_2 => B"0001001010",
      CHAN_BOND_SEQ_1_3 => B"0001001010",
      CHAN_BOND_SEQ_1_4 => B"0110111100",
      CHAN_BOND_SEQ_1_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_1 => B"0001000101",
      CHAN_BOND_SEQ_2_2 => B"0001000101",
      CHAN_BOND_SEQ_2_3 => B"0001000101",
      CHAN_BOND_SEQ_2_4 => B"0110111100",
      CHAN_BOND_SEQ_2_ENABLE => B"1111",
      CHAN_BOND_SEQ_2_USE => "TRUE",
      CHAN_BOND_SEQ_LEN => 4,
      CLK_CORRECT_USE => "TRUE",
      CLK_COR_KEEP_IDLE => "TRUE",
      CLK_COR_MAX_LAT => 20,
      CLK_COR_MIN_LAT => 18,
      CLK_COR_PRECEDENCE => "TRUE",
      CLK_COR_REPEAT_WAIT => 0,
      CLK_COR_SEQ_1_1 => B"0100011100",
      CLK_COR_SEQ_1_2 => B"0000000000",
      CLK_COR_SEQ_1_3 => B"0000000000",
      CLK_COR_SEQ_1_4 => B"0000000000",
      CLK_COR_SEQ_1_ENABLE => B"1111",
      CLK_COR_SEQ_2_1 => B"0000000000",
      CLK_COR_SEQ_2_2 => B"0000000000",
      CLK_COR_SEQ_2_3 => B"0000000000",
      CLK_COR_SEQ_2_4 => B"0000000000",
      CLK_COR_SEQ_2_ENABLE => B"0000",
      CLK_COR_SEQ_2_USE => "FALSE",
      CLK_COR_SEQ_LEN => 1,
      CPLL_CFG => X"A407CC",
      CPLL_FBDIV => 5,
      CPLL_FBDIV_45 => 5,
      CPLL_INIT_CFG => X"00001E",
      CPLL_LOCK_CFG => X"01E8",
      CPLL_REFCLK_DIV => 1,
      DEC_MCOMMA_DETECT => "TRUE",
      DEC_PCOMMA_DETECT => "TRUE",
      DEC_VALID_COMMA_ONLY => "FALSE",
      DMONITOR_CFG => X"000B01",
      ES_CONTROL => B"000000",
      ES_ERRDET_EN => "FALSE",
      ES_EYE_SCAN_EN => "FALSE",
      ES_HORZ_OFFSET => X"000",
      ES_PMA_CFG => B"0000000000",
      ES_PRESCALE => B"00000",
      ES_QUALIFIER => X"00000000000000000000",
      ES_QUAL_MASK => X"00000000000000000000",
      ES_SDATA_MASK => X"00000000000000000000",
      ES_VERT_OFFSET => B"000000000",
      FTS_DESKEW_SEQ_ENABLE => B"1111",
      FTS_LANE_DESKEW_CFG => B"1111",
      FTS_LANE_DESKEW_EN => "TRUE",
      GEARBOX_MODE => B"000",
      IS_CPLLLOCKDETCLK_INVERTED => '0',
      IS_DRPCLK_INVERTED => '0',
      IS_GTGREFCLK_INVERTED => '0',
      IS_RXUSRCLK2_INVERTED => '0',
      IS_RXUSRCLK_INVERTED => '0',
      IS_TXPHDLYTSTCLK_INVERTED => '0',
      IS_TXUSRCLK2_INVERTED => '0',
      IS_TXUSRCLK_INVERTED => '0',
      OUTREFCLK_SEL_INV => B"11",
      PCS_PCIE_EN => "TRUE",
      PCS_RSVD_ATTR => X"0000000001CF",
      PD_TRANS_TIME_FROM_P2 => X"03C",
      PD_TRANS_TIME_NONE_P2 => X"09",
      PD_TRANS_TIME_TO_P2 => X"64",
      PMA_RSV => X"00018480",
      PMA_RSV2 => X"2050",
      PMA_RSV3 => B"00",
      PMA_RSV4 => X"00000000",
      RXBUFRESET_TIME => B"00001",
      RXBUF_ADDR_MODE => "FULL",
      RXBUF_EIDLE_HI_CNT => B"0100",
      RXBUF_EIDLE_LO_CNT => B"0000",
      RXBUF_EN => "TRUE",
      RXBUF_RESET_ON_CB_CHANGE => "TRUE",
      RXBUF_RESET_ON_COMMAALIGN => "FALSE",
      RXBUF_RESET_ON_EIDLE => "TRUE",
      RXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      RXBUF_THRESH_OVFLW => 61,
      RXBUF_THRESH_OVRD => "FALSE",
      RXBUF_THRESH_UNDFLW => 4,
      RXCDRFREQRESET_TIME => B"00001",
      RXCDRPHRESET_TIME => B"00001",
      RXCDR_CFG => X"03000023FF10200020",
      RXCDR_FR_RESET_ON_EIDLE => '0',
      RXCDR_HOLD_DURING_EIDLE => '1',
      RXCDR_LOCK_CFG => B"010101",
      RXCDR_PH_RESET_ON_EIDLE => '0',
      RXDFELPMRESET_TIME => B"0001111",
      RXDLY_CFG => X"001F",
      RXDLY_LCFG => X"030",
      RXDLY_TAP_CFG => X"0000",
      RXGEARBOX_EN => "FALSE",
      RXISCANRESET_TIME => B"00001",
      RXLPM_HF_CFG => B"00000011110000",
      RXLPM_LF_CFG => B"00000011110000",
      RXOOB_CFG => B"0000110",
      RXOUT_DIV => 2,
      RXPCSRESET_TIME => B"00001",
      RXPHDLY_CFG => X"004020",
      RXPH_CFG => X"000000",
      RXPH_MONITOR_SEL => B"00000",
      RXPMARESET_TIME => B"00011",
      RXPRBS_ERR_LOOPBACK => '0',
      RXSLIDE_AUTO_WAIT => 7,
      RXSLIDE_MODE => "PMA",
      RX_BIAS_CFG => B"000000000100",
      RX_BUFFER_CFG => B"000000",
      RX_CLK25_DIV => 4,
      RX_CLKMUX_PD => '1',
      RX_CM_SEL => B"11",
      RX_CM_TRIM => B"010",
      RX_DATA_WIDTH => 20,
      RX_DDI_SEL => B"000000",
      RX_DEBUG_CFG => B"000000000000",
      RX_DEFER_RESET_BUF_EN => "TRUE",
      RX_DFE_GAIN_CFG => X"020FEA",
      RX_DFE_H2_CFG => B"000000000000",
      RX_DFE_H3_CFG => B"000001000000",
      RX_DFE_H4_CFG => B"00011110000",
      RX_DFE_H5_CFG => B"00011100000",
      RX_DFE_KL_CFG => B"0000011111110",
      RX_DFE_KL_CFG2 => X"3290D86C",
      RX_DFE_LPM_CFG => X"0954",
      RX_DFE_LPM_HOLD_DURING_EIDLE => '1',
      RX_DFE_UT_CFG => B"10001111000000000",
      RX_DFE_VP_CFG => B"00011111100000011",
      RX_DFE_XYD_CFG => B"0000000000000",
      RX_DISPERR_SEQ_MATCH => "TRUE",
      RX_INT_DATAWIDTH => 0,
      RX_OS_CFG => B"0000010000000",
      RX_SIG_VALID_DLY => 4,
      RX_XCLK_SEL => "RXREC",
      SAS_MAX_COM => 64,
      SAS_MIN_COM => 36,
      SATA_BURST_SEQ_LEN => B"1111",
      SATA_BURST_VAL => B"100",
      SATA_CPLL_CFG => "VCO_3000MHZ",
      SATA_EIDLE_VAL => B"100",
      SATA_MAX_BURST => 8,
      SATA_MAX_INIT => 21,
      SATA_MAX_WAKE => 7,
      SATA_MIN_BURST => 4,
      SATA_MIN_INIT => 12,
      SATA_MIN_WAKE => 4,
      SHOW_REALIGN_COMMA => "FALSE",
      SIM_CPLLREFCLK_SEL => B"001",
      SIM_RECEIVER_DETECT_PASS => "TRUE",
      SIM_RESET_SPEEDUP => "FALSE",
      SIM_TX_EIDLE_DRIVE_LEVEL => "1",
      SIM_VERSION => "3.0",
      TERM_RCAL_CFG => B"10000",
      TERM_RCAL_OVRD => '0',
      TRANS_TIME_RATE => X"0E",
      TST_RSV => X"00000000",
      TXBUF_EN => "FALSE",
      TXBUF_RESET_ON_RATE_CHANGE => "TRUE",
      TXDLY_CFG => X"001F",
      TXDLY_LCFG => X"030",
      TXDLY_TAP_CFG => X"0000",
      TXGEARBOX_EN => "FALSE",
      TXOUT_DIV => 2,
      TXPCSRESET_TIME => B"00001",
      TXPHDLY_CFG => X"084020",
      TXPH_CFG => X"0780",
      TXPH_MONITOR_SEL => B"00000",
      TXPMARESET_TIME => B"00011",
      TX_CLK25_DIV => 4,
      TX_CLKMUX_PD => '1',
      TX_DATA_WIDTH => 20,
      TX_DEEMPH0 => B"10100",
      TX_DEEMPH1 => B"01011",
      TX_DRIVE_MODE => "PIPE",
      TX_EIDLE_ASSERT_DELAY => B"010",
      TX_EIDLE_DEASSERT_DELAY => B"100",
      TX_INT_DATAWIDTH => 0,
      TX_LOOPBACK_DRIVE_HIZ => "FALSE",
      TX_MAINCURSOR_SEL => '0',
      TX_MARGIN_FULL_0 => B"1001111",
      TX_MARGIN_FULL_1 => B"1001110",
      TX_MARGIN_FULL_2 => B"1001101",
      TX_MARGIN_FULL_3 => B"1001100",
      TX_MARGIN_FULL_4 => B"1000011",
      TX_MARGIN_LOW_0 => B"1000101",
      TX_MARGIN_LOW_1 => B"1000110",
      TX_MARGIN_LOW_2 => B"1000011",
      TX_MARGIN_LOW_3 => B"1000010",
      TX_MARGIN_LOW_4 => B"1000000",
      TX_PREDRIVER_MODE => '0',
      TX_QPI_STATUS_EN => '0',
      TX_RXDETECT_CFG => X"0064",
      TX_RXDETECT_REF => B"011",
      TX_XCLK_SEL => "TXUSR",
      UCODEER_CLR => '0'
    )
        port map (
      CFGRESET => '0',
      CLKRSVD(3 downto 1) => B"000",
      CLKRSVD(0) => CLKRSVD(0),
      CPLLFBCLKLOST => \NLW_gtx_channel.gtxe2_channel_i_CPLLFBCLKLOST_UNCONNECTED\,
      CPLLLOCK => D(0),
      CPLLLOCKDETCLK => '0',
      CPLLLOCKEN => '1',
      CPLLPD => CPLLPD0,
      CPLLREFCLKLOST => \NLW_gtx_channel.gtxe2_channel_i_CPLLREFCLKLOST_UNCONNECTED\,
      CPLLREFCLKSEL(2 downto 0) => B"001",
      CPLLRESET => CPLLRESET0,
      DMONITOROUT(7 downto 0) => pipe_dmonitorout(7 downto 0),
      DRPADDR(8 downto 0) => DRPADDR(8 downto 0),
      DRPCLK => CLK,
      DRPDI(15 downto 0) => DRPDI(15 downto 0),
      DRPDO(15 downto 0) => ext_ch_gt_drpdo(15 downto 0),
      DRPEN => drp_mux_en_1,
      DRPRDY => ext_ch_gt_drprdy(0),
      DRPWE => drp_mux_we_1,
      EYESCANDATAERROR => pipe_eyescandataerror(0),
      EYESCANMODE => '0',
      EYESCANRESET => '0',
      EYESCANTRIGGER => '0',
      GTGREFCLK => '0',
      GTNORTHREFCLK0 => '0',
      GTNORTHREFCLK1 => '0',
      GTREFCLK0 => sys_clk,
      GTREFCLK1 => '0',
      GTREFCLKMONITOR => \NLW_gtx_channel.gtxe2_channel_i_GTREFCLKMONITOR_UNCONNECTED\,
      GTRESETSEL => '0',
      GTRSVD(15 downto 0) => B"0000000000000000",
      GTRXRESET => rst_gtreset,
      GTSOUTHREFCLK0 => '0',
      GTSOUTHREFCLK1 => '0',
      GTTXRESET => rst_gtreset,
      GTXRXN => pci_exp_rxn(0),
      GTXRXP => pci_exp_rxp(0),
      GTXTXN => pci_exp_txn(0),
      GTXTXP => pci_exp_txp(0),
      LOOPBACK(2 downto 0) => B"000",
      PCSRSVDIN(15 downto 0) => B"0000000000000000",
      PCSRSVDIN2(4 downto 0) => B"00000",
      PCSRSVDOUT(15 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_PCSRSVDOUT_UNCONNECTED\(15 downto 0),
      PHYSTATUS => sys_clk_0(0),
      PMARSVDIN(4 downto 0) => B"00000",
      PMARSVDIN2(4 downto 0) => B"00000",
      QPLLCLK => int_qplloutclk_out(0),
      QPLLREFCLK => int_qplloutrefclk_out(0),
      RESETOVRD => '0',
      RX8B10BEN => rxchbonden_1,
      RXBUFRESET => '0',
      RXBUFSTATUS(2 downto 0) => pipe_rxbufstatus(2 downto 0),
      RXBYTEISALIGNED => \gtx_channel.gtxe2_channel_i_n_9\,
      RXBYTEREALIGN => \gtx_channel.gtxe2_channel_i_n_10\,
      RXCDRFREQRESET => '0',
      RXCDRHOLD => '0',
      RXCDRLOCK => gt_rxcdrlock_1,
      RXCDROVRDEN => '0',
      RXCDRRESET => '0',
      RXCDRRESETRSV => '0',
      RXCHANBONDSEQ => \NLW_gtx_channel.gtxe2_channel_i_RXCHANBONDSEQ_UNCONNECTED\,
      RXCHANISALIGNED => pipe_rx1_chanisaligned,
      RXCHANREALIGN => \NLW_gtx_channel.gtxe2_channel_i_RXCHANREALIGN_UNCONNECTED\,
      RXCHARISCOMMA(7 downto 4) => \NLW_gtx_channel.gtxe2_channel_i_RXCHARISCOMMA_UNCONNECTED\(7 downto 4),
      RXCHARISCOMMA(3) => \gtx_channel.gtxe2_channel_i_n_189\,
      RXCHARISCOMMA(2) => \gtx_channel.gtxe2_channel_i_n_190\,
      RXCHARISCOMMA(1) => \gtx_channel.gtxe2_channel_i_n_191\,
      RXCHARISCOMMA(0) => \gtx_channel.gtxe2_channel_i_n_192\,
      RXCHARISK(7 downto 4) => \NLW_gtx_channel.gtxe2_channel_i_RXCHARISK_UNCONNECTED\(7 downto 4),
      RXCHARISK(3) => \gtx_channel.gtxe2_channel_i_n_197\,
      RXCHARISK(2) => \gtx_channel.gtxe2_channel_i_n_198\,
      RXCHARISK(1 downto 0) => sys_clk_2(1 downto 0),
      RXCHBONDEN => rxchbonden_1,
      RXCHBONDI(4 downto 0) => RXCHBONDO(4 downto 0),
      RXCHBONDLEVEL(2 downto 0) => B"000",
      RXCHBONDMASTER => '0',
      RXCHBONDO(4) => \gtx_channel.gtxe2_channel_i_n_91\,
      RXCHBONDO(3) => \gtx_channel.gtxe2_channel_i_n_92\,
      RXCHBONDO(2) => \gtx_channel.gtxe2_channel_i_n_93\,
      RXCHBONDO(1) => \gtx_channel.gtxe2_channel_i_n_94\,
      RXCHBONDO(0) => \gtx_channel.gtxe2_channel_i_n_95\,
      RXCHBONDSLAVE => rxchbonden_1,
      RXCLKCORCNT(1 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXCLKCORCNT_UNCONNECTED\(1 downto 0),
      RXCOMINITDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMINITDET_UNCONNECTED\,
      RXCOMMADET => pipe_rxcommadet(0),
      RXCOMMADETEN => '1',
      RXCOMSASDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMSASDET_UNCONNECTED\,
      RXCOMWAKEDET => \NLW_gtx_channel.gtxe2_channel_i_RXCOMWAKEDET_UNCONNECTED\,
      RXDATA(63 downto 32) => \NLW_gtx_channel.gtxe2_channel_i_RXDATA_UNCONNECTED\(63 downto 32),
      RXDATA(31) => \gtx_channel.gtxe2_channel_i_n_138\,
      RXDATA(30) => \gtx_channel.gtxe2_channel_i_n_139\,
      RXDATA(29) => \gtx_channel.gtxe2_channel_i_n_140\,
      RXDATA(28) => \gtx_channel.gtxe2_channel_i_n_141\,
      RXDATA(27) => \gtx_channel.gtxe2_channel_i_n_142\,
      RXDATA(26) => \gtx_channel.gtxe2_channel_i_n_143\,
      RXDATA(25) => \gtx_channel.gtxe2_channel_i_n_144\,
      RXDATA(24) => \gtx_channel.gtxe2_channel_i_n_145\,
      RXDATA(23) => \gtx_channel.gtxe2_channel_i_n_146\,
      RXDATA(22) => \gtx_channel.gtxe2_channel_i_n_147\,
      RXDATA(21) => \gtx_channel.gtxe2_channel_i_n_148\,
      RXDATA(20) => \gtx_channel.gtxe2_channel_i_n_149\,
      RXDATA(19) => \gtx_channel.gtxe2_channel_i_n_150\,
      RXDATA(18) => \gtx_channel.gtxe2_channel_i_n_151\,
      RXDATA(17) => \gtx_channel.gtxe2_channel_i_n_152\,
      RXDATA(16) => \gtx_channel.gtxe2_channel_i_n_153\,
      RXDATA(15 downto 0) => sys_clk_1(15 downto 0),
      RXDATAVALID => \NLW_gtx_channel.gtxe2_channel_i_RXDATAVALID_UNCONNECTED\,
      RXDDIEN => '0',
      RXDFEAGCHOLD => \cplllock_reg1_reg[1]\,
      RXDFEAGCOVRDEN => '0',
      RXDFECM1EN => '0',
      RXDFELFHOLD => '0',
      RXDFELFOVRDEN => '1',
      RXDFELPMRESET => '0',
      RXDFETAP2HOLD => '0',
      RXDFETAP2OVRDEN => '0',
      RXDFETAP3HOLD => '0',
      RXDFETAP3OVRDEN => '0',
      RXDFETAP4HOLD => '0',
      RXDFETAP4OVRDEN => '0',
      RXDFETAP5HOLD => '0',
      RXDFETAP5OVRDEN => '0',
      RXDFEUTHOLD => '0',
      RXDFEUTOVRDEN => '0',
      RXDFEVPHOLD => '0',
      RXDFEVPOVRDEN => '0',
      RXDFEVSEN => '0',
      RXDFEXYDEN => '0',
      RXDFEXYDHOLD => '0',
      RXDFEXYDOVRDEN => '0',
      RXDISPERR(7 downto 0) => pipe_rxdisperr(7 downto 0),
      RXDLYBYPASS => '1',
      RXDLYEN => '0',
      RXDLYOVRDEN => '0',
      RXDLYSRESET => '0',
      RXDLYSRESETDONE => pipe_rxdlysresetdone(0),
      RXELECIDLE => PIPE_RXELECIDLE(0),
      RXELECIDLEMODE(1 downto 0) => B"00",
      RXGEARBOXSLIP => '0',
      RXHEADER(2 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXHEADER_UNCONNECTED\(2 downto 0),
      RXHEADERVALID => \NLW_gtx_channel.gtxe2_channel_i_RXHEADERVALID_UNCONNECTED\,
      RXLPMEN => rxchbonden_1,
      RXLPMHFHOLD => '0',
      RXLPMHFOVRDEN => '0',
      RXLPMLFHOLD => '0',
      RXLPMLFKLOVRDEN => '0',
      RXMCOMMAALIGNEN => rxchbonden_1,
      RXMONITOROUT(6 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXMONITOROUT_UNCONNECTED\(6 downto 0),
      RXMONITORSEL(1 downto 0) => B"00",
      RXNOTINTABLE(7 downto 0) => pipe_rxnotintable(7 downto 0),
      RXOOBRESET => '0',
      RXOSHOLD => '0',
      RXOSOVRDEN => '0',
      RXOUTCLK => pipe_rxoutclk_out(0),
      RXOUTCLKFABRIC => \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKFABRIC_UNCONNECTED\,
      RXOUTCLKPCS => \NLW_gtx_channel.gtxe2_channel_i_RXOUTCLKPCS_UNCONNECTED\,
      RXOUTCLKSEL(2 downto 0) => B"000",
      RXPCOMMAALIGNEN => rxchbonden_1,
      RXPCSRESET => '0',
      RXPD(1 downto 0) => pipe_tx1_powerdown(1 downto 0),
      RXPHALIGN => '0',
      RXPHALIGNDONE => pipe_rxphaligndone(0),
      RXPHALIGNEN => '0',
      RXPHDLYPD => '0',
      RXPHDLYRESET => '0',
      RXPHMONITOR(4 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXPHMONITOR_UNCONNECTED\(4 downto 0),
      RXPHOVRDEN => '0',
      RXPHSLIPMONITOR(4 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_RXPHSLIPMONITOR_UNCONNECTED\(4 downto 0),
      RXPMARESET => rate_rxpmareset_1,
      RXPOLARITY => pipe_rx1_polarity,
      RXPRBSCNTRESET => '0',
      RXPRBSERR => pipe_rxprbserr(0),
      RXPRBSSEL(2 downto 0) => B"000",
      RXQPIEN => '0',
      RXQPISENN => \NLW_gtx_channel.gtxe2_channel_i_RXQPISENN_UNCONNECTED\,
      RXQPISENP => \NLW_gtx_channel.gtxe2_channel_i_RXQPISENP_UNCONNECTED\,
      RXRATE(2 downto 1) => B"00",
      RXRATE(0) => RXRATE(0),
      RXRATEDONE => gt_rxratedone_1,
      RXRESETDONE => gt_rxresetdone_1,
      RXSLIDE => '0',
      RXSTARTOFSEQ => \NLW_gtx_channel.gtxe2_channel_i_RXSTARTOFSEQ_UNCONNECTED\,
      RXSTATUS(2 downto 0) => \^pipe_rxstatus\(2 downto 0),
      RXSYSCLKSEL(1) => '0',
      RXSYSCLKSEL(0) => RXSYSCLKSEL(0),
      RXUSERRDY => rst_userrdy,
      RXUSRCLK => \cplllock_reg1_reg[1]_0\,
      RXUSRCLK2 => \cplllock_reg1_reg[1]_0\,
      RXVALID => gt_rxvalid_1,
      SETERRSTATUS => '0',
      TSTIN(19 downto 0) => B"11111111111111111111",
      TSTOUT(9 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_TSTOUT_UNCONNECTED\(9 downto 0),
      TX8B10BBYPASS(7 downto 0) => B"00000000",
      TX8B10BEN => rxchbonden_1,
      TXBUFDIFFCTRL(2 downto 0) => B"100",
      TXBUFSTATUS(1 downto 0) => \NLW_gtx_channel.gtxe2_channel_i_TXBUFSTATUS_UNCONNECTED\(1 downto 0),
      TXCHARDISPMODE(7 downto 1) => B"0000000",
      TXCHARDISPMODE(0) => pipe_tx1_compliance,
      TXCHARDISPVAL(7 downto 0) => B"00000000",
      TXCHARISK(7 downto 2) => B"000000",
      TXCHARISK(1 downto 0) => pipe_tx1_char_is_k(1 downto 0),
      TXCOMFINISH => \NLW_gtx_channel.gtxe2_channel_i_TXCOMFINISH_UNCONNECTED\,
      TXCOMINIT => '0',
      TXCOMSAS => '0',
      TXCOMWAKE => '0',
      TXDATA(63 downto 16) => B"000000000000000000000000000000000000000000000000",
      TXDATA(15 downto 0) => pipe_tx1_data(15 downto 0),
      TXDEEMPH => pipe_tx_deemph,
      TXDETECTRX => pipe_tx_rcvr_det,
      TXDIFFCTRL(3 downto 0) => B"1100",
      TXDIFFPD => '0',
      TXDLYBYPASS => '0',
      TXDLYEN => '0',
      TXDLYHOLD => '0',
      TXDLYOVRDEN => '0',
      TXDLYSRESET => Q(0),
      TXDLYSRESETDONE => pipe_txdlysresetdone(0),
      TXDLYUPDOWN => '0',
      TXELECIDLE => pipe_tx1_elec_idle,
      TXGEARBOXREADY => \NLW_gtx_channel.gtxe2_channel_i_TXGEARBOXREADY_UNCONNECTED\,
      TXHEADER(2 downto 0) => B"000",
      TXINHIBIT => pipe_txinhibit(0),
      TXMAINCURSOR(6 downto 0) => TXMAINCURSOR(6 downto 0),
      TXMARGIN(2 downto 0) => pipe_tx_margin(2 downto 0),
      TXOUTCLK => \gtx_channel.gtxe2_channel_i_n_37\,
      TXOUTCLKFABRIC => \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKFABRIC_UNCONNECTED\,
      TXOUTCLKPCS => \NLW_gtx_channel.gtxe2_channel_i_TXOUTCLKPCS_UNCONNECTED\,
      TXOUTCLKSEL(2 downto 0) => B"000",
      TXPCSRESET => '0',
      TXPD(1 downto 0) => pipe_tx1_powerdown(1 downto 0),
      TXPDELECIDLEMODE => '0',
      TXPHALIGN => Q(2),
      TXPHALIGNDONE => pipe_txphaligndone(0),
      TXPHALIGNEN => '1',
      TXPHDLYPD => '0',
      TXPHDLYRESET => '0',
      TXPHDLYTSTCLK => '0',
      TXPHINIT => Q(1),
      TXPHINITDONE => pipe_txphinitdone(0),
      TXPHOVRDEN => '0',
      TXPISOPD => '0',
      TXPMARESET => rate_rxpmareset_1,
      TXPOLARITY => '0',
      TXPOSTCURSOR(4 downto 0) => TXPOSTCURSOR(4 downto 0),
      TXPOSTCURSORINV => '0',
      TXPRBSFORCEERR => '0',
      TXPRBSSEL(2 downto 0) => B"000",
      TXPRECURSOR(4 downto 0) => TXPRECURSOR(4 downto 0),
      TXPRECURSORINV => '0',
      TXQPIBIASEN => '0',
      TXQPISENN => \NLW_gtx_channel.gtxe2_channel_i_TXQPISENN_UNCONNECTED\,
      TXQPISENP => \NLW_gtx_channel.gtxe2_channel_i_TXQPISENP_UNCONNECTED\,
      TXQPISTRONGPDOWN => '0',
      TXQPIWEAKPUP => '0',
      TXRATE(2 downto 1) => B"00",
      TXRATE(0) => RXRATE(0),
      TXRATEDONE => gt_txratedone_1,
      TXRESETDONE => gt_txresetdone_1,
      TXSEQUENCE(6 downto 0) => B"0000000",
      TXSTARTSEQ => '0',
      TXSWING => '0',
      TXSYSCLKSEL(1) => '0',
      TXSYSCLKSEL(0) => RXSYSCLKSEL(0),
      TXUSERRDY => rst_userrdy,
      TXUSRCLK => \cplllock_reg1_reg[1]_0\,
      TXUSRCLK2 => \cplllock_reg1_reg[1]_0\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x is
  port (
    rdata : out STD_LOGIC_VECTOR ( 17 downto 0 );
    CLK : in STD_LOGIC;
    mim_tx_wen : in STD_LOGIC;
    mim_tx_ren : in STD_LOGIC;
    MIMTXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMTXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    wdata : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x : entity is "spec7_pcie_7x_0_pcie_bram_7x";
end spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x is
begin
\use_tdp.ramb36\: entity work.spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_6
     port map (
      CLK => CLK,
      MIMTXRADDR(10 downto 0) => MIMTXRADDR(10 downto 0),
      MIMTXWADDR(10 downto 0) => MIMTXWADDR(10 downto 0),
      mim_tx_ren => mim_tx_ren,
      mim_tx_wen => mim_tx_wen,
      rdata(17 downto 0) => rdata(17 downto 0),
      wdata(17 downto 0) => wdata(17 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_1 is
  port (
    rdata : out STD_LOGIC_VECTOR ( 17 downto 0 );
    CLK : in STD_LOGIC;
    mim_tx_wen : in STD_LOGIC;
    mim_tx_ren : in STD_LOGIC;
    MIMTXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMTXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    wdata : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_1 : entity is "spec7_pcie_7x_0_pcie_bram_7x";
end spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_1;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_1 is
begin
\use_tdp.ramb36\: entity work.spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_5
     port map (
      CLK => CLK,
      MIMTXRADDR(10 downto 0) => MIMTXRADDR(10 downto 0),
      MIMTXWADDR(10 downto 0) => MIMTXWADDR(10 downto 0),
      mim_tx_ren => mim_tx_ren,
      mim_tx_wen => mim_tx_wen,
      rdata(17 downto 0) => rdata(17 downto 0),
      wdata(17 downto 0) => wdata(17 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_10 is
  port (
    \ramb_bl.ramb36_dp_bl.ram36_bl\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
    CLK : in STD_LOGIC;
    mim_rx_wen : in STD_LOGIC;
    mim_rx_ren : in STD_LOGIC;
    MIMRXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMRXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_0\ : in STD_LOGIC_VECTOR ( 13 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_10 : entity is "spec7_pcie_7x_0_pcie_bram_7x";
end spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_10;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_10 is
begin
\use_tdp.ramb36\: entity work.spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_11
     port map (
      CLK => CLK,
      MIMRXRADDR(10 downto 0) => MIMRXRADDR(10 downto 0),
      MIMRXWADDR(10 downto 0) => MIMRXWADDR(10 downto 0),
      mim_rx_ren => mim_rx_ren,
      mim_rx_wen => mim_rx_wen,
      \ramb_bl.ramb36_dp_bl.ram36_bl_0\(13 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl\(13 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_1\(13 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(13 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_2 is
  port (
    rdata : out STD_LOGIC_VECTOR ( 17 downto 0 );
    CLK : in STD_LOGIC;
    mim_tx_wen : in STD_LOGIC;
    mim_tx_ren : in STD_LOGIC;
    MIMTXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMTXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    wdata : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_2 : entity is "spec7_pcie_7x_0_pcie_bram_7x";
end spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_2;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_2 is
begin
\use_tdp.ramb36\: entity work.spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_4
     port map (
      CLK => CLK,
      MIMTXRADDR(10 downto 0) => MIMTXRADDR(10 downto 0),
      MIMTXWADDR(10 downto 0) => MIMTXWADDR(10 downto 0),
      mim_tx_ren => mim_tx_ren,
      mim_tx_wen => mim_tx_wen,
      rdata(17 downto 0) => rdata(17 downto 0),
      wdata(17 downto 0) => wdata(17 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_3 is
  port (
    rdata : out STD_LOGIC_VECTOR ( 14 downto 0 );
    CLK : in STD_LOGIC;
    mim_tx_wen : in STD_LOGIC;
    mim_tx_ren : in STD_LOGIC;
    MIMTXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMTXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    wdata : in STD_LOGIC_VECTOR ( 14 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_3 : entity is "spec7_pcie_7x_0_pcie_bram_7x";
end spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_3;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_3 is
begin
\use_tdp.ramb36\: entity work.spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO
     port map (
      CLK => CLK,
      MIMTXRADDR(10 downto 0) => MIMTXRADDR(10 downto 0),
      MIMTXWADDR(10 downto 0) => MIMTXWADDR(10 downto 0),
      mim_tx_ren => mim_tx_ren,
      mim_tx_wen => mim_tx_wen,
      rdata(14 downto 0) => rdata(14 downto 0),
      wdata(14 downto 0) => wdata(14 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_7 is
  port (
    \ramb_bl.ramb36_dp_bl.ram36_bl\ : out STD_LOGIC_VECTOR ( 17 downto 0 );
    CLK : in STD_LOGIC;
    mim_rx_wen : in STD_LOGIC;
    mim_rx_ren : in STD_LOGIC;
    MIMRXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMRXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_0\ : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_7 : entity is "spec7_pcie_7x_0_pcie_bram_7x";
end spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_7;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_7 is
begin
\use_tdp.ramb36\: entity work.spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_14
     port map (
      CLK => CLK,
      MIMRXRADDR(10 downto 0) => MIMRXRADDR(10 downto 0),
      MIMRXWADDR(10 downto 0) => MIMRXWADDR(10 downto 0),
      mim_rx_ren => mim_rx_ren,
      mim_rx_wen => mim_rx_wen,
      \ramb_bl.ramb36_dp_bl.ram36_bl_0\(17 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl\(17 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_1\(17 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(17 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_8 is
  port (
    \ramb_bl.ramb36_dp_bl.ram36_bl\ : out STD_LOGIC_VECTOR ( 17 downto 0 );
    CLK : in STD_LOGIC;
    mim_rx_wen : in STD_LOGIC;
    mim_rx_ren : in STD_LOGIC;
    MIMRXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMRXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_0\ : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_8 : entity is "spec7_pcie_7x_0_pcie_bram_7x";
end spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_8;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_8 is
begin
\use_tdp.ramb36\: entity work.spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_13
     port map (
      CLK => CLK,
      MIMRXRADDR(10 downto 0) => MIMRXRADDR(10 downto 0),
      MIMRXWADDR(10 downto 0) => MIMRXWADDR(10 downto 0),
      mim_rx_ren => mim_rx_ren,
      mim_rx_wen => mim_rx_wen,
      \ramb_bl.ramb36_dp_bl.ram36_bl_0\(17 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl\(17 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_1\(17 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(17 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_9 is
  port (
    \ramb_bl.ramb36_dp_bl.ram36_bl\ : out STD_LOGIC_VECTOR ( 17 downto 0 );
    CLK : in STD_LOGIC;
    mim_rx_wen : in STD_LOGIC;
    mim_rx_ren : in STD_LOGIC;
    MIMRXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMRXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_0\ : in STD_LOGIC_VECTOR ( 17 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_9 : entity is "spec7_pcie_7x_0_pcie_bram_7x";
end spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_9;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_9 is
begin
\use_tdp.ramb36\: entity work.spec7_pcie_7x_0_unimacro_BRAM_TDP_MACRO_12
     port map (
      CLK => CLK,
      MIMRXRADDR(10 downto 0) => MIMRXRADDR(10 downto 0),
      MIMRXWADDR(10 downto 0) => MIMRXWADDR(10 downto 0),
      mim_rx_ren => mim_rx_ren,
      mim_rx_wen => mim_rx_wen,
      \ramb_bl.ramb36_dp_bl.ram36_bl_0\(17 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl\(17 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_1\(17 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(17 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_eq is
  port (
    rxeq_adapt_done_reg_0 : out STD_LOGIC;
    TXPRECURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 );
    TXMAINCURSOR : out STD_LOGIC_VECTOR ( 6 downto 0 );
    TXPOSTCURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \out\ : in STD_LOGIC;
    \fs_reg2_reg[5]\ : in STD_LOGIC;
    SYNC_GEN3 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_eq : entity is "spec7_pcie_7x_0_pipe_eq";
end spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_eq;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_eq is
  signal \FSM_onehot_fsm_rx[1]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx[1]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx[3]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx[4]_i_1_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx_reg_n_0_[1]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx_reg_n_0_[2]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx_reg_n_0_[3]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx_reg_n_0_[4]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx_reg_n_0_[5]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx_reg_n_0_[6]\ : STD_LOGIC;
  signal \FSM_sequential_fsm_tx[1]_i_2_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_tx[2]_i_2_n_0\ : STD_LOGIC;
  signal fsm_tx : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \fsm_tx__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal gen3_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of gen3_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of gen3_reg1 : signal is "true";
  signal gen3_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of gen3_reg2 : signal is "NO";
  attribute async_reg of gen3_reg2 : signal is "true";
  signal p_0_out : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal rxeq_adapt_done_i_2_n_0 : STD_LOGIC;
  signal \^rxeq_adapt_done_reg_0\ : STD_LOGIC;
  signal rxeq_adapt_done_reg_i_2_n_0 : STD_LOGIC;
  signal rxeq_adapt_done_reg_reg_n_0 : STD_LOGIC;
  signal rxeq_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \rxeq_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal rxeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_control_reg1 : signal is "NO";
  attribute async_reg of rxeq_control_reg1 : signal is "true";
  signal rxeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_control_reg2 : signal is "NO";
  attribute async_reg of rxeq_control_reg2 : signal is "true";
  signal rxeq_fs : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_fs[5]_i_1_n_0\ : STD_LOGIC;
  signal \rxeq_fs_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_fs_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_fs_reg_n_0_[2]\ : STD_LOGIC;
  signal \rxeq_fs_reg_n_0_[3]\ : STD_LOGIC;
  signal \rxeq_fs_reg_n_0_[4]\ : STD_LOGIC;
  signal \rxeq_fs_reg_n_0_[5]\ : STD_LOGIC;
  signal rxeq_lf : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_lf[5]_i_1_n_0\ : STD_LOGIC;
  signal \rxeq_lf_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_lf_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_lf_reg_n_0_[2]\ : STD_LOGIC;
  signal \rxeq_lf_reg_n_0_[3]\ : STD_LOGIC;
  signal \rxeq_lf_reg_n_0_[4]\ : STD_LOGIC;
  signal \rxeq_lf_reg_n_0_[5]\ : STD_LOGIC;
  signal rxeq_lffs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_lffs_reg1 : signal is "NO";
  attribute async_reg of rxeq_lffs_reg1 : signal is "true";
  signal rxeq_lffs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_lffs_reg2 : signal is "NO";
  attribute async_reg of rxeq_lffs_reg2 : signal is "true";
  signal rxeq_new_txcoeff_req : STD_LOGIC;
  signal rxeq_new_txcoeff_req_reg_n_0 : STD_LOGIC;
  signal \rxeq_preset[0]_i_1_n_0\ : STD_LOGIC;
  signal \rxeq_preset[1]_i_1_n_0\ : STD_LOGIC;
  signal \rxeq_preset[2]_i_1_n_0\ : STD_LOGIC;
  signal \rxeq_preset[2]_i_2_n_0\ : STD_LOGIC;
  signal \rxeq_preset[2]_i_3_n_0\ : STD_LOGIC;
  signal rxeq_preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_preset_reg1 : signal is "NO";
  attribute async_reg of rxeq_preset_reg1 : signal is "true";
  signal rxeq_preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_preset_reg2 : signal is "NO";
  attribute async_reg of rxeq_preset_reg2 : signal is "true";
  signal \rxeq_preset_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_preset_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_preset_reg_n_0_[2]\ : STD_LOGIC;
  signal rxeq_preset_valid : STD_LOGIC;
  signal rxeq_scan_i_n_0 : STD_LOGIC;
  signal rxeq_scan_i_n_1 : STD_LOGIC;
  signal rxeq_scan_i_n_2 : STD_LOGIC;
  signal rxeq_scan_i_n_3 : STD_LOGIC;
  signal rxeq_scan_i_n_4 : STD_LOGIC;
  signal rxeq_txcoeff : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal \rxeq_txcoeff_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[10]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[11]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[12]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[13]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[14]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[15]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[16]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[17]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[2]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[3]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[4]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[5]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[6]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[7]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[8]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[9]\ : STD_LOGIC;
  signal rxeq_txpreset : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rxeq_txpreset[3]_i_1_n_0\ : STD_LOGIC;
  signal \rxeq_txpreset[3]_i_3_n_0\ : STD_LOGIC;
  signal rxeq_txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_txpreset_reg1 : signal is "NO";
  attribute async_reg of rxeq_txpreset_reg1 : signal is "true";
  signal rxeq_txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_txpreset_reg2 : signal is "NO";
  attribute async_reg of rxeq_txpreset_reg2 : signal is "true";
  signal \rxeq_txpreset_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_txpreset_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_txpreset_reg_n_0_[2]\ : STD_LOGIC;
  signal \rxeq_txpreset_reg_n_0_[3]\ : STD_LOGIC;
  signal rxeq_user_en_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxeq_user_en_reg1 : signal is "NO";
  attribute async_reg of rxeq_user_en_reg1 : signal is "true";
  signal rxeq_user_en_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxeq_user_en_reg2 : signal is "NO";
  attribute async_reg of rxeq_user_en_reg2 : signal is "true";
  signal rxeq_user_mode_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxeq_user_mode_reg1 : signal is "NO";
  attribute async_reg of rxeq_user_mode_reg1 : signal is "true";
  signal rxeq_user_mode_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxeq_user_mode_reg2 : signal is "NO";
  attribute async_reg of rxeq_user_mode_reg2 : signal is "true";
  signal rxeq_user_txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_user_txcoeff_reg1 : signal is "NO";
  attribute async_reg of rxeq_user_txcoeff_reg1 : signal is "true";
  signal rxeq_user_txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_user_txcoeff_reg2 : signal is "NO";
  attribute async_reg of rxeq_user_txcoeff_reg2 : signal is "true";
  signal txeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of txeq_control_reg1 : signal is "NO";
  attribute async_reg of txeq_control_reg1 : signal is "true";
  signal txeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of txeq_control_reg2 : signal is "NO";
  attribute async_reg of txeq_control_reg2 : signal is "true";
  signal txeq_deemph_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT of txeq_deemph_reg1 : signal is "NO";
  attribute async_reg of txeq_deemph_reg1 : signal is "true";
  signal txeq_deemph_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT of txeq_deemph_reg2 : signal is "NO";
  attribute async_reg of txeq_deemph_reg2 : signal is "true";
  signal \txeq_preset[17]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_preset[3]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_preset[7]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_preset[7]_i_2_n_0\ : STD_LOGIC;
  signal txeq_preset_done : STD_LOGIC;
  signal txeq_preset_done_i_1_n_0 : STD_LOGIC;
  signal txeq_preset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SHIFT_EXTRACT of txeq_preset_reg1 : signal is "NO";
  attribute async_reg of txeq_preset_reg1 : signal is "true";
  signal txeq_preset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SHIFT_EXTRACT of txeq_preset_reg2 : signal is "NO";
  attribute async_reg of txeq_preset_reg2 : signal is "true";
  signal \txeq_preset_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[10]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[11]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[12]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[13]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[14]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[15]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[16]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[17]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[2]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[3]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[7]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[8]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[9]\ : STD_LOGIC;
  signal txeq_txcoeff : STD_LOGIC;
  signal \txeq_txcoeff[0]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[0]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[10]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[10]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[11]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[11]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[12]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[12]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[13]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[13]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[14]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[14]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[15]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[15]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[16]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[16]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[17]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[17]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[1]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[1]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[2]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[2]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[3]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[3]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[4]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[4]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[5]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[5]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[5]_i_3_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[6]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[6]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[7]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[7]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[8]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[8]_i_2_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[9]_i_1_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[9]_i_2_n_0\ : STD_LOGIC;
  signal txeq_txcoeff_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \txeq_txcoeff_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_txcoeff_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[10]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[11]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[12]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[13]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[14]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[15]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[16]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[17]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[18]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[2]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[3]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[4]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[5]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[6]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[7]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[8]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[9]\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_fsm_rx[4]_i_1\ : label is "soft_lutpair19";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[1]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[2]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[3]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[4]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[5]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[6]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001";
  attribute SOFT_HLUTNM of \FSM_sequential_fsm_tx[2]_i_2\ : label is "soft_lutpair18";
  attribute FSM_ENCODED_STATES of \FSM_sequential_fsm_tx_reg[0]\ : label is "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000";
  attribute FSM_ENCODED_STATES of \FSM_sequential_fsm_tx_reg[1]\ : label is "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000";
  attribute FSM_ENCODED_STATES of \FSM_sequential_fsm_tx_reg[2]\ : label is "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of gen3_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of gen3_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of gen3_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of gen3_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of gen3_reg2_reg : label is "NO";
  attribute SOFT_HLUTNM of \rxeq_cnt[1]_i_1\ : label is "soft_lutpair21";
  attribute SOFT_HLUTNM of \rxeq_cnt[2]_i_1\ : label is "soft_lutpair19";
  attribute ASYNC_REG_boolean of \rxeq_control_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_control_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_control_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_control_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_control_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_control_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_control_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_control_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[5]\ : label is "NO";
  attribute SOFT_HLUTNM of \rxeq_preset[2]_i_3\ : label is "soft_lutpair21";
  attribute ASYNC_REG_boolean of \rxeq_preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_preset_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_preset_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_preset_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_preset_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_preset_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_preset_reg2_reg[2]\ : label is "NO";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[0]_i_1\ : label is "soft_lutpair22";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[10]_i_1\ : label is "soft_lutpair27";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[11]_i_1\ : label is "soft_lutpair27";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[1]_i_1\ : label is "soft_lutpair22";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[2]_i_1\ : label is "soft_lutpair23";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[3]_i_1\ : label is "soft_lutpair23";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[4]_i_1\ : label is "soft_lutpair24";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[5]_i_1\ : label is "soft_lutpair24";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[6]_i_1\ : label is "soft_lutpair25";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[7]_i_1\ : label is "soft_lutpair25";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[8]_i_1\ : label is "soft_lutpair26";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[9]_i_1\ : label is "soft_lutpair26";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of rxeq_user_en_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_en_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxeq_user_en_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxeq_user_en_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_en_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxeq_user_en_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxeq_user_mode_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_mode_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxeq_user_mode_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxeq_user_mode_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_mode_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxeq_user_mode_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[10]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[10]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[11]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[11]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[12]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[12]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[13]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[13]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[14]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[14]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[15]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[15]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[16]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[16]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[16]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[17]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[17]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[17]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[6]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[6]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[7]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[7]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[8]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[8]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[9]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[9]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[10]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[10]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[11]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[11]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[12]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[12]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[13]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[13]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[14]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[14]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[15]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[15]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[16]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[16]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[16]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[17]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[17]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[17]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[6]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[6]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[7]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[7]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[8]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[8]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[9]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[9]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_control_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_control_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_control_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_control_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_control_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_control_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_control_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_control_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[3]\ : label is "NO";
  attribute SOFT_HLUTNM of \txeq_txcoeff[18]_i_3\ : label is "soft_lutpair20";
  attribute SOFT_HLUTNM of \txeq_txcoeff[5]_i_3\ : label is "soft_lutpair18";
  attribute SOFT_HLUTNM of \txeq_txcoeff_cnt[1]_i_1\ : label is "soft_lutpair20";
begin
  rxeq_adapt_done_reg_0 <= \^rxeq_adapt_done_reg_0\;
\FSM_onehot_fsm_rx[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ABABABAA"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx[1]_i_2_n_0\,
      I1 => rxeq_control_reg2(0),
      I2 => rxeq_control_reg2(1),
      I3 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I4 => \FSM_onehot_fsm_rx_reg_n_0_[6]\,
      O => \FSM_onehot_fsm_rx[1]_i_1_n_0\
    );
\FSM_onehot_fsm_rx[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[6]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[5]\,
      I3 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I5 => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      O => \FSM_onehot_fsm_rx[1]_i_2_n_0\
    );
\FSM_onehot_fsm_rx[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF8FF88888888"
    )
        port map (
      I0 => rxeq_control_reg2(1),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I2 => \rxeq_cnt_reg_n_0_[2]\,
      I3 => \rxeq_cnt_reg_n_0_[1]\,
      I4 => \rxeq_cnt_reg_n_0_[0]\,
      I5 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      O => \FSM_onehot_fsm_rx[3]_i_1_n_0\
    );
\FSM_onehot_fsm_rx[4]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2ABA2AAA"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I1 => \rxeq_cnt_reg_n_0_[2]\,
      I2 => \rxeq_cnt_reg_n_0_[1]\,
      I3 => \rxeq_cnt_reg_n_0_[0]\,
      I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      O => \FSM_onehot_fsm_rx[4]_i_1_n_0\
    );
\FSM_onehot_fsm_rx_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \FSM_onehot_fsm_rx[1]_i_1_n_0\,
      Q => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      S => \out\
    );
\FSM_onehot_fsm_rx_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_scan_i_n_4,
      Q => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      R => \out\
    );
\FSM_onehot_fsm_rx_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \FSM_onehot_fsm_rx[3]_i_1_n_0\,
      Q => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      R => \out\
    );
\FSM_onehot_fsm_rx_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \FSM_onehot_fsm_rx[4]_i_1_n_0\,
      Q => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      R => \out\
    );
\FSM_onehot_fsm_rx_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_scan_i_n_3,
      Q => \FSM_onehot_fsm_rx_reg_n_0_[5]\,
      R => \out\
    );
\FSM_onehot_fsm_rx_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_scan_i_n_2,
      Q => \FSM_onehot_fsm_rx_reg_n_0_[6]\,
      R => \out\
    );
\FSM_sequential_fsm_tx[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCF44440000FF3F"
    )
        port map (
      I0 => \FSM_sequential_fsm_tx[1]_i_2_n_0\,
      I1 => fsm_tx(0),
      I2 => txeq_control_reg2(0),
      I3 => txeq_control_reg2(1),
      I4 => fsm_tx(2),
      I5 => fsm_tx(1),
      O => \fsm_tx__0\(0)
    );
\FSM_sequential_fsm_tx[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3F703F7C3F7C0F70"
    )
        port map (
      I0 => \FSM_sequential_fsm_tx[1]_i_2_n_0\,
      I1 => fsm_tx(0),
      I2 => fsm_tx(1),
      I3 => fsm_tx(2),
      I4 => txeq_control_reg2(1),
      I5 => txeq_control_reg2(0),
      O => \fsm_tx__0\(1)
    );
\FSM_sequential_fsm_tx[1]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      O => \FSM_sequential_fsm_tx[1]_i_2_n_0\
    );
\FSM_sequential_fsm_tx[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00A8EAAA55FDFFFF"
    )
        port map (
      I0 => fsm_tx(2),
      I1 => txeq_control_reg2(1),
      I2 => txeq_control_reg2(0),
      I3 => fsm_tx(0),
      I4 => fsm_tx(1),
      I5 => \FSM_sequential_fsm_tx[2]_i_2_n_0\,
      O => \fsm_tx__0\(2)
    );
\FSM_sequential_fsm_tx[2]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"D0FFDFFF"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => fsm_tx(0),
      I3 => fsm_tx(1),
      I4 => txeq_preset_done,
      O => \FSM_sequential_fsm_tx[2]_i_2_n_0\
    );
\FSM_sequential_fsm_tx_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \fsm_tx__0\(0),
      Q => fsm_tx(0),
      S => \out\
    );
\FSM_sequential_fsm_tx_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \fsm_tx__0\(1),
      Q => fsm_tx(1),
      R => \out\
    );
\FSM_sequential_fsm_tx_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \fsm_tx__0\(2),
      Q => fsm_tx(2),
      R => \out\
    );
gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => SYNC_GEN3,
      Q => gen3_reg1,
      R => \out\
    );
gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => gen3_reg1,
      Q => gen3_reg2,
      R => \out\
    );
\gtx_channel.gtxe2_channel_i_i_22\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[17]\,
      O => TXPOSTCURSOR(4)
    );
\gtx_channel.gtxe2_channel_i_i_23\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[16]\,
      O => TXPOSTCURSOR(3)
    );
\gtx_channel.gtxe2_channel_i_i_24\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[15]\,
      O => TXPOSTCURSOR(2)
    );
\gtx_channel.gtxe2_channel_i_i_25\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[14]\,
      O => TXPOSTCURSOR(1)
    );
\gtx_channel.gtxe2_channel_i_i_26\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[13]\,
      O => TXPOSTCURSOR(0)
    );
\gtx_channel.gtxe2_channel_i_i_27\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[4]\,
      O => TXPRECURSOR(4)
    );
\gtx_channel.gtxe2_channel_i_i_28\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[3]\,
      O => TXPRECURSOR(3)
    );
\gtx_channel.gtxe2_channel_i_i_29\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[2]\,
      O => TXPRECURSOR(2)
    );
\gtx_channel.gtxe2_channel_i_i_30\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[1]\,
      O => TXPRECURSOR(1)
    );
\gtx_channel.gtxe2_channel_i_i_31\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[0]\,
      I1 => gen3_reg2,
      O => TXPRECURSOR(0)
    );
\gtx_channel.gtxe2_channel_i_i_32\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[12]\,
      O => TXMAINCURSOR(6)
    );
\gtx_channel.gtxe2_channel_i_i_33\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[11]\,
      O => TXMAINCURSOR(5)
    );
\gtx_channel.gtxe2_channel_i_i_34\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[10]\,
      O => TXMAINCURSOR(4)
    );
\gtx_channel.gtxe2_channel_i_i_35\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[9]\,
      O => TXMAINCURSOR(3)
    );
\gtx_channel.gtxe2_channel_i_i_36\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[8]\,
      O => TXMAINCURSOR(2)
    );
\gtx_channel.gtxe2_channel_i_i_37\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[7]\,
      O => TXMAINCURSOR(1)
    );
\gtx_channel.gtxe2_channel_i_i_38\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[6]\,
      O => TXMAINCURSOR(0)
    );
rxeq_adapt_done_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEFFFFFFFF"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[5]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      I3 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I5 => \FSM_onehot_fsm_rx_reg_n_0_[6]\,
      O => rxeq_adapt_done_i_2_n_0
    );
rxeq_adapt_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_scan_i_n_1,
      Q => \^rxeq_adapt_done_reg_0\,
      R => \out\
    );
rxeq_adapt_done_reg_i_2: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => rxeq_control_reg2(0),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I2 => rxeq_control_reg2(1),
      O => rxeq_adapt_done_reg_i_2_n_0
    );
rxeq_adapt_done_reg_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_scan_i_n_0,
      Q => rxeq_adapt_done_reg_reg_n_0,
      R => \out\
    );
\rxeq_cnt[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8888FFF8"
    )
        port map (
      I0 => rxeq_control_reg2(1),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I3 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I4 => \rxeq_cnt_reg_n_0_[0]\,
      O => rxeq_cnt(0)
    );
\rxeq_cnt[1]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6660"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[1]\,
      I1 => \rxeq_cnt_reg_n_0_[0]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I3 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      O => rxeq_cnt(1)
    );
\rxeq_cnt[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78787800"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[0]\,
      I1 => \rxeq_cnt_reg_n_0_[1]\,
      I2 => \rxeq_cnt_reg_n_0_[2]\,
      I3 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      O => rxeq_cnt(2)
    );
\rxeq_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_cnt(0),
      Q => \rxeq_cnt_reg_n_0_[0]\,
      R => \out\
    );
\rxeq_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_cnt(1),
      Q => \rxeq_cnt_reg_n_0_[1]\,
      R => \out\
    );
\rxeq_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_cnt(2),
      Q => \rxeq_cnt_reg_n_0_[2]\,
      R => \out\
    );
\rxeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_control_reg1(0),
      R => \out\
    );
\rxeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_control_reg1(1),
      R => \out\
    );
\rxeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_control_reg1(0),
      Q => rxeq_control_reg2(0),
      R => \out\
    );
\rxeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_control_reg1(1),
      Q => rxeq_control_reg2(1),
      R => \out\
    );
\rxeq_fs[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_lffs_reg2(0),
      O => rxeq_fs(0)
    );
\rxeq_fs[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_lffs_reg2(1),
      O => rxeq_fs(1)
    );
\rxeq_fs[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_lffs_reg2(2),
      O => rxeq_fs(2)
    );
\rxeq_fs[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_lffs_reg2(3),
      O => rxeq_fs(3)
    );
\rxeq_fs[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_lffs_reg2(4),
      O => rxeq_fs(4)
    );
\rxeq_fs[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => rxeq_control_reg2(1),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_rx[1]_i_2_n_0\,
      O => \rxeq_fs[5]_i_1_n_0\
    );
\rxeq_fs[5]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_lffs_reg2(5),
      O => rxeq_fs(5)
    );
\rxeq_fs_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_fs[5]_i_1_n_0\,
      D => rxeq_fs(0),
      Q => \rxeq_fs_reg_n_0_[0]\,
      R => \out\
    );
\rxeq_fs_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_fs[5]_i_1_n_0\,
      D => rxeq_fs(1),
      Q => \rxeq_fs_reg_n_0_[1]\,
      R => \out\
    );
\rxeq_fs_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_fs[5]_i_1_n_0\,
      D => rxeq_fs(2),
      Q => \rxeq_fs_reg_n_0_[2]\,
      R => \out\
    );
\rxeq_fs_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_fs[5]_i_1_n_0\,
      D => rxeq_fs(3),
      Q => \rxeq_fs_reg_n_0_[3]\,
      R => \out\
    );
\rxeq_fs_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_fs[5]_i_1_n_0\,
      D => rxeq_fs(4),
      Q => \rxeq_fs_reg_n_0_[4]\,
      R => \out\
    );
\rxeq_fs_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_fs[5]_i_1_n_0\,
      D => rxeq_fs(5),
      Q => \rxeq_fs_reg_n_0_[5]\,
      R => \out\
    );
\rxeq_lf[0]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I1 => rxeq_lffs_reg2(0),
      O => rxeq_lf(0)
    );
\rxeq_lf[1]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I1 => rxeq_lffs_reg2(1),
      O => rxeq_lf(1)
    );
\rxeq_lf[2]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I1 => rxeq_lffs_reg2(2),
      O => rxeq_lf(2)
    );
\rxeq_lf[3]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I1 => rxeq_lffs_reg2(3),
      O => rxeq_lf(3)
    );
\rxeq_lf[4]_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I1 => rxeq_lffs_reg2(4),
      O => rxeq_lf(4)
    );
\rxeq_lf[5]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAAAAAAA"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx[1]_i_2_n_0\,
      I1 => \rxeq_cnt_reg_n_0_[1]\,
      I2 => \rxeq_cnt_reg_n_0_[0]\,
      I3 => \rxeq_cnt_reg_n_0_[2]\,
      I4 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      O => \rxeq_lf[5]_i_1_n_0\
    );
\rxeq_lf[5]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I1 => rxeq_lffs_reg2(5),
      O => rxeq_lf(5)
    );
\rxeq_lf_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_lf[5]_i_1_n_0\,
      D => rxeq_lf(0),
      Q => \rxeq_lf_reg_n_0_[0]\,
      R => \out\
    );
\rxeq_lf_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_lf[5]_i_1_n_0\,
      D => rxeq_lf(1),
      Q => \rxeq_lf_reg_n_0_[1]\,
      R => \out\
    );
\rxeq_lf_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_lf[5]_i_1_n_0\,
      D => rxeq_lf(2),
      Q => \rxeq_lf_reg_n_0_[2]\,
      R => \out\
    );
\rxeq_lf_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_lf[5]_i_1_n_0\,
      D => rxeq_lf(3),
      Q => \rxeq_lf_reg_n_0_[3]\,
      R => \out\
    );
\rxeq_lf_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_lf[5]_i_1_n_0\,
      D => rxeq_lf(4),
      Q => \rxeq_lf_reg_n_0_[4]\,
      R => \out\
    );
\rxeq_lf_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_lf[5]_i_1_n_0\,
      D => rxeq_lf(5),
      Q => \rxeq_lf_reg_n_0_[5]\,
      R => \out\
    );
\rxeq_lffs_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(0),
      R => \out\
    );
\rxeq_lffs_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(1),
      R => \out\
    );
\rxeq_lffs_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(2),
      R => \out\
    );
\rxeq_lffs_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(3),
      R => \out\
    );
\rxeq_lffs_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(4),
      R => \out\
    );
\rxeq_lffs_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(5),
      R => \out\
    );
\rxeq_lffs_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_lffs_reg1(0),
      Q => rxeq_lffs_reg2(0),
      R => \out\
    );
\rxeq_lffs_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_lffs_reg1(1),
      Q => rxeq_lffs_reg2(1),
      R => \out\
    );
\rxeq_lffs_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_lffs_reg1(2),
      Q => rxeq_lffs_reg2(2),
      R => \out\
    );
\rxeq_lffs_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_lffs_reg1(3),
      Q => rxeq_lffs_reg2(3),
      R => \out\
    );
\rxeq_lffs_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_lffs_reg1(4),
      Q => rxeq_lffs_reg2(4),
      R => \out\
    );
\rxeq_lffs_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_lffs_reg1(5),
      Q => rxeq_lffs_reg2(5),
      R => \out\
    );
rxeq_new_txcoeff_req_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_new_txcoeff_req,
      Q => rxeq_new_txcoeff_req_reg_n_0,
      R => \out\
    );
\rxeq_preset[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8FFA800"
    )
        port map (
      I0 => rxeq_preset_reg2(0),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I3 => \rxeq_preset[2]_i_2_n_0\,
      I4 => \rxeq_preset_reg_n_0_[0]\,
      O => \rxeq_preset[0]_i_1_n_0\
    );
\rxeq_preset[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8FFA800"
    )
        port map (
      I0 => rxeq_preset_reg2(1),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I3 => \rxeq_preset[2]_i_2_n_0\,
      I4 => \rxeq_preset_reg_n_0_[1]\,
      O => \rxeq_preset[1]_i_1_n_0\
    );
\rxeq_preset[2]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8FFA800"
    )
        port map (
      I0 => rxeq_preset_reg2(2),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I3 => \rxeq_preset[2]_i_2_n_0\,
      I4 => \rxeq_preset_reg_n_0_[2]\,
      O => \rxeq_preset[2]_i_1_n_0\
    );
\rxeq_preset[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF0100"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[6]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[5]\,
      I3 => \rxeq_preset[2]_i_3_n_0\,
      I4 => rxeq_adapt_done_reg_i_2_n_0,
      I5 => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      O => \rxeq_preset[2]_i_2_n_0\
    );
\rxeq_preset[2]_i_3\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      O => \rxeq_preset[2]_i_3_n_0\
    );
\rxeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(0),
      R => \out\
    );
\rxeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(1),
      R => \out\
    );
\rxeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(2),
      R => \out\
    );
\rxeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_preset_reg1(0),
      Q => rxeq_preset_reg2(0),
      R => \out\
    );
\rxeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_preset_reg1(1),
      Q => rxeq_preset_reg2(1),
      R => \out\
    );
\rxeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_preset_reg1(2),
      Q => rxeq_preset_reg2(2),
      R => \out\
    );
\rxeq_preset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \rxeq_preset[0]_i_1_n_0\,
      Q => \rxeq_preset_reg_n_0_[0]\,
      R => \out\
    );
\rxeq_preset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \rxeq_preset[1]_i_1_n_0\,
      Q => \rxeq_preset_reg_n_0_[1]\,
      R => \out\
    );
\rxeq_preset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \rxeq_preset[2]_i_1_n_0\,
      Q => \rxeq_preset_reg_n_0_[2]\,
      R => \out\
    );
rxeq_preset_valid_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      Q => rxeq_preset_valid,
      R => \out\
    );
rxeq_scan_i: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_rxeq_scan_22
     port map (
      D(2) => rxeq_scan_i_n_2,
      D(1) => rxeq_scan_i_n_3,
      D(0) => rxeq_scan_i_n_4,
      \FSM_onehot_fsm_rx_reg[5]\(2) => \rxeq_cnt_reg_n_0_[2]\,
      \FSM_onehot_fsm_rx_reg[5]\(1) => \rxeq_cnt_reg_n_0_[1]\,
      \FSM_onehot_fsm_rx_reg[5]\(0) => \rxeq_cnt_reg_n_0_[0]\,
      Q(4) => \FSM_onehot_fsm_rx_reg_n_0_[6]\,
      Q(3) => \FSM_onehot_fsm_rx_reg_n_0_[5]\,
      Q(2) => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      Q(1) => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      Q(0) => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      adapt_done_cnt_reg_0(1 downto 0) => rxeq_control_reg2(1 downto 0),
      adapt_done_reg_0 => rxeq_scan_i_n_0,
      \fs_reg1_reg[5]_0\(5) => \rxeq_fs_reg_n_0_[5]\,
      \fs_reg1_reg[5]_0\(4) => \rxeq_fs_reg_n_0_[4]\,
      \fs_reg1_reg[5]_0\(3) => \rxeq_fs_reg_n_0_[3]\,
      \fs_reg1_reg[5]_0\(2) => \rxeq_fs_reg_n_0_[2]\,
      \fs_reg1_reg[5]_0\(1) => \rxeq_fs_reg_n_0_[1]\,
      \fs_reg1_reg[5]_0\(0) => \rxeq_fs_reg_n_0_[0]\,
      \fs_reg2_reg[5]_0\ => \fs_reg2_reg[5]\,
      \lf_reg1_reg[5]_0\(5) => \rxeq_lf_reg_n_0_[5]\,
      \lf_reg1_reg[5]_0\(4) => \rxeq_lf_reg_n_0_[4]\,
      \lf_reg1_reg[5]_0\(3) => \rxeq_lf_reg_n_0_[3]\,
      \lf_reg1_reg[5]_0\(2) => \rxeq_lf_reg_n_0_[2]\,
      \lf_reg1_reg[5]_0\(1) => \rxeq_lf_reg_n_0_[1]\,
      \lf_reg1_reg[5]_0\(0) => \rxeq_lf_reg_n_0_[0]\,
      new_txcoeff_done_reg_0 => rxeq_scan_i_n_1,
      new_txcoeff_req_reg1_reg_0 => rxeq_new_txcoeff_req_reg_n_0,
      \out\ => \out\,
      \preset_reg1_reg[2]_0\(2) => \rxeq_preset_reg_n_0_[2]\,
      \preset_reg1_reg[2]_0\(1) => \rxeq_preset_reg_n_0_[1]\,
      \preset_reg1_reg[2]_0\(0) => \rxeq_preset_reg_n_0_[0]\,
      rxeq_adapt_done_reg => rxeq_adapt_done_i_2_n_0,
      rxeq_adapt_done_reg_0 => \^rxeq_adapt_done_reg_0\,
      rxeq_adapt_done_reg_reg => \FSM_onehot_fsm_rx[1]_i_2_n_0\,
      rxeq_adapt_done_reg_reg_0 => rxeq_adapt_done_reg_i_2_n_0,
      rxeq_adapt_done_reg_reg_1 => rxeq_adapt_done_reg_reg_n_0,
      rxeq_new_txcoeff_req => rxeq_new_txcoeff_req,
      rxeq_preset_valid => rxeq_preset_valid,
      \txcoeff_reg1_reg[17]_0\(17) => \rxeq_txcoeff_reg_n_0_[17]\,
      \txcoeff_reg1_reg[17]_0\(16) => \rxeq_txcoeff_reg_n_0_[16]\,
      \txcoeff_reg1_reg[17]_0\(15) => \rxeq_txcoeff_reg_n_0_[15]\,
      \txcoeff_reg1_reg[17]_0\(14) => \rxeq_txcoeff_reg_n_0_[14]\,
      \txcoeff_reg1_reg[17]_0\(13) => \rxeq_txcoeff_reg_n_0_[13]\,
      \txcoeff_reg1_reg[17]_0\(12) => \rxeq_txcoeff_reg_n_0_[12]\,
      \txcoeff_reg1_reg[17]_0\(11) => \rxeq_txcoeff_reg_n_0_[11]\,
      \txcoeff_reg1_reg[17]_0\(10) => \rxeq_txcoeff_reg_n_0_[10]\,
      \txcoeff_reg1_reg[17]_0\(9) => \rxeq_txcoeff_reg_n_0_[9]\,
      \txcoeff_reg1_reg[17]_0\(8) => \rxeq_txcoeff_reg_n_0_[8]\,
      \txcoeff_reg1_reg[17]_0\(7) => \rxeq_txcoeff_reg_n_0_[7]\,
      \txcoeff_reg1_reg[17]_0\(6) => \rxeq_txcoeff_reg_n_0_[6]\,
      \txcoeff_reg1_reg[17]_0\(5) => \rxeq_txcoeff_reg_n_0_[5]\,
      \txcoeff_reg1_reg[17]_0\(4) => \rxeq_txcoeff_reg_n_0_[4]\,
      \txcoeff_reg1_reg[17]_0\(3) => \rxeq_txcoeff_reg_n_0_[3]\,
      \txcoeff_reg1_reg[17]_0\(2) => \rxeq_txcoeff_reg_n_0_[2]\,
      \txcoeff_reg1_reg[17]_0\(1) => \rxeq_txcoeff_reg_n_0_[1]\,
      \txcoeff_reg1_reg[17]_0\(0) => \rxeq_txcoeff_reg_n_0_[0]\,
      \txpreset_reg1_reg[3]_0\(3) => \rxeq_txpreset_reg_n_0_[3]\,
      \txpreset_reg1_reg[3]_0\(2) => \rxeq_txpreset_reg_n_0_[2]\,
      \txpreset_reg1_reg[3]_0\(1) => \rxeq_txpreset_reg_n_0_[1]\,
      \txpreset_reg1_reg[3]_0\(0) => \rxeq_txpreset_reg_n_0_[0]\
    );
\rxeq_txcoeff[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \rxeq_txcoeff_reg_n_0_[6]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(0)
    );
\rxeq_txcoeff[10]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \rxeq_txcoeff_reg_n_0_[16]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(10)
    );
\rxeq_txcoeff[11]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \rxeq_txcoeff_reg_n_0_[17]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(11)
    );
\rxeq_txcoeff[12]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => txeq_deemph_reg2(0),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(12)
    );
\rxeq_txcoeff[13]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => txeq_deemph_reg2(1),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(13)
    );
\rxeq_txcoeff[14]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => txeq_deemph_reg2(2),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(14)
    );
\rxeq_txcoeff[15]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => txeq_deemph_reg2(3),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(15)
    );
\rxeq_txcoeff[16]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => txeq_deemph_reg2(4),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(16)
    );
\rxeq_txcoeff[17]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => txeq_deemph_reg2(5),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(17)
    );
\rxeq_txcoeff[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \rxeq_txcoeff_reg_n_0_[7]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(1)
    );
\rxeq_txcoeff[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \rxeq_txcoeff_reg_n_0_[8]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(2)
    );
\rxeq_txcoeff[3]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \rxeq_txcoeff_reg_n_0_[9]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(3)
    );
\rxeq_txcoeff[4]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \rxeq_txcoeff_reg_n_0_[10]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(4)
    );
\rxeq_txcoeff[5]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \rxeq_txcoeff_reg_n_0_[11]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(5)
    );
\rxeq_txcoeff[6]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \rxeq_txcoeff_reg_n_0_[12]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(6)
    );
\rxeq_txcoeff[7]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \rxeq_txcoeff_reg_n_0_[13]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(7)
    );
\rxeq_txcoeff[8]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \rxeq_txcoeff_reg_n_0_[14]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(8)
    );
\rxeq_txcoeff[9]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \rxeq_txcoeff_reg_n_0_[15]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(9)
    );
\rxeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(0),
      Q => \rxeq_txcoeff_reg_n_0_[0]\,
      R => \out\
    );
\rxeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(10),
      Q => \rxeq_txcoeff_reg_n_0_[10]\,
      R => \out\
    );
\rxeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(11),
      Q => \rxeq_txcoeff_reg_n_0_[11]\,
      R => \out\
    );
\rxeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(12),
      Q => \rxeq_txcoeff_reg_n_0_[12]\,
      R => \out\
    );
\rxeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(13),
      Q => \rxeq_txcoeff_reg_n_0_[13]\,
      R => \out\
    );
\rxeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(14),
      Q => \rxeq_txcoeff_reg_n_0_[14]\,
      R => \out\
    );
\rxeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(15),
      Q => \rxeq_txcoeff_reg_n_0_[15]\,
      R => \out\
    );
\rxeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(16),
      Q => \rxeq_txcoeff_reg_n_0_[16]\,
      R => \out\
    );
\rxeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(17),
      Q => \rxeq_txcoeff_reg_n_0_[17]\,
      R => \out\
    );
\rxeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(1),
      Q => \rxeq_txcoeff_reg_n_0_[1]\,
      R => \out\
    );
\rxeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(2),
      Q => \rxeq_txcoeff_reg_n_0_[2]\,
      R => \out\
    );
\rxeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(3),
      Q => \rxeq_txcoeff_reg_n_0_[3]\,
      R => \out\
    );
\rxeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(4),
      Q => \rxeq_txcoeff_reg_n_0_[4]\,
      R => \out\
    );
\rxeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(5),
      Q => \rxeq_txcoeff_reg_n_0_[5]\,
      R => \out\
    );
\rxeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(6),
      Q => \rxeq_txcoeff_reg_n_0_[6]\,
      R => \out\
    );
\rxeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(7),
      Q => \rxeq_txcoeff_reg_n_0_[7]\,
      R => \out\
    );
\rxeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(8),
      Q => \rxeq_txcoeff_reg_n_0_[8]\,
      R => \out\
    );
\rxeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txcoeff(9),
      Q => \rxeq_txcoeff_reg_n_0_[9]\,
      R => \out\
    );
\rxeq_txpreset[0]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => rxeq_txpreset_reg2(0),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txpreset(0)
    );
\rxeq_txpreset[1]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => rxeq_txpreset_reg2(1),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txpreset(1)
    );
\rxeq_txpreset[2]_i_1\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => rxeq_txpreset_reg2(2),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txpreset(2)
    );
\rxeq_txpreset[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF404"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[6]\,
      I1 => \rxeq_txpreset[3]_i_3_n_0\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I3 => rxeq_control_reg2(1),
      I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      O => \rxeq_txpreset[3]_i_1_n_0\
    );
\rxeq_txpreset[3]_i_2\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => rxeq_txpreset_reg2(3),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txpreset(3)
    );
\rxeq_txpreset[3]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[5]\,
      O => \rxeq_txpreset[3]_i_3_n_0\
    );
\rxeq_txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(0),
      R => \out\
    );
\rxeq_txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(1),
      R => \out\
    );
\rxeq_txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(2),
      R => \out\
    );
\rxeq_txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(3),
      R => \out\
    );
\rxeq_txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_txpreset_reg1(0),
      Q => rxeq_txpreset_reg2(0),
      R => \out\
    );
\rxeq_txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_txpreset_reg1(1),
      Q => rxeq_txpreset_reg2(1),
      R => \out\
    );
\rxeq_txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_txpreset_reg1(2),
      Q => rxeq_txpreset_reg2(2),
      R => \out\
    );
\rxeq_txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_txpreset_reg1(3),
      Q => rxeq_txpreset_reg2(3),
      R => \out\
    );
\rxeq_txpreset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txpreset(0),
      Q => \rxeq_txpreset_reg_n_0_[0]\,
      R => \out\
    );
\rxeq_txpreset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txpreset(1),
      Q => \rxeq_txpreset_reg_n_0_[1]\,
      R => \out\
    );
\rxeq_txpreset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txpreset(2),
      Q => \rxeq_txpreset_reg_n_0_[2]\,
      R => \out\
    );
\rxeq_txpreset_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1_n_0\,
      D => rxeq_txpreset(3),
      Q => \rxeq_txpreset_reg_n_0_[3]\,
      R => \out\
    );
rxeq_user_en_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_en_reg1,
      R => \out\
    );
rxeq_user_en_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_en_reg1,
      Q => rxeq_user_en_reg2,
      R => \out\
    );
rxeq_user_mode_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_mode_reg1,
      R => \out\
    );
rxeq_user_mode_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_mode_reg1,
      Q => rxeq_user_mode_reg2,
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(0),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(10),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(11),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(12),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(13),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(14),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(15),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(16),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(17),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(1),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(2),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(3),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(4),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(5),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(6),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(7),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(8),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(9),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(0),
      Q => rxeq_user_txcoeff_reg2(0),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(10),
      Q => rxeq_user_txcoeff_reg2(10),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(11),
      Q => rxeq_user_txcoeff_reg2(11),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(12),
      Q => rxeq_user_txcoeff_reg2(12),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(13),
      Q => rxeq_user_txcoeff_reg2(13),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(14),
      Q => rxeq_user_txcoeff_reg2(14),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(15),
      Q => rxeq_user_txcoeff_reg2(15),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(16),
      Q => rxeq_user_txcoeff_reg2(16),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(17),
      Q => rxeq_user_txcoeff_reg2(17),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(1),
      Q => rxeq_user_txcoeff_reg2(1),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(2),
      Q => rxeq_user_txcoeff_reg2(2),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(3),
      Q => rxeq_user_txcoeff_reg2(3),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(4),
      Q => rxeq_user_txcoeff_reg2(4),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(5),
      Q => rxeq_user_txcoeff_reg2(5),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(6),
      Q => rxeq_user_txcoeff_reg2(6),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(7),
      Q => rxeq_user_txcoeff_reg2(7),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(8),
      Q => rxeq_user_txcoeff_reg2(8),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(9),
      Q => rxeq_user_txcoeff_reg2(9),
      R => \out\
    );
\txeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_control_reg1(0),
      R => \out\
    );
\txeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_control_reg1(1),
      R => \out\
    );
\txeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_control_reg1(0),
      Q => txeq_control_reg2(0),
      R => \out\
    );
\txeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_control_reg1(1),
      Q => txeq_control_reg2(1),
      R => \out\
    );
\txeq_deemph_reg1_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(0),
      S => \out\
    );
\txeq_deemph_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(1),
      R => \out\
    );
\txeq_deemph_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(2),
      R => \out\
    );
\txeq_deemph_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(3),
      R => \out\
    );
\txeq_deemph_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(4),
      R => \out\
    );
\txeq_deemph_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(5),
      R => \out\
    );
\txeq_deemph_reg2_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_deemph_reg1(0),
      Q => txeq_deemph_reg2(0),
      S => \out\
    );
\txeq_deemph_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_deemph_reg1(1),
      Q => txeq_deemph_reg2(1),
      R => \out\
    );
\txeq_deemph_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_deemph_reg1(2),
      Q => txeq_deemph_reg2(2),
      R => \out\
    );
\txeq_deemph_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_deemph_reg1(3),
      Q => txeq_deemph_reg2(3),
      R => \out\
    );
\txeq_deemph_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_deemph_reg1(4),
      Q => txeq_deemph_reg2(4),
      R => \out\
    );
\txeq_deemph_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_deemph_reg1(5),
      Q => txeq_deemph_reg2(5),
      R => \out\
    );
\txeq_preset[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00040000"
    )
        port map (
      I0 => txeq_preset_reg2(1),
      I1 => txeq_preset_reg2(3),
      I2 => \out\,
      I3 => txeq_preset_reg2(2),
      I4 => txeq_preset_reg2(0),
      O => p_0_out(0)
    );
\txeq_preset[10]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAEABBAF"
    )
        port map (
      I0 => \out\,
      I1 => txeq_preset_reg2(2),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(0),
      O => p_0_out(10)
    );
\txeq_preset[11]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF1811"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => \out\,
      O => p_0_out(11)
    );
\txeq_preset[12]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01111310"
    )
        port map (
      I0 => txeq_preset_reg2(3),
      I1 => \out\,
      I2 => txeq_preset_reg2(2),
      I3 => txeq_preset_reg2(0),
      I4 => txeq_preset_reg2(1),
      O => p_0_out(12)
    );
\txeq_preset[13]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01000010"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => \out\,
      I2 => txeq_preset_reg2(0),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(1),
      O => p_0_out(13)
    );
\txeq_preset[14]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00100100"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => \out\,
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(0),
      O => p_0_out(14)
    );
\txeq_preset[15]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F0F1"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(1),
      I2 => \out\,
      I3 => txeq_preset_reg2(3),
      O => p_0_out(15)
    );
\txeq_preset[16]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0006"
    )
        port map (
      I0 => txeq_preset_reg2(3),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(2),
      I3 => \out\,
      O => p_0_out(16)
    );
\txeq_preset[17]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AABA"
    )
        port map (
      I0 => \out\,
      I1 => fsm_tx(0),
      I2 => fsm_tx(1),
      I3 => fsm_tx(2),
      O => \txeq_preset[17]_i_1_n_0\
    );
\txeq_preset[17]_i_2\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF1091"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      I4 => \out\,
      O => p_0_out(17)
    );
\txeq_preset[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001004"
    )
        port map (
      I0 => \out\,
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(2),
      I4 => txeq_preset_reg2(0),
      O => p_0_out(1)
    );
\txeq_preset[2]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4440"
    )
        port map (
      I0 => \out\,
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(2),
      I3 => txeq_preset_reg2(0),
      O => p_0_out(2)
    );
\txeq_preset[3]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00441140"
    )
        port map (
      I0 => \out\,
      I1 => txeq_preset_reg2(2),
      I2 => txeq_preset_reg2(0),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(1),
      O => \txeq_preset[3]_i_1_n_0\
    );
\txeq_preset[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000AAAA3C00AAAA"
    )
        port map (
      I0 => \txeq_preset_reg_n_0_[7]\,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(2),
      I3 => \txeq_preset[7]_i_2_n_0\,
      I4 => \txeq_preset[17]_i_1_n_0\,
      I5 => \out\,
      O => \txeq_preset[7]_i_1_n_0\
    );
\txeq_preset[7]_i_2\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txeq_preset_reg2(1),
      I1 => txeq_preset_reg2(3),
      O => \txeq_preset[7]_i_2_n_0\
    );
\txeq_preset[8]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AABEAFAF"
    )
        port map (
      I0 => \out\,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(2),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(1),
      O => p_0_out(8)
    );
\txeq_preset[9]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CFCCCCFD"
    )
        port map (
      I0 => txeq_preset_reg2(1),
      I1 => \out\,
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(0),
      I4 => txeq_preset_reg2(2),
      O => p_0_out(9)
    );
txeq_preset_done_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => fsm_tx(2),
      I1 => fsm_tx(1),
      I2 => fsm_tx(0),
      O => txeq_preset_done_i_1_n_0
    );
txeq_preset_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_preset_done_i_1_n_0,
      Q => txeq_preset_done,
      R => \out\
    );
\txeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(0),
      R => \out\
    );
\txeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(1),
      R => \out\
    );
\txeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(2),
      R => \out\
    );
\txeq_preset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(3),
      R => \out\
    );
\txeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_preset_reg1(0),
      Q => txeq_preset_reg2(0),
      R => \out\
    );
\txeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_preset_reg1(1),
      Q => txeq_preset_reg2(1),
      R => \out\
    );
\txeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_preset_reg1(2),
      Q => txeq_preset_reg2(2),
      R => \out\
    );
\txeq_preset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_preset_reg1(3),
      Q => txeq_preset_reg2(3),
      R => \out\
    );
\txeq_preset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => p_0_out(0),
      Q => \txeq_preset_reg_n_0_[0]\,
      R => '0'
    );
\txeq_preset_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => p_0_out(10),
      Q => \txeq_preset_reg_n_0_[10]\,
      R => '0'
    );
\txeq_preset_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => p_0_out(11),
      Q => \txeq_preset_reg_n_0_[11]\,
      R => '0'
    );
\txeq_preset_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => p_0_out(12),
      Q => \txeq_preset_reg_n_0_[12]\,
      R => '0'
    );
\txeq_preset_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => p_0_out(13),
      Q => \txeq_preset_reg_n_0_[13]\,
      R => '0'
    );
\txeq_preset_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => p_0_out(14),
      Q => \txeq_preset_reg_n_0_[14]\,
      R => '0'
    );
\txeq_preset_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => p_0_out(15),
      Q => \txeq_preset_reg_n_0_[15]\,
      R => '0'
    );
\txeq_preset_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => p_0_out(16),
      Q => \txeq_preset_reg_n_0_[16]\,
      R => '0'
    );
\txeq_preset_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => p_0_out(17),
      Q => \txeq_preset_reg_n_0_[17]\,
      R => '0'
    );
\txeq_preset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => p_0_out(1),
      Q => \txeq_preset_reg_n_0_[1]\,
      R => '0'
    );
\txeq_preset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => p_0_out(2),
      Q => \txeq_preset_reg_n_0_[2]\,
      R => '0'
    );
\txeq_preset_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => \txeq_preset[3]_i_1_n_0\,
      Q => \txeq_preset_reg_n_0_[3]\,
      R => '0'
    );
\txeq_preset_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \txeq_preset[7]_i_1_n_0\,
      Q => \txeq_preset_reg_n_0_[7]\,
      R => '0'
    );
\txeq_preset_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => p_0_out(8),
      Q => \txeq_preset_reg_n_0_[8]\,
      R => '0'
    );
\txeq_preset_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1_n_0\,
      D => p_0_out(9),
      Q => \txeq_preset_reg_n_0_[9]\,
      R => '0'
    );
\txeq_txcoeff[0]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"45404040"
    )
        port map (
      I0 => fsm_tx(2),
      I1 => \txeq_txcoeff[0]_i_2_n_0\,
      I2 => fsm_tx(1),
      I3 => \txeq_txcoeff_reg_n_0_[6]\,
      I4 => fsm_tx(0),
      O => \txeq_txcoeff[0]_i_1_n_0\
    );
\txeq_txcoeff[0]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[7]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[6]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[0]\,
      O => \txeq_txcoeff[0]_i_2_n_0\
    );
\txeq_txcoeff[10]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[9]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[10]_i_2_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[16]\,
      O => \txeq_txcoeff[10]_i_1_n_0\
    );
\txeq_txcoeff[10]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[17]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[16]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[10]\,
      O => \txeq_txcoeff[10]_i_2_n_0\
    );
\txeq_txcoeff[11]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[10]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[11]_i_2_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[17]\,
      O => \txeq_txcoeff[11]_i_1_n_0\
    );
\txeq_txcoeff[11]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[18]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[17]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[11]\,
      O => \txeq_txcoeff[11]_i_2_n_0\
    );
\txeq_txcoeff[12]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[11]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[12]_i_2_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[18]\,
      O => \txeq_txcoeff[12]_i_1_n_0\
    );
\txeq_txcoeff[12]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => txeq_deemph_reg2(0),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[18]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[12]\,
      O => \txeq_txcoeff[12]_i_2_n_0\
    );
\txeq_txcoeff[13]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[12]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[13]_i_2_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => txeq_deemph_reg2(0),
      O => \txeq_txcoeff[13]_i_1_n_0\
    );
\txeq_txcoeff[13]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => txeq_deemph_reg2(1),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => txeq_deemph_reg2(0),
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[13]\,
      O => \txeq_txcoeff[13]_i_2_n_0\
    );
\txeq_txcoeff[14]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[13]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[14]_i_2_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => txeq_deemph_reg2(1),
      O => \txeq_txcoeff[14]_i_1_n_0\
    );
\txeq_txcoeff[14]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => txeq_deemph_reg2(2),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => txeq_deemph_reg2(1),
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[14]\,
      O => \txeq_txcoeff[14]_i_2_n_0\
    );
\txeq_txcoeff[15]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[14]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[15]_i_2_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => txeq_deemph_reg2(2),
      O => \txeq_txcoeff[15]_i_1_n_0\
    );
\txeq_txcoeff[15]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => txeq_deemph_reg2(3),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => txeq_deemph_reg2(2),
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[15]\,
      O => \txeq_txcoeff[15]_i_2_n_0\
    );
\txeq_txcoeff[16]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[15]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[16]_i_2_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => txeq_deemph_reg2(3),
      O => \txeq_txcoeff[16]_i_1_n_0\
    );
\txeq_txcoeff[16]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => txeq_deemph_reg2(4),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => txeq_deemph_reg2(3),
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[16]\,
      O => \txeq_txcoeff[16]_i_2_n_0\
    );
\txeq_txcoeff[17]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[16]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[17]_i_2_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => txeq_deemph_reg2(4),
      O => \txeq_txcoeff[17]_i_1_n_0\
    );
\txeq_txcoeff[17]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => txeq_deemph_reg2(5),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => txeq_deemph_reg2(4),
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[17]\,
      O => \txeq_txcoeff[17]_i_2_n_0\
    );
\txeq_txcoeff[18]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF040FFF"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      I2 => fsm_tx(2),
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      O => txeq_txcoeff
    );
\txeq_txcoeff[18]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"202020202F202020"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[17]\,
      I1 => fsm_tx(1),
      I2 => fsm_tx(2),
      I3 => txeq_deemph_reg2(5),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff[18]_i_3_n_0\,
      O => \txeq_txcoeff[18]_i_2_n_0\
    );
\txeq_txcoeff[18]_i_3\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I1 => fsm_tx(1),
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      O => \txeq_txcoeff[18]_i_3_n_0\
    );
\txeq_txcoeff[1]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[0]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[1]_i_2_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[7]\,
      O => \txeq_txcoeff[1]_i_1_n_0\
    );
\txeq_txcoeff[1]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[8]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[7]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[1]\,
      O => \txeq_txcoeff[1]_i_2_n_0\
    );
\txeq_txcoeff[2]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[1]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[2]_i_2_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[8]\,
      O => \txeq_txcoeff[2]_i_1_n_0\
    );
\txeq_txcoeff[2]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[9]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[8]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[2]\,
      O => \txeq_txcoeff[2]_i_2_n_0\
    );
\txeq_txcoeff[3]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[2]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[3]_i_2_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[9]\,
      O => \txeq_txcoeff[3]_i_1_n_0\
    );
\txeq_txcoeff[3]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[10]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[9]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[3]\,
      O => \txeq_txcoeff[3]_i_2_n_0\
    );
\txeq_txcoeff[4]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000AE00AEAEAEAE"
    )
        port map (
      I0 => \txeq_txcoeff[4]_i_2_n_0\,
      I1 => \txeq_txcoeff_reg_n_0_[10]\,
      I2 => \txeq_txcoeff[5]_i_3_n_0\,
      I3 => \txeq_txcoeff_reg_n_0_[3]\,
      I4 => fsm_tx(1),
      I5 => fsm_tx(2),
      O => \txeq_txcoeff[4]_i_1_n_0\
    );
\txeq_txcoeff[4]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAEAAAAAAAAAAAAA"
    )
        port map (
      I0 => fsm_tx(2),
      I1 => fsm_tx(1),
      I2 => fsm_tx(0),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I5 => \txeq_txcoeff_reg_n_0_[11]\,
      O => \txeq_txcoeff[4]_i_2_n_0\
    );
\txeq_txcoeff[5]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000AE00AEAEAEAE"
    )
        port map (
      I0 => \txeq_txcoeff[5]_i_2_n_0\,
      I1 => \txeq_txcoeff_reg_n_0_[11]\,
      I2 => \txeq_txcoeff[5]_i_3_n_0\,
      I3 => \txeq_txcoeff_reg_n_0_[4]\,
      I4 => fsm_tx(1),
      I5 => fsm_tx(2),
      O => \txeq_txcoeff[5]_i_1_n_0\
    );
\txeq_txcoeff[5]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAEAAAAAAAAAAAAA"
    )
        port map (
      I0 => fsm_tx(2),
      I1 => fsm_tx(1),
      I2 => fsm_tx(0),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I5 => \txeq_txcoeff_reg_n_0_[12]\,
      O => \txeq_txcoeff[5]_i_2_n_0\
    );
\txeq_txcoeff[5]_i_3\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"40FF"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I1 => fsm_tx(1),
      I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I3 => fsm_tx(0),
      O => \txeq_txcoeff[5]_i_3_n_0\
    );
\txeq_txcoeff[6]_i_1\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[5]\,
      I1 => fsm_tx(1),
      I2 => fsm_tx(2),
      I3 => \txeq_txcoeff[6]_i_2_n_0\,
      O => \txeq_txcoeff[6]_i_1_n_0\
    );
\txeq_txcoeff[6]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0E0A0A0A020A0A0"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[12]\,
      I1 => fsm_tx(1),
      I2 => fsm_tx(0),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I5 => \txeq_txcoeff_reg_n_0_[13]\,
      O => \txeq_txcoeff[6]_i_2_n_0\
    );
\txeq_txcoeff[7]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[6]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[7]_i_2_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[13]\,
      O => \txeq_txcoeff[7]_i_1_n_0\
    );
\txeq_txcoeff[7]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[14]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[13]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[7]\,
      O => \txeq_txcoeff[7]_i_2_n_0\
    );
\txeq_txcoeff[8]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[7]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[8]_i_2_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[14]\,
      O => \txeq_txcoeff[8]_i_1_n_0\
    );
\txeq_txcoeff[8]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[15]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[14]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[8]\,
      O => \txeq_txcoeff[8]_i_2_n_0\
    );
\txeq_txcoeff[9]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[8]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[9]_i_2_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[15]\,
      O => \txeq_txcoeff[9]_i_1_n_0\
    );
\txeq_txcoeff[9]_i_2\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[16]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[15]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[9]\,
      O => \txeq_txcoeff[9]_i_2_n_0\
    );
\txeq_txcoeff_cnt[0]_i_1\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000004000F000400"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      I2 => fsm_tx(2),
      I3 => fsm_tx(0),
      I4 => fsm_tx(1),
      I5 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      O => txeq_txcoeff_cnt(0)
    );
\txeq_txcoeff_cnt[1]_i_1\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00006000"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I2 => fsm_tx(0),
      I3 => fsm_tx(1),
      I4 => fsm_tx(2),
      O => txeq_txcoeff_cnt(1)
    );
\txeq_txcoeff_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_txcoeff_cnt(0),
      Q => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      R => \out\
    );
\txeq_txcoeff_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_txcoeff_cnt(1),
      Q => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      R => \out\
    );
\txeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[0]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[0]\,
      R => \out\
    );
\txeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[10]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[10]\,
      R => \out\
    );
\txeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[11]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[11]\,
      R => \out\
    );
\txeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[12]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[12]\,
      R => \out\
    );
\txeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[13]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[13]\,
      R => \out\
    );
\txeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[14]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[14]\,
      R => \out\
    );
\txeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[15]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[15]\,
      R => \out\
    );
\txeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[16]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[16]\,
      R => \out\
    );
\txeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[17]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[17]\,
      R => \out\
    );
\txeq_txcoeff_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[18]_i_2_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[18]\,
      R => \out\
    );
\txeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[1]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[1]\,
      R => \out\
    );
\txeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[2]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[2]\,
      R => \out\
    );
\txeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[3]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[3]\,
      R => \out\
    );
\txeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[4]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[4]\,
      R => \out\
    );
\txeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[5]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[5]\,
      R => \out\
    );
\txeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[6]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[6]\,
      R => \out\
    );
\txeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[7]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[7]\,
      R => \out\
    );
\txeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[8]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[8]\,
      R => \out\
    );
\txeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[9]_i_1_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[9]\,
      R => \out\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_eq_18 is
  port (
    rxeq_adapt_done_reg_0 : out STD_LOGIC;
    TXPRECURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 );
    TXMAINCURSOR : out STD_LOGIC_VECTOR ( 6 downto 0 );
    TXPOSTCURSOR : out STD_LOGIC_VECTOR ( 4 downto 0 );
    \out\ : in STD_LOGIC;
    \fs_reg2_reg[5]\ : in STD_LOGIC;
    rate_gen3_1 : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_eq_18 : entity is "spec7_pcie_7x_0_pipe_eq";
end spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_eq_18;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_eq_18 is
  signal \FSM_onehot_fsm_rx[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx_reg_n_0_[1]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx_reg_n_0_[2]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx_reg_n_0_[3]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx_reg_n_0_[4]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx_reg_n_0_[5]\ : STD_LOGIC;
  signal \FSM_onehot_fsm_rx_reg_n_0_[6]\ : STD_LOGIC;
  signal \FSM_sequential_fsm_tx[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \FSM_sequential_fsm_tx[2]_i_2__0_n_0\ : STD_LOGIC;
  signal fsm_tx : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \fsm_tx__0\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal gen3_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of gen3_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of gen3_reg1 : signal is "true";
  signal gen3_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of gen3_reg2 : signal is "NO";
  attribute async_reg of gen3_reg2 : signal is "true";
  signal p_0_out : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal \rxeq_adapt_done_i_2__0_n_0\ : STD_LOGIC;
  signal \^rxeq_adapt_done_reg_0\ : STD_LOGIC;
  signal \rxeq_adapt_done_reg_i_2__0_n_0\ : STD_LOGIC;
  signal rxeq_adapt_done_reg_reg_n_0 : STD_LOGIC;
  signal rxeq_cnt : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal \rxeq_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_cnt_reg_n_0_[2]\ : STD_LOGIC;
  signal rxeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_control_reg1 : signal is "NO";
  attribute async_reg of rxeq_control_reg1 : signal is "true";
  signal rxeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_control_reg2 : signal is "NO";
  attribute async_reg of rxeq_control_reg2 : signal is "true";
  signal rxeq_fs : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_fs[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \rxeq_fs_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_fs_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_fs_reg_n_0_[2]\ : STD_LOGIC;
  signal \rxeq_fs_reg_n_0_[3]\ : STD_LOGIC;
  signal \rxeq_fs_reg_n_0_[4]\ : STD_LOGIC;
  signal \rxeq_fs_reg_n_0_[5]\ : STD_LOGIC;
  signal rxeq_lf : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \rxeq_lf[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \rxeq_lf_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_lf_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_lf_reg_n_0_[2]\ : STD_LOGIC;
  signal \rxeq_lf_reg_n_0_[3]\ : STD_LOGIC;
  signal \rxeq_lf_reg_n_0_[4]\ : STD_LOGIC;
  signal \rxeq_lf_reg_n_0_[5]\ : STD_LOGIC;
  signal rxeq_lffs_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_lffs_reg1 : signal is "NO";
  attribute async_reg of rxeq_lffs_reg1 : signal is "true";
  signal rxeq_lffs_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_lffs_reg2 : signal is "NO";
  attribute async_reg of rxeq_lffs_reg2 : signal is "true";
  signal rxeq_new_txcoeff_req : STD_LOGIC;
  signal rxeq_new_txcoeff_req_reg_n_0 : STD_LOGIC;
  signal \rxeq_preset[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \rxeq_preset[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \rxeq_preset[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \rxeq_preset[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \rxeq_preset[2]_i_3__0_n_0\ : STD_LOGIC;
  signal rxeq_preset_reg1 : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_preset_reg1 : signal is "NO";
  attribute async_reg of rxeq_preset_reg1 : signal is "true";
  signal rxeq_preset_reg2 : STD_LOGIC_VECTOR ( 2 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_preset_reg2 : signal is "NO";
  attribute async_reg of rxeq_preset_reg2 : signal is "true";
  signal \rxeq_preset_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_preset_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_preset_reg_n_0_[2]\ : STD_LOGIC;
  signal rxeq_preset_valid : STD_LOGIC;
  signal rxeq_scan_i_n_0 : STD_LOGIC;
  signal rxeq_scan_i_n_1 : STD_LOGIC;
  signal rxeq_scan_i_n_2 : STD_LOGIC;
  signal rxeq_scan_i_n_3 : STD_LOGIC;
  signal rxeq_scan_i_n_4 : STD_LOGIC;
  signal rxeq_txcoeff : STD_LOGIC_VECTOR ( 17 downto 0 );
  signal \rxeq_txcoeff_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[10]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[11]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[12]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[13]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[14]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[15]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[16]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[17]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[2]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[3]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[4]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[5]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[6]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[7]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[8]\ : STD_LOGIC;
  signal \rxeq_txcoeff_reg_n_0_[9]\ : STD_LOGIC;
  signal rxeq_txpreset : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \rxeq_txpreset[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \rxeq_txpreset[3]_i_3__0_n_0\ : STD_LOGIC;
  signal rxeq_txpreset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_txpreset_reg1 : signal is "NO";
  attribute async_reg of rxeq_txpreset_reg1 : signal is "true";
  signal rxeq_txpreset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_txpreset_reg2 : signal is "NO";
  attribute async_reg of rxeq_txpreset_reg2 : signal is "true";
  signal \rxeq_txpreset_reg_n_0_[0]\ : STD_LOGIC;
  signal \rxeq_txpreset_reg_n_0_[1]\ : STD_LOGIC;
  signal \rxeq_txpreset_reg_n_0_[2]\ : STD_LOGIC;
  signal \rxeq_txpreset_reg_n_0_[3]\ : STD_LOGIC;
  signal rxeq_user_en_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxeq_user_en_reg1 : signal is "NO";
  attribute async_reg of rxeq_user_en_reg1 : signal is "true";
  signal rxeq_user_en_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxeq_user_en_reg2 : signal is "NO";
  attribute async_reg of rxeq_user_en_reg2 : signal is "true";
  signal rxeq_user_mode_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxeq_user_mode_reg1 : signal is "NO";
  attribute async_reg of rxeq_user_mode_reg1 : signal is "true";
  signal rxeq_user_mode_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of rxeq_user_mode_reg2 : signal is "NO";
  attribute async_reg of rxeq_user_mode_reg2 : signal is "true";
  signal rxeq_user_txcoeff_reg1 : STD_LOGIC_VECTOR ( 17 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_user_txcoeff_reg1 : signal is "NO";
  attribute async_reg of rxeq_user_txcoeff_reg1 : signal is "true";
  signal rxeq_user_txcoeff_reg2 : STD_LOGIC_VECTOR ( 17 downto 0 );
  attribute SHIFT_EXTRACT of rxeq_user_txcoeff_reg2 : signal is "NO";
  attribute async_reg of rxeq_user_txcoeff_reg2 : signal is "true";
  signal txeq_control_reg1 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of txeq_control_reg1 : signal is "NO";
  attribute async_reg of txeq_control_reg1 : signal is "true";
  signal txeq_control_reg2 : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute SHIFT_EXTRACT of txeq_control_reg2 : signal is "NO";
  attribute async_reg of txeq_control_reg2 : signal is "true";
  signal txeq_deemph_reg1 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT of txeq_deemph_reg1 : signal is "NO";
  attribute async_reg of txeq_deemph_reg1 : signal is "true";
  signal txeq_deemph_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  attribute SHIFT_EXTRACT of txeq_deemph_reg2 : signal is "NO";
  attribute async_reg of txeq_deemph_reg2 : signal is "true";
  signal \txeq_preset[17]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_preset[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_preset[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_preset[7]_i_2__0_n_0\ : STD_LOGIC;
  signal txeq_preset_done : STD_LOGIC;
  signal \txeq_preset_done_i_1__0_n_0\ : STD_LOGIC;
  signal txeq_preset_reg1 : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SHIFT_EXTRACT of txeq_preset_reg1 : signal is "NO";
  attribute async_reg of txeq_preset_reg1 : signal is "true";
  signal txeq_preset_reg2 : STD_LOGIC_VECTOR ( 3 downto 0 );
  attribute SHIFT_EXTRACT of txeq_preset_reg2 : signal is "NO";
  attribute async_reg of txeq_preset_reg2 : signal is "true";
  signal \txeq_preset_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[10]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[11]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[12]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[13]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[14]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[15]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[16]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[17]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[2]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[3]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[7]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[8]\ : STD_LOGIC;
  signal \txeq_preset_reg_n_0_[9]\ : STD_LOGIC;
  signal txeq_txcoeff : STD_LOGIC;
  signal \txeq_txcoeff[0]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[0]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[10]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[10]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[11]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[11]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[12]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[12]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[13]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[13]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[14]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[14]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[15]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[15]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[16]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[16]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[17]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[17]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[18]_i_3__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[1]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[1]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[2]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[2]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[3]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[3]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[4]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[4]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[5]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[5]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[5]_i_3__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[6]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[6]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[7]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[7]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[8]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[8]_i_2__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[9]_i_1__0_n_0\ : STD_LOGIC;
  signal \txeq_txcoeff[9]_i_2__0_n_0\ : STD_LOGIC;
  signal txeq_txcoeff_cnt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \txeq_txcoeff_cnt_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_txcoeff_cnt_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[0]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[10]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[11]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[12]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[13]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[14]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[15]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[16]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[17]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[18]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[1]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[2]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[3]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[4]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[5]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[6]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[7]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[8]\ : STD_LOGIC;
  signal \txeq_txcoeff_reg_n_0_[9]\ : STD_LOGIC;
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of \FSM_onehot_fsm_rx[4]_i_1__0\ : label is "soft_lutpair59";
  attribute FSM_ENCODED_STATES : string;
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[1]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[2]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[3]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[4]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[5]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001";
  attribute FSM_ENCODED_STATES of \FSM_onehot_fsm_rx_reg[6]\ : label is "FSM_RXEQ_PRESET:0000100,FSM_RXEQ_TXCOEFF:0001000,FSM_RXEQ_LF:0010000,FSM_RXEQ_NEW_TXCOEFF_REQ:0100000,FSM_RXEQ_DONE:1000000,FSM_RXEQ_IDLE:0000010,iSTATE:0000001";
  attribute SOFT_HLUTNM of \FSM_sequential_fsm_tx[2]_i_2__0\ : label is "soft_lutpair58";
  attribute FSM_ENCODED_STATES of \FSM_sequential_fsm_tx_reg[0]\ : label is "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000";
  attribute FSM_ENCODED_STATES of \FSM_sequential_fsm_tx_reg[1]\ : label is "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000";
  attribute FSM_ENCODED_STATES of \FSM_sequential_fsm_tx_reg[2]\ : label is "FSM_TXEQ_QUERY:101,FSM_TXEQ_PRESET:010,FSM_TXEQ_TXCOEFF:011,FSM_TXEQ_REMAP:100,FSM_TXEQ_DONE:110,FSM_TXEQ_IDLE:001,iSTATE:000";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of gen3_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of gen3_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of gen3_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of gen3_reg2_reg : label is std.standard.true;
  attribute KEEP of gen3_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of gen3_reg2_reg : label is "NO";
  attribute SOFT_HLUTNM of \rxeq_cnt[1]_i_1__0\ : label is "soft_lutpair61";
  attribute SOFT_HLUTNM of \rxeq_cnt[2]_i_1__0\ : label is "soft_lutpair59";
  attribute ASYNC_REG_boolean of \rxeq_control_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_control_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_control_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_control_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_control_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_control_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_control_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_control_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_control_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg1_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg1_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_lffs_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_lffs_reg2_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_lffs_reg2_reg[5]\ : label is "NO";
  attribute SOFT_HLUTNM of \rxeq_preset[2]_i_3__0\ : label is "soft_lutpair61";
  attribute ASYNC_REG_boolean of \rxeq_preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_preset_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_preset_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_preset_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_preset_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_preset_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_preset_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_preset_reg2_reg[2]\ : label is "NO";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[0]_i_1__0\ : label is "soft_lutpair62";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[10]_i_1__0\ : label is "soft_lutpair67";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[11]_i_1__0\ : label is "soft_lutpair67";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[1]_i_1__0\ : label is "soft_lutpair62";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[2]_i_1__0\ : label is "soft_lutpair63";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[3]_i_1__0\ : label is "soft_lutpair63";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[4]_i_1__0\ : label is "soft_lutpair64";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[5]_i_1__0\ : label is "soft_lutpair64";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[6]_i_1__0\ : label is "soft_lutpair65";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[7]_i_1__0\ : label is "soft_lutpair65";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[8]_i_1__0\ : label is "soft_lutpair66";
  attribute SOFT_HLUTNM of \rxeq_txcoeff[9]_i_1__0\ : label is "soft_lutpair66";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_txpreset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_txpreset_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_txpreset_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of rxeq_user_en_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_en_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxeq_user_en_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxeq_user_en_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_en_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxeq_user_en_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxeq_user_mode_reg1_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_mode_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxeq_user_mode_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of rxeq_user_mode_reg2_reg : label is std.standard.true;
  attribute KEEP of rxeq_user_mode_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of rxeq_user_mode_reg2_reg : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[10]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[10]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[10]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[11]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[11]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[11]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[12]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[12]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[12]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[13]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[13]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[13]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[14]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[14]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[14]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[15]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[15]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[15]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[16]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[16]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[16]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[17]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[17]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[17]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[6]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[6]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[6]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[7]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[7]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[7]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[8]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[8]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[8]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg1_reg[9]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg1_reg[9]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg1_reg[9]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[10]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[10]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[10]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[11]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[11]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[11]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[12]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[12]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[12]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[13]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[13]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[13]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[14]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[14]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[14]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[15]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[15]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[15]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[16]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[16]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[16]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[17]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[17]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[17]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[6]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[6]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[6]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[7]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[7]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[7]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[8]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[8]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[8]\ : label is "NO";
  attribute ASYNC_REG_boolean of \rxeq_user_txcoeff_reg2_reg[9]\ : label is std.standard.true;
  attribute KEEP of \rxeq_user_txcoeff_reg2_reg[9]\ : label is "yes";
  attribute SHIFT_EXTRACT of \rxeq_user_txcoeff_reg2_reg[9]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_control_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_control_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_control_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_control_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_control_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_control_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_control_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_control_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_control_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg1_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg1_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg1_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[4]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[4]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[4]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_deemph_reg2_reg[5]\ : label is std.standard.true;
  attribute KEEP of \txeq_deemph_reg2_reg[5]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_deemph_reg2_reg[5]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_preset_reg1_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg1_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg1_reg[3]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[0]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[0]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[0]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[1]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[1]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[1]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[2]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[2]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[2]\ : label is "NO";
  attribute ASYNC_REG_boolean of \txeq_preset_reg2_reg[3]\ : label is std.standard.true;
  attribute KEEP of \txeq_preset_reg2_reg[3]\ : label is "yes";
  attribute SHIFT_EXTRACT of \txeq_preset_reg2_reg[3]\ : label is "NO";
  attribute SOFT_HLUTNM of \txeq_txcoeff[18]_i_3__0\ : label is "soft_lutpair60";
  attribute SOFT_HLUTNM of \txeq_txcoeff[5]_i_3__0\ : label is "soft_lutpair58";
  attribute SOFT_HLUTNM of \txeq_txcoeff_cnt[1]_i_1__0\ : label is "soft_lutpair60";
begin
  rxeq_adapt_done_reg_0 <= \^rxeq_adapt_done_reg_0\;
\FSM_onehot_fsm_rx[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"ABABABAA"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx[1]_i_2__0_n_0\,
      I1 => rxeq_control_reg2(0),
      I2 => rxeq_control_reg2(1),
      I3 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I4 => \FSM_onehot_fsm_rx_reg_n_0_[6]\,
      O => \FSM_onehot_fsm_rx[1]_i_1__0_n_0\
    );
\FSM_onehot_fsm_rx[1]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000000000001"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[6]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[5]\,
      I3 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I5 => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      O => \FSM_onehot_fsm_rx[1]_i_2__0_n_0\
    );
\FSM_onehot_fsm_rx[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFF8FF88888888"
    )
        port map (
      I0 => rxeq_control_reg2(1),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I2 => \rxeq_cnt_reg_n_0_[2]\,
      I3 => \rxeq_cnt_reg_n_0_[1]\,
      I4 => \rxeq_cnt_reg_n_0_[0]\,
      I5 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      O => \FSM_onehot_fsm_rx[3]_i_1__0_n_0\
    );
\FSM_onehot_fsm_rx[4]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"2ABA2AAA"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I1 => \rxeq_cnt_reg_n_0_[2]\,
      I2 => \rxeq_cnt_reg_n_0_[1]\,
      I3 => \rxeq_cnt_reg_n_0_[0]\,
      I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      O => \FSM_onehot_fsm_rx[4]_i_1__0_n_0\
    );
\FSM_onehot_fsm_rx_reg[1]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \FSM_onehot_fsm_rx[1]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      S => \out\
    );
\FSM_onehot_fsm_rx_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_scan_i_n_4,
      Q => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      R => \out\
    );
\FSM_onehot_fsm_rx_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \FSM_onehot_fsm_rx[3]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      R => \out\
    );
\FSM_onehot_fsm_rx_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \FSM_onehot_fsm_rx[4]_i_1__0_n_0\,
      Q => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      R => \out\
    );
\FSM_onehot_fsm_rx_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_scan_i_n_3,
      Q => \FSM_onehot_fsm_rx_reg_n_0_[5]\,
      R => \out\
    );
\FSM_onehot_fsm_rx_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_scan_i_n_2,
      Q => \FSM_onehot_fsm_rx_reg_n_0_[6]\,
      R => \out\
    );
\FSM_sequential_fsm_tx[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"CCCF44440000FF3F"
    )
        port map (
      I0 => \FSM_sequential_fsm_tx[1]_i_2__0_n_0\,
      I1 => fsm_tx(0),
      I2 => txeq_control_reg2(0),
      I3 => txeq_control_reg2(1),
      I4 => fsm_tx(2),
      I5 => fsm_tx(1),
      O => \fsm_tx__0\(0)
    );
\FSM_sequential_fsm_tx[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"3F703F7C3F7C0F70"
    )
        port map (
      I0 => \FSM_sequential_fsm_tx[1]_i_2__0_n_0\,
      I1 => fsm_tx(0),
      I2 => fsm_tx(1),
      I3 => fsm_tx(2),
      I4 => txeq_control_reg2(1),
      I5 => txeq_control_reg2(0),
      O => \fsm_tx__0\(1)
    );
\FSM_sequential_fsm_tx[1]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      O => \FSM_sequential_fsm_tx[1]_i_2__0_n_0\
    );
\FSM_sequential_fsm_tx[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"00A8EAAA55FDFFFF"
    )
        port map (
      I0 => fsm_tx(2),
      I1 => txeq_control_reg2(1),
      I2 => txeq_control_reg2(0),
      I3 => fsm_tx(0),
      I4 => fsm_tx(1),
      I5 => \FSM_sequential_fsm_tx[2]_i_2__0_n_0\,
      O => \fsm_tx__0\(2)
    );
\FSM_sequential_fsm_tx[2]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"D0FFDFFF"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => fsm_tx(0),
      I3 => fsm_tx(1),
      I4 => txeq_preset_done,
      O => \FSM_sequential_fsm_tx[2]_i_2__0_n_0\
    );
\FSM_sequential_fsm_tx_reg[0]\: unisim.vcomponents.FDSE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \fsm_tx__0\(0),
      Q => fsm_tx(0),
      S => \out\
    );
\FSM_sequential_fsm_tx_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \fsm_tx__0\(1),
      Q => fsm_tx(1),
      R => \out\
    );
\FSM_sequential_fsm_tx_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \fsm_tx__0\(2),
      Q => fsm_tx(2),
      R => \out\
    );
gen3_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rate_gen3_1,
      Q => gen3_reg1,
      R => \out\
    );
gen3_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => gen3_reg1,
      Q => gen3_reg2,
      R => \out\
    );
\gtx_channel.gtxe2_channel_i_i_23__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[17]\,
      O => TXPOSTCURSOR(4)
    );
\gtx_channel.gtxe2_channel_i_i_24__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[16]\,
      O => TXPOSTCURSOR(3)
    );
\gtx_channel.gtxe2_channel_i_i_25__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[15]\,
      O => TXPOSTCURSOR(2)
    );
\gtx_channel.gtxe2_channel_i_i_26__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[14]\,
      O => TXPOSTCURSOR(1)
    );
\gtx_channel.gtxe2_channel_i_i_27__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[13]\,
      O => TXPOSTCURSOR(0)
    );
\gtx_channel.gtxe2_channel_i_i_28__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[4]\,
      O => TXPRECURSOR(4)
    );
\gtx_channel.gtxe2_channel_i_i_29__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[3]\,
      O => TXPRECURSOR(3)
    );
\gtx_channel.gtxe2_channel_i_i_30__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[2]\,
      O => TXPRECURSOR(2)
    );
\gtx_channel.gtxe2_channel_i_i_31__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[1]\,
      O => TXPRECURSOR(1)
    );
\gtx_channel.gtxe2_channel_i_i_32__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[0]\,
      I1 => gen3_reg2,
      O => TXPRECURSOR(0)
    );
\gtx_channel.gtxe2_channel_i_i_33__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[12]\,
      O => TXMAINCURSOR(6)
    );
\gtx_channel.gtxe2_channel_i_i_34__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[11]\,
      O => TXMAINCURSOR(5)
    );
\gtx_channel.gtxe2_channel_i_i_35__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[10]\,
      O => TXMAINCURSOR(4)
    );
\gtx_channel.gtxe2_channel_i_i_36__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[9]\,
      O => TXMAINCURSOR(3)
    );
\gtx_channel.gtxe2_channel_i_i_37__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[8]\,
      O => TXMAINCURSOR(2)
    );
\gtx_channel.gtxe2_channel_i_i_38__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[7]\,
      O => TXMAINCURSOR(1)
    );
\gtx_channel.gtxe2_channel_i_i_39\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => gen3_reg2,
      I1 => \txeq_txcoeff_reg_n_0_[6]\,
      O => TXMAINCURSOR(0)
    );
\rxeq_adapt_done_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFEFFFFFFFF"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[5]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      I3 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I5 => \FSM_onehot_fsm_rx_reg_n_0_[6]\,
      O => \rxeq_adapt_done_i_2__0_n_0\
    );
rxeq_adapt_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_scan_i_n_1,
      Q => \^rxeq_adapt_done_reg_0\,
      R => \out\
    );
\rxeq_adapt_done_reg_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => rxeq_control_reg2(0),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I2 => rxeq_control_reg2(1),
      O => \rxeq_adapt_done_reg_i_2__0_n_0\
    );
rxeq_adapt_done_reg_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_scan_i_n_0,
      Q => rxeq_adapt_done_reg_reg_n_0,
      R => \out\
    );
\rxeq_cnt[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"8888FFF8"
    )
        port map (
      I0 => rxeq_control_reg2(1),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I3 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I4 => \rxeq_cnt_reg_n_0_[0]\,
      O => rxeq_cnt(0)
    );
\rxeq_cnt[1]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"6660"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[1]\,
      I1 => \rxeq_cnt_reg_n_0_[0]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I3 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      O => rxeq_cnt(1)
    );
\rxeq_cnt[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"78787800"
    )
        port map (
      I0 => \rxeq_cnt_reg_n_0_[0]\,
      I1 => \rxeq_cnt_reg_n_0_[1]\,
      I2 => \rxeq_cnt_reg_n_0_[2]\,
      I3 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      O => rxeq_cnt(2)
    );
\rxeq_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_cnt(0),
      Q => \rxeq_cnt_reg_n_0_[0]\,
      R => \out\
    );
\rxeq_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_cnt(1),
      Q => \rxeq_cnt_reg_n_0_[1]\,
      R => \out\
    );
\rxeq_cnt_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_cnt(2),
      Q => \rxeq_cnt_reg_n_0_[2]\,
      R => \out\
    );
\rxeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_control_reg1(0),
      R => \out\
    );
\rxeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_control_reg1(1),
      R => \out\
    );
\rxeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_control_reg1(0),
      Q => rxeq_control_reg2(0),
      R => \out\
    );
\rxeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_control_reg1(1),
      Q => rxeq_control_reg2(1),
      R => \out\
    );
\rxeq_fs[0]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_lffs_reg2(0),
      O => rxeq_fs(0)
    );
\rxeq_fs[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_lffs_reg2(1),
      O => rxeq_fs(1)
    );
\rxeq_fs[2]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_lffs_reg2(2),
      O => rxeq_fs(2)
    );
\rxeq_fs[3]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_lffs_reg2(3),
      O => rxeq_fs(3)
    );
\rxeq_fs[4]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_lffs_reg2(4),
      O => rxeq_fs(4)
    );
\rxeq_fs[5]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"F8"
    )
        port map (
      I0 => rxeq_control_reg2(1),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I2 => \FSM_onehot_fsm_rx[1]_i_2__0_n_0\,
      O => \rxeq_fs[5]_i_1__0_n_0\
    );
\rxeq_fs[5]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => rxeq_lffs_reg2(5),
      O => rxeq_fs(5)
    );
\rxeq_fs_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_fs[5]_i_1__0_n_0\,
      D => rxeq_fs(0),
      Q => \rxeq_fs_reg_n_0_[0]\,
      R => \out\
    );
\rxeq_fs_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_fs[5]_i_1__0_n_0\,
      D => rxeq_fs(1),
      Q => \rxeq_fs_reg_n_0_[1]\,
      R => \out\
    );
\rxeq_fs_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_fs[5]_i_1__0_n_0\,
      D => rxeq_fs(2),
      Q => \rxeq_fs_reg_n_0_[2]\,
      R => \out\
    );
\rxeq_fs_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_fs[5]_i_1__0_n_0\,
      D => rxeq_fs(3),
      Q => \rxeq_fs_reg_n_0_[3]\,
      R => \out\
    );
\rxeq_fs_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_fs[5]_i_1__0_n_0\,
      D => rxeq_fs(4),
      Q => \rxeq_fs_reg_n_0_[4]\,
      R => \out\
    );
\rxeq_fs_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_fs[5]_i_1__0_n_0\,
      D => rxeq_fs(5),
      Q => \rxeq_fs_reg_n_0_[5]\,
      R => \out\
    );
\rxeq_lf[0]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I1 => rxeq_lffs_reg2(0),
      O => rxeq_lf(0)
    );
\rxeq_lf[1]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I1 => rxeq_lffs_reg2(1),
      O => rxeq_lf(1)
    );
\rxeq_lf[2]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I1 => rxeq_lffs_reg2(2),
      O => rxeq_lf(2)
    );
\rxeq_lf[3]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I1 => rxeq_lffs_reg2(3),
      O => rxeq_lf(3)
    );
\rxeq_lf[4]_i_1__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I1 => rxeq_lffs_reg2(4),
      O => rxeq_lf(4)
    );
\rxeq_lf[5]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"EAAAAAAA"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx[1]_i_2__0_n_0\,
      I1 => \rxeq_cnt_reg_n_0_[1]\,
      I2 => \rxeq_cnt_reg_n_0_[0]\,
      I3 => \rxeq_cnt_reg_n_0_[2]\,
      I4 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      O => \rxeq_lf[5]_i_1__0_n_0\
    );
\rxeq_lf[5]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I1 => rxeq_lffs_reg2(5),
      O => rxeq_lf(5)
    );
\rxeq_lf_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_lf[5]_i_1__0_n_0\,
      D => rxeq_lf(0),
      Q => \rxeq_lf_reg_n_0_[0]\,
      R => \out\
    );
\rxeq_lf_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_lf[5]_i_1__0_n_0\,
      D => rxeq_lf(1),
      Q => \rxeq_lf_reg_n_0_[1]\,
      R => \out\
    );
\rxeq_lf_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_lf[5]_i_1__0_n_0\,
      D => rxeq_lf(2),
      Q => \rxeq_lf_reg_n_0_[2]\,
      R => \out\
    );
\rxeq_lf_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_lf[5]_i_1__0_n_0\,
      D => rxeq_lf(3),
      Q => \rxeq_lf_reg_n_0_[3]\,
      R => \out\
    );
\rxeq_lf_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_lf[5]_i_1__0_n_0\,
      D => rxeq_lf(4),
      Q => \rxeq_lf_reg_n_0_[4]\,
      R => \out\
    );
\rxeq_lf_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_lf[5]_i_1__0_n_0\,
      D => rxeq_lf(5),
      Q => \rxeq_lf_reg_n_0_[5]\,
      R => \out\
    );
\rxeq_lffs_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(0),
      R => \out\
    );
\rxeq_lffs_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(1),
      R => \out\
    );
\rxeq_lffs_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(2),
      R => \out\
    );
\rxeq_lffs_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(3),
      R => \out\
    );
\rxeq_lffs_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(4),
      R => \out\
    );
\rxeq_lffs_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_lffs_reg1(5),
      R => \out\
    );
\rxeq_lffs_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_lffs_reg1(0),
      Q => rxeq_lffs_reg2(0),
      R => \out\
    );
\rxeq_lffs_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_lffs_reg1(1),
      Q => rxeq_lffs_reg2(1),
      R => \out\
    );
\rxeq_lffs_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_lffs_reg1(2),
      Q => rxeq_lffs_reg2(2),
      R => \out\
    );
\rxeq_lffs_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_lffs_reg1(3),
      Q => rxeq_lffs_reg2(3),
      R => \out\
    );
\rxeq_lffs_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_lffs_reg1(4),
      Q => rxeq_lffs_reg2(4),
      R => \out\
    );
\rxeq_lffs_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_lffs_reg1(5),
      Q => rxeq_lffs_reg2(5),
      R => \out\
    );
rxeq_new_txcoeff_req_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_new_txcoeff_req,
      Q => rxeq_new_txcoeff_req_reg_n_0,
      R => \out\
    );
\rxeq_preset[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8FFA800"
    )
        port map (
      I0 => rxeq_preset_reg2(0),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I3 => \rxeq_preset[2]_i_2__0_n_0\,
      I4 => \rxeq_preset_reg_n_0_[0]\,
      O => \rxeq_preset[0]_i_1__0_n_0\
    );
\rxeq_preset[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8FFA800"
    )
        port map (
      I0 => rxeq_preset_reg2(1),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I3 => \rxeq_preset[2]_i_2__0_n_0\,
      I4 => \rxeq_preset_reg_n_0_[1]\,
      O => \rxeq_preset[1]_i_1__0_n_0\
    );
\rxeq_preset[2]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"A8FFA800"
    )
        port map (
      I0 => rxeq_preset_reg2(2),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I3 => \rxeq_preset[2]_i_2__0_n_0\,
      I4 => \rxeq_preset_reg_n_0_[2]\,
      O => \rxeq_preset[2]_i_1__0_n_0\
    );
\rxeq_preset[2]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FFFFFFFFFFFF0100"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[6]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[5]\,
      I3 => \rxeq_preset[2]_i_3__0_n_0\,
      I4 => \rxeq_adapt_done_reg_i_2__0_n_0\,
      I5 => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      O => \rxeq_preset[2]_i_2__0_n_0\
    );
\rxeq_preset[2]_i_3__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      O => \rxeq_preset[2]_i_3__0_n_0\
    );
\rxeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(0),
      R => \out\
    );
\rxeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(1),
      R => \out\
    );
\rxeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_preset_reg1(2),
      R => \out\
    );
\rxeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_preset_reg1(0),
      Q => rxeq_preset_reg2(0),
      R => \out\
    );
\rxeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_preset_reg1(1),
      Q => rxeq_preset_reg2(1),
      R => \out\
    );
\rxeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_preset_reg1(2),
      Q => rxeq_preset_reg2(2),
      R => \out\
    );
\rxeq_preset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \rxeq_preset[0]_i_1__0_n_0\,
      Q => \rxeq_preset_reg_n_0_[0]\,
      R => \out\
    );
\rxeq_preset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \rxeq_preset[1]_i_1__0_n_0\,
      Q => \rxeq_preset_reg_n_0_[1]\,
      R => \out\
    );
\rxeq_preset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \rxeq_preset[2]_i_1__0_n_0\,
      Q => \rxeq_preset_reg_n_0_[2]\,
      R => \out\
    );
rxeq_preset_valid_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      Q => rxeq_preset_valid,
      R => \out\
    );
rxeq_scan_i: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_rxeq_scan
     port map (
      D(2) => rxeq_scan_i_n_2,
      D(1) => rxeq_scan_i_n_3,
      D(0) => rxeq_scan_i_n_4,
      \FSM_onehot_fsm_rx_reg[5]\(2) => \rxeq_cnt_reg_n_0_[2]\,
      \FSM_onehot_fsm_rx_reg[5]\(1) => \rxeq_cnt_reg_n_0_[1]\,
      \FSM_onehot_fsm_rx_reg[5]\(0) => \rxeq_cnt_reg_n_0_[0]\,
      Q(4) => \FSM_onehot_fsm_rx_reg_n_0_[6]\,
      Q(3) => \FSM_onehot_fsm_rx_reg_n_0_[5]\,
      Q(2) => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      Q(1) => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      Q(0) => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      adapt_done_cnt_reg_0(1 downto 0) => rxeq_control_reg2(1 downto 0),
      adapt_done_reg_0 => rxeq_scan_i_n_0,
      \fs_reg1_reg[5]_0\(5) => \rxeq_fs_reg_n_0_[5]\,
      \fs_reg1_reg[5]_0\(4) => \rxeq_fs_reg_n_0_[4]\,
      \fs_reg1_reg[5]_0\(3) => \rxeq_fs_reg_n_0_[3]\,
      \fs_reg1_reg[5]_0\(2) => \rxeq_fs_reg_n_0_[2]\,
      \fs_reg1_reg[5]_0\(1) => \rxeq_fs_reg_n_0_[1]\,
      \fs_reg1_reg[5]_0\(0) => \rxeq_fs_reg_n_0_[0]\,
      \fs_reg2_reg[5]_0\ => \fs_reg2_reg[5]\,
      \lf_reg1_reg[5]_0\(5) => \rxeq_lf_reg_n_0_[5]\,
      \lf_reg1_reg[5]_0\(4) => \rxeq_lf_reg_n_0_[4]\,
      \lf_reg1_reg[5]_0\(3) => \rxeq_lf_reg_n_0_[3]\,
      \lf_reg1_reg[5]_0\(2) => \rxeq_lf_reg_n_0_[2]\,
      \lf_reg1_reg[5]_0\(1) => \rxeq_lf_reg_n_0_[1]\,
      \lf_reg1_reg[5]_0\(0) => \rxeq_lf_reg_n_0_[0]\,
      new_txcoeff_done_reg_0 => rxeq_scan_i_n_1,
      new_txcoeff_req_reg1_reg_0 => rxeq_new_txcoeff_req_reg_n_0,
      \out\ => \out\,
      \preset_reg1_reg[2]_0\(2) => \rxeq_preset_reg_n_0_[2]\,
      \preset_reg1_reg[2]_0\(1) => \rxeq_preset_reg_n_0_[1]\,
      \preset_reg1_reg[2]_0\(0) => \rxeq_preset_reg_n_0_[0]\,
      rxeq_adapt_done_reg => \rxeq_adapt_done_i_2__0_n_0\,
      rxeq_adapt_done_reg_0 => \^rxeq_adapt_done_reg_0\,
      rxeq_adapt_done_reg_reg => \FSM_onehot_fsm_rx[1]_i_2__0_n_0\,
      rxeq_adapt_done_reg_reg_0 => \rxeq_adapt_done_reg_i_2__0_n_0\,
      rxeq_adapt_done_reg_reg_1 => rxeq_adapt_done_reg_reg_n_0,
      rxeq_new_txcoeff_req => rxeq_new_txcoeff_req,
      rxeq_preset_valid => rxeq_preset_valid,
      \txcoeff_reg1_reg[17]_0\(17) => \rxeq_txcoeff_reg_n_0_[17]\,
      \txcoeff_reg1_reg[17]_0\(16) => \rxeq_txcoeff_reg_n_0_[16]\,
      \txcoeff_reg1_reg[17]_0\(15) => \rxeq_txcoeff_reg_n_0_[15]\,
      \txcoeff_reg1_reg[17]_0\(14) => \rxeq_txcoeff_reg_n_0_[14]\,
      \txcoeff_reg1_reg[17]_0\(13) => \rxeq_txcoeff_reg_n_0_[13]\,
      \txcoeff_reg1_reg[17]_0\(12) => \rxeq_txcoeff_reg_n_0_[12]\,
      \txcoeff_reg1_reg[17]_0\(11) => \rxeq_txcoeff_reg_n_0_[11]\,
      \txcoeff_reg1_reg[17]_0\(10) => \rxeq_txcoeff_reg_n_0_[10]\,
      \txcoeff_reg1_reg[17]_0\(9) => \rxeq_txcoeff_reg_n_0_[9]\,
      \txcoeff_reg1_reg[17]_0\(8) => \rxeq_txcoeff_reg_n_0_[8]\,
      \txcoeff_reg1_reg[17]_0\(7) => \rxeq_txcoeff_reg_n_0_[7]\,
      \txcoeff_reg1_reg[17]_0\(6) => \rxeq_txcoeff_reg_n_0_[6]\,
      \txcoeff_reg1_reg[17]_0\(5) => \rxeq_txcoeff_reg_n_0_[5]\,
      \txcoeff_reg1_reg[17]_0\(4) => \rxeq_txcoeff_reg_n_0_[4]\,
      \txcoeff_reg1_reg[17]_0\(3) => \rxeq_txcoeff_reg_n_0_[3]\,
      \txcoeff_reg1_reg[17]_0\(2) => \rxeq_txcoeff_reg_n_0_[2]\,
      \txcoeff_reg1_reg[17]_0\(1) => \rxeq_txcoeff_reg_n_0_[1]\,
      \txcoeff_reg1_reg[17]_0\(0) => \rxeq_txcoeff_reg_n_0_[0]\,
      \txpreset_reg1_reg[3]_0\(3) => \rxeq_txpreset_reg_n_0_[3]\,
      \txpreset_reg1_reg[3]_0\(2) => \rxeq_txpreset_reg_n_0_[2]\,
      \txpreset_reg1_reg[3]_0\(1) => \rxeq_txpreset_reg_n_0_[1]\,
      \txpreset_reg1_reg[3]_0\(0) => \rxeq_txpreset_reg_n_0_[0]\
    );
\rxeq_txcoeff[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \rxeq_txcoeff_reg_n_0_[6]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(0)
    );
\rxeq_txcoeff[10]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \rxeq_txcoeff_reg_n_0_[16]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(10)
    );
\rxeq_txcoeff[11]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \rxeq_txcoeff_reg_n_0_[17]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(11)
    );
\rxeq_txcoeff[12]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => txeq_deemph_reg2(0),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(12)
    );
\rxeq_txcoeff[13]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => txeq_deemph_reg2(1),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(13)
    );
\rxeq_txcoeff[14]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => txeq_deemph_reg2(2),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(14)
    );
\rxeq_txcoeff[15]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => txeq_deemph_reg2(3),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(15)
    );
\rxeq_txcoeff[16]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => txeq_deemph_reg2(4),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(16)
    );
\rxeq_txcoeff[17]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => txeq_deemph_reg2(5),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(17)
    );
\rxeq_txcoeff[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \rxeq_txcoeff_reg_n_0_[7]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(1)
    );
\rxeq_txcoeff[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \rxeq_txcoeff_reg_n_0_[8]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(2)
    );
\rxeq_txcoeff[3]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \rxeq_txcoeff_reg_n_0_[9]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(3)
    );
\rxeq_txcoeff[4]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \rxeq_txcoeff_reg_n_0_[10]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(4)
    );
\rxeq_txcoeff[5]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \rxeq_txcoeff_reg_n_0_[11]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(5)
    );
\rxeq_txcoeff[6]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \rxeq_txcoeff_reg_n_0_[12]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(6)
    );
\rxeq_txcoeff[7]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \rxeq_txcoeff_reg_n_0_[13]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(7)
    );
\rxeq_txcoeff[8]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \rxeq_txcoeff_reg_n_0_[14]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(8)
    );
\rxeq_txcoeff[9]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => \rxeq_txcoeff_reg_n_0_[15]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txcoeff(9)
    );
\rxeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(0),
      Q => \rxeq_txcoeff_reg_n_0_[0]\,
      R => \out\
    );
\rxeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(10),
      Q => \rxeq_txcoeff_reg_n_0_[10]\,
      R => \out\
    );
\rxeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(11),
      Q => \rxeq_txcoeff_reg_n_0_[11]\,
      R => \out\
    );
\rxeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(12),
      Q => \rxeq_txcoeff_reg_n_0_[12]\,
      R => \out\
    );
\rxeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(13),
      Q => \rxeq_txcoeff_reg_n_0_[13]\,
      R => \out\
    );
\rxeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(14),
      Q => \rxeq_txcoeff_reg_n_0_[14]\,
      R => \out\
    );
\rxeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(15),
      Q => \rxeq_txcoeff_reg_n_0_[15]\,
      R => \out\
    );
\rxeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(16),
      Q => \rxeq_txcoeff_reg_n_0_[16]\,
      R => \out\
    );
\rxeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(17),
      Q => \rxeq_txcoeff_reg_n_0_[17]\,
      R => \out\
    );
\rxeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(1),
      Q => \rxeq_txcoeff_reg_n_0_[1]\,
      R => \out\
    );
\rxeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(2),
      Q => \rxeq_txcoeff_reg_n_0_[2]\,
      R => \out\
    );
\rxeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(3),
      Q => \rxeq_txcoeff_reg_n_0_[3]\,
      R => \out\
    );
\rxeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(4),
      Q => \rxeq_txcoeff_reg_n_0_[4]\,
      R => \out\
    );
\rxeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(5),
      Q => \rxeq_txcoeff_reg_n_0_[5]\,
      R => \out\
    );
\rxeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(6),
      Q => \rxeq_txcoeff_reg_n_0_[6]\,
      R => \out\
    );
\rxeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(7),
      Q => \rxeq_txcoeff_reg_n_0_[7]\,
      R => \out\
    );
\rxeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(8),
      Q => \rxeq_txcoeff_reg_n_0_[8]\,
      R => \out\
    );
\rxeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txcoeff(9),
      Q => \rxeq_txcoeff_reg_n_0_[9]\,
      R => \out\
    );
\rxeq_txpreset[0]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => rxeq_txpreset_reg2(0),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txpreset(0)
    );
\rxeq_txpreset[1]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => rxeq_txpreset_reg2(1),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txpreset(1)
    );
\rxeq_txpreset[2]_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => rxeq_txpreset_reg2(2),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txpreset(2)
    );
\rxeq_txpreset[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFFF404"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[6]\,
      I1 => \rxeq_txpreset[3]_i_3__0_n_0\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      I3 => rxeq_control_reg2(1),
      I4 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      O => \rxeq_txpreset[3]_i_1__0_n_0\
    );
\rxeq_txpreset[3]_i_2__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"A8"
    )
        port map (
      I0 => rxeq_txpreset_reg2(3),
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[3]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[1]\,
      O => rxeq_txpreset(3)
    );
\rxeq_txpreset[3]_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"01"
    )
        port map (
      I0 => \FSM_onehot_fsm_rx_reg_n_0_[2]\,
      I1 => \FSM_onehot_fsm_rx_reg_n_0_[4]\,
      I2 => \FSM_onehot_fsm_rx_reg_n_0_[5]\,
      O => \rxeq_txpreset[3]_i_3__0_n_0\
    );
\rxeq_txpreset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(0),
      R => \out\
    );
\rxeq_txpreset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(1),
      R => \out\
    );
\rxeq_txpreset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(2),
      R => \out\
    );
\rxeq_txpreset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_txpreset_reg1(3),
      R => \out\
    );
\rxeq_txpreset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_txpreset_reg1(0),
      Q => rxeq_txpreset_reg2(0),
      R => \out\
    );
\rxeq_txpreset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_txpreset_reg1(1),
      Q => rxeq_txpreset_reg2(1),
      R => \out\
    );
\rxeq_txpreset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_txpreset_reg1(2),
      Q => rxeq_txpreset_reg2(2),
      R => \out\
    );
\rxeq_txpreset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_txpreset_reg1(3),
      Q => rxeq_txpreset_reg2(3),
      R => \out\
    );
\rxeq_txpreset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txpreset(0),
      Q => \rxeq_txpreset_reg_n_0_[0]\,
      R => \out\
    );
\rxeq_txpreset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txpreset(1),
      Q => \rxeq_txpreset_reg_n_0_[1]\,
      R => \out\
    );
\rxeq_txpreset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txpreset(2),
      Q => \rxeq_txpreset_reg_n_0_[2]\,
      R => \out\
    );
\rxeq_txpreset_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \rxeq_txpreset[3]_i_1__0_n_0\,
      D => rxeq_txpreset(3),
      Q => \rxeq_txpreset_reg_n_0_[3]\,
      R => \out\
    );
rxeq_user_en_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_en_reg1,
      R => \out\
    );
rxeq_user_en_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_en_reg1,
      Q => rxeq_user_en_reg2,
      R => \out\
    );
rxeq_user_mode_reg1_reg: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_mode_reg1,
      R => \out\
    );
rxeq_user_mode_reg2_reg: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_mode_reg1,
      Q => rxeq_user_mode_reg2,
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(0),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(10),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(11),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(12),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(13),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(14),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(15),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(16),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(17),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(1),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(2),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(3),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(4),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(5),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(6),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(7),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(8),
      R => \out\
    );
\rxeq_user_txcoeff_reg1_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => rxeq_user_txcoeff_reg1(9),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(0),
      Q => rxeq_user_txcoeff_reg2(0),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[10]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(10),
      Q => rxeq_user_txcoeff_reg2(10),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[11]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(11),
      Q => rxeq_user_txcoeff_reg2(11),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[12]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(12),
      Q => rxeq_user_txcoeff_reg2(12),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[13]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(13),
      Q => rxeq_user_txcoeff_reg2(13),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[14]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(14),
      Q => rxeq_user_txcoeff_reg2(14),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[15]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(15),
      Q => rxeq_user_txcoeff_reg2(15),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[16]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(16),
      Q => rxeq_user_txcoeff_reg2(16),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[17]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(17),
      Q => rxeq_user_txcoeff_reg2(17),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(1),
      Q => rxeq_user_txcoeff_reg2(1),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(2),
      Q => rxeq_user_txcoeff_reg2(2),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(3),
      Q => rxeq_user_txcoeff_reg2(3),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(4),
      Q => rxeq_user_txcoeff_reg2(4),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(5),
      Q => rxeq_user_txcoeff_reg2(5),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(6),
      Q => rxeq_user_txcoeff_reg2(6),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(7),
      Q => rxeq_user_txcoeff_reg2(7),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[8]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(8),
      Q => rxeq_user_txcoeff_reg2(8),
      R => \out\
    );
\rxeq_user_txcoeff_reg2_reg[9]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => rxeq_user_txcoeff_reg1(9),
      Q => rxeq_user_txcoeff_reg2(9),
      R => \out\
    );
\txeq_control_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_control_reg1(0),
      R => \out\
    );
\txeq_control_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_control_reg1(1),
      R => \out\
    );
\txeq_control_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_control_reg1(0),
      Q => txeq_control_reg2(0),
      R => \out\
    );
\txeq_control_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_control_reg1(1),
      Q => txeq_control_reg2(1),
      R => \out\
    );
\txeq_deemph_reg1_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(0),
      S => \out\
    );
\txeq_deemph_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(1),
      R => \out\
    );
\txeq_deemph_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(2),
      R => \out\
    );
\txeq_deemph_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(3),
      R => \out\
    );
\txeq_deemph_reg1_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(4),
      R => \out\
    );
\txeq_deemph_reg1_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_deemph_reg1(5),
      R => \out\
    );
\txeq_deemph_reg2_reg[0]\: unisim.vcomponents.FDSE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_deemph_reg1(0),
      Q => txeq_deemph_reg2(0),
      S => \out\
    );
\txeq_deemph_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_deemph_reg1(1),
      Q => txeq_deemph_reg2(1),
      R => \out\
    );
\txeq_deemph_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_deemph_reg1(2),
      Q => txeq_deemph_reg2(2),
      R => \out\
    );
\txeq_deemph_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_deemph_reg1(3),
      Q => txeq_deemph_reg2(3),
      R => \out\
    );
\txeq_deemph_reg2_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_deemph_reg1(4),
      Q => txeq_deemph_reg2(4),
      R => \out\
    );
\txeq_deemph_reg2_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_deemph_reg1(5),
      Q => txeq_deemph_reg2(5),
      R => \out\
    );
\txeq_preset[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00040000"
    )
        port map (
      I0 => txeq_preset_reg2(1),
      I1 => txeq_preset_reg2(3),
      I2 => \out\,
      I3 => txeq_preset_reg2(2),
      I4 => txeq_preset_reg2(0),
      O => p_0_out(0)
    );
\txeq_preset[10]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AAEABBAF"
    )
        port map (
      I0 => \out\,
      I1 => txeq_preset_reg2(2),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(0),
      O => p_0_out(10)
    );
\txeq_preset[11]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF1811"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(1),
      I4 => \out\,
      O => p_0_out(11)
    );
\txeq_preset[12]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01111310"
    )
        port map (
      I0 => txeq_preset_reg2(3),
      I1 => \out\,
      I2 => txeq_preset_reg2(2),
      I3 => txeq_preset_reg2(0),
      I4 => txeq_preset_reg2(1),
      O => p_0_out(12)
    );
\txeq_preset[13]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"01000010"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => \out\,
      I2 => txeq_preset_reg2(0),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(1),
      O => p_0_out(13)
    );
\txeq_preset[14]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00100100"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => \out\,
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(0),
      O => p_0_out(14)
    );
\txeq_preset[15]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"F0F1"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(1),
      I2 => \out\,
      I3 => txeq_preset_reg2(3),
      O => p_0_out(15)
    );
\txeq_preset[16]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"0006"
    )
        port map (
      I0 => txeq_preset_reg2(3),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(2),
      I3 => \out\,
      O => p_0_out(16)
    );
\txeq_preset[17]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AABA"
    )
        port map (
      I0 => \out\,
      I1 => fsm_tx(0),
      I2 => fsm_tx(1),
      I3 => fsm_tx(2),
      O => \txeq_preset[17]_i_1__0_n_0\
    );
\txeq_preset[17]_i_2__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFF1091"
    )
        port map (
      I0 => txeq_preset_reg2(2),
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(3),
      I4 => \out\,
      O => p_0_out(17)
    );
\txeq_preset[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00001004"
    )
        port map (
      I0 => \out\,
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(1),
      I3 => txeq_preset_reg2(2),
      I4 => txeq_preset_reg2(0),
      O => p_0_out(1)
    );
\txeq_preset[2]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"4440"
    )
        port map (
      I0 => \out\,
      I1 => txeq_preset_reg2(3),
      I2 => txeq_preset_reg2(2),
      I3 => txeq_preset_reg2(0),
      O => p_0_out(2)
    );
\txeq_preset[3]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00441140"
    )
        port map (
      I0 => \out\,
      I1 => txeq_preset_reg2(2),
      I2 => txeq_preset_reg2(0),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(1),
      O => \txeq_preset[3]_i_1__0_n_0\
    );
\txeq_preset[7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000AAAA3C00AAAA"
    )
        port map (
      I0 => \txeq_preset_reg_n_0_[7]\,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(2),
      I3 => \txeq_preset[7]_i_2__0_n_0\,
      I4 => \txeq_preset[17]_i_1__0_n_0\,
      I5 => \out\,
      O => \txeq_preset[7]_i_1__0_n_0\
    );
\txeq_preset[7]_i_2__0\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"2"
    )
        port map (
      I0 => txeq_preset_reg2(1),
      I1 => txeq_preset_reg2(3),
      O => \txeq_preset[7]_i_2__0_n_0\
    );
\txeq_preset[8]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"AABEAFAF"
    )
        port map (
      I0 => \out\,
      I1 => txeq_preset_reg2(0),
      I2 => txeq_preset_reg2(2),
      I3 => txeq_preset_reg2(3),
      I4 => txeq_preset_reg2(1),
      O => p_0_out(8)
    );
\txeq_preset[9]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"CFCCCCFD"
    )
        port map (
      I0 => txeq_preset_reg2(1),
      I1 => \out\,
      I2 => txeq_preset_reg2(3),
      I3 => txeq_preset_reg2(0),
      I4 => txeq_preset_reg2(2),
      O => p_0_out(9)
    );
\txeq_preset_done_i_1__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"04"
    )
        port map (
      I0 => fsm_tx(2),
      I1 => fsm_tx(1),
      I2 => fsm_tx(0),
      O => \txeq_preset_done_i_1__0_n_0\
    );
txeq_preset_done_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \txeq_preset_done_i_1__0_n_0\,
      Q => txeq_preset_done,
      R => \out\
    );
\txeq_preset_reg1_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(0),
      R => \out\
    );
\txeq_preset_reg1_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(1),
      R => \out\
    );
\txeq_preset_reg1_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(2),
      R => \out\
    );
\txeq_preset_reg1_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => '0',
      Q => txeq_preset_reg1(3),
      R => \out\
    );
\txeq_preset_reg2_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_preset_reg1(0),
      Q => txeq_preset_reg2(0),
      R => \out\
    );
\txeq_preset_reg2_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_preset_reg1(1),
      Q => txeq_preset_reg2(1),
      R => \out\
    );
\txeq_preset_reg2_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_preset_reg1(2),
      Q => txeq_preset_reg2(2),
      R => \out\
    );
\txeq_preset_reg2_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_preset_reg1(3),
      Q => txeq_preset_reg2(3),
      R => \out\
    );
\txeq_preset_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => p_0_out(0),
      Q => \txeq_preset_reg_n_0_[0]\,
      R => '0'
    );
\txeq_preset_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => p_0_out(10),
      Q => \txeq_preset_reg_n_0_[10]\,
      R => '0'
    );
\txeq_preset_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => p_0_out(11),
      Q => \txeq_preset_reg_n_0_[11]\,
      R => '0'
    );
\txeq_preset_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => p_0_out(12),
      Q => \txeq_preset_reg_n_0_[12]\,
      R => '0'
    );
\txeq_preset_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => p_0_out(13),
      Q => \txeq_preset_reg_n_0_[13]\,
      R => '0'
    );
\txeq_preset_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => p_0_out(14),
      Q => \txeq_preset_reg_n_0_[14]\,
      R => '0'
    );
\txeq_preset_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => p_0_out(15),
      Q => \txeq_preset_reg_n_0_[15]\,
      R => '0'
    );
\txeq_preset_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => p_0_out(16),
      Q => \txeq_preset_reg_n_0_[16]\,
      R => '0'
    );
\txeq_preset_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => p_0_out(17),
      Q => \txeq_preset_reg_n_0_[17]\,
      R => '0'
    );
\txeq_preset_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => p_0_out(1),
      Q => \txeq_preset_reg_n_0_[1]\,
      R => '0'
    );
\txeq_preset_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => p_0_out(2),
      Q => \txeq_preset_reg_n_0_[2]\,
      R => '0'
    );
\txeq_preset_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => \txeq_preset[3]_i_1__0_n_0\,
      Q => \txeq_preset_reg_n_0_[3]\,
      R => '0'
    );
\txeq_preset_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => \txeq_preset[7]_i_1__0_n_0\,
      Q => \txeq_preset_reg_n_0_[7]\,
      R => '0'
    );
\txeq_preset_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => p_0_out(8),
      Q => \txeq_preset_reg_n_0_[8]\,
      R => '0'
    );
\txeq_preset_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => \txeq_preset[17]_i_1__0_n_0\,
      D => p_0_out(9),
      Q => \txeq_preset_reg_n_0_[9]\,
      R => '0'
    );
\txeq_txcoeff[0]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"45404040"
    )
        port map (
      I0 => fsm_tx(2),
      I1 => \txeq_txcoeff[0]_i_2__0_n_0\,
      I2 => fsm_tx(1),
      I3 => \txeq_txcoeff_reg_n_0_[6]\,
      I4 => fsm_tx(0),
      O => \txeq_txcoeff[0]_i_1__0_n_0\
    );
\txeq_txcoeff[0]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[7]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[6]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[0]\,
      O => \txeq_txcoeff[0]_i_2__0_n_0\
    );
\txeq_txcoeff[10]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[9]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[10]_i_2__0_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[16]\,
      O => \txeq_txcoeff[10]_i_1__0_n_0\
    );
\txeq_txcoeff[10]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[17]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[16]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[10]\,
      O => \txeq_txcoeff[10]_i_2__0_n_0\
    );
\txeq_txcoeff[11]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[10]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[11]_i_2__0_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[17]\,
      O => \txeq_txcoeff[11]_i_1__0_n_0\
    );
\txeq_txcoeff[11]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[18]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[17]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[11]\,
      O => \txeq_txcoeff[11]_i_2__0_n_0\
    );
\txeq_txcoeff[12]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[11]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[12]_i_2__0_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[18]\,
      O => \txeq_txcoeff[12]_i_1__0_n_0\
    );
\txeq_txcoeff[12]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => txeq_deemph_reg2(0),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[18]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[12]\,
      O => \txeq_txcoeff[12]_i_2__0_n_0\
    );
\txeq_txcoeff[13]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[12]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[13]_i_2__0_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => txeq_deemph_reg2(0),
      O => \txeq_txcoeff[13]_i_1__0_n_0\
    );
\txeq_txcoeff[13]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => txeq_deemph_reg2(1),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => txeq_deemph_reg2(0),
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[13]\,
      O => \txeq_txcoeff[13]_i_2__0_n_0\
    );
\txeq_txcoeff[14]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[13]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[14]_i_2__0_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => txeq_deemph_reg2(1),
      O => \txeq_txcoeff[14]_i_1__0_n_0\
    );
\txeq_txcoeff[14]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => txeq_deemph_reg2(2),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => txeq_deemph_reg2(1),
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[14]\,
      O => \txeq_txcoeff[14]_i_2__0_n_0\
    );
\txeq_txcoeff[15]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[14]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[15]_i_2__0_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => txeq_deemph_reg2(2),
      O => \txeq_txcoeff[15]_i_1__0_n_0\
    );
\txeq_txcoeff[15]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => txeq_deemph_reg2(3),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => txeq_deemph_reg2(2),
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[15]\,
      O => \txeq_txcoeff[15]_i_2__0_n_0\
    );
\txeq_txcoeff[16]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[15]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[16]_i_2__0_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => txeq_deemph_reg2(3),
      O => \txeq_txcoeff[16]_i_1__0_n_0\
    );
\txeq_txcoeff[16]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => txeq_deemph_reg2(4),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => txeq_deemph_reg2(3),
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[16]\,
      O => \txeq_txcoeff[16]_i_2__0_n_0\
    );
\txeq_txcoeff[17]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[16]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[17]_i_2__0_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => txeq_deemph_reg2(4),
      O => \txeq_txcoeff[17]_i_1__0_n_0\
    );
\txeq_txcoeff[17]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => txeq_deemph_reg2(5),
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => txeq_deemph_reg2(4),
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[17]\,
      O => \txeq_txcoeff[17]_i_2__0_n_0\
    );
\txeq_txcoeff[18]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FF040FFF"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      I2 => fsm_tx(2),
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      O => txeq_txcoeff
    );
\txeq_txcoeff[18]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"202020202F202020"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[17]\,
      I1 => fsm_tx(1),
      I2 => fsm_tx(2),
      I3 => txeq_deemph_reg2(5),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff[18]_i_3__0_n_0\,
      O => \txeq_txcoeff[18]_i_2__0_n_0\
    );
\txeq_txcoeff[18]_i_3__0\: unisim.vcomponents.LUT3
    generic map(
      INIT => X"08"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I1 => fsm_tx(1),
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      O => \txeq_txcoeff[18]_i_3__0_n_0\
    );
\txeq_txcoeff[1]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[0]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[1]_i_2__0_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[7]\,
      O => \txeq_txcoeff[1]_i_1__0_n_0\
    );
\txeq_txcoeff[1]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[8]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[7]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[1]\,
      O => \txeq_txcoeff[1]_i_2__0_n_0\
    );
\txeq_txcoeff[2]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[1]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[2]_i_2__0_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[8]\,
      O => \txeq_txcoeff[2]_i_1__0_n_0\
    );
\txeq_txcoeff[2]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[9]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[8]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[2]\,
      O => \txeq_txcoeff[2]_i_2__0_n_0\
    );
\txeq_txcoeff[3]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[2]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[3]_i_2__0_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[9]\,
      O => \txeq_txcoeff[3]_i_1__0_n_0\
    );
\txeq_txcoeff[3]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[10]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[9]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[3]\,
      O => \txeq_txcoeff[3]_i_2__0_n_0\
    );
\txeq_txcoeff[4]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000AE00AEAEAEAE"
    )
        port map (
      I0 => \txeq_txcoeff[4]_i_2__0_n_0\,
      I1 => \txeq_txcoeff_reg_n_0_[10]\,
      I2 => \txeq_txcoeff[5]_i_3__0_n_0\,
      I3 => \txeq_txcoeff_reg_n_0_[3]\,
      I4 => fsm_tx(1),
      I5 => fsm_tx(2),
      O => \txeq_txcoeff[4]_i_1__0_n_0\
    );
\txeq_txcoeff[4]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAEAAAAAAAAAAAAA"
    )
        port map (
      I0 => fsm_tx(2),
      I1 => fsm_tx(1),
      I2 => fsm_tx(0),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I5 => \txeq_txcoeff_reg_n_0_[11]\,
      O => \txeq_txcoeff[4]_i_2__0_n_0\
    );
\txeq_txcoeff[5]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000AE00AEAEAEAE"
    )
        port map (
      I0 => \txeq_txcoeff[5]_i_2__0_n_0\,
      I1 => \txeq_txcoeff_reg_n_0_[11]\,
      I2 => \txeq_txcoeff[5]_i_3__0_n_0\,
      I3 => \txeq_txcoeff_reg_n_0_[4]\,
      I4 => fsm_tx(1),
      I5 => fsm_tx(2),
      O => \txeq_txcoeff[5]_i_1__0_n_0\
    );
\txeq_txcoeff[5]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"AAEAAAAAAAAAAAAA"
    )
        port map (
      I0 => fsm_tx(2),
      I1 => fsm_tx(1),
      I2 => fsm_tx(0),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I5 => \txeq_txcoeff_reg_n_0_[12]\,
      O => \txeq_txcoeff[5]_i_2__0_n_0\
    );
\txeq_txcoeff[5]_i_3__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"40FF"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I1 => fsm_tx(1),
      I2 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I3 => fsm_tx(0),
      O => \txeq_txcoeff[5]_i_3__0_n_0\
    );
\txeq_txcoeff[6]_i_1__0\: unisim.vcomponents.LUT4
    generic map(
      INIT => X"2F20"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[5]\,
      I1 => fsm_tx(1),
      I2 => fsm_tx(2),
      I3 => \txeq_txcoeff[6]_i_2__0_n_0\,
      O => \txeq_txcoeff[6]_i_1__0_n_0\
    );
\txeq_txcoeff[6]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"A0E0A0A0A020A0A0"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[12]\,
      I1 => fsm_tx(1),
      I2 => fsm_tx(0),
      I3 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I4 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I5 => \txeq_txcoeff_reg_n_0_[13]\,
      O => \txeq_txcoeff[6]_i_2__0_n_0\
    );
\txeq_txcoeff[7]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[6]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[7]_i_2__0_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[13]\,
      O => \txeq_txcoeff[7]_i_1__0_n_0\
    );
\txeq_txcoeff[7]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[14]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[13]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[7]\,
      O => \txeq_txcoeff[7]_i_2__0_n_0\
    );
\txeq_txcoeff[8]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[7]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[8]_i_2__0_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[14]\,
      O => \txeq_txcoeff[8]_i_1__0_n_0\
    );
\txeq_txcoeff[8]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[15]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[14]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[8]\,
      O => \txeq_txcoeff[8]_i_2__0_n_0\
    );
\txeq_txcoeff[9]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"30BB308830883088"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[8]\,
      I1 => fsm_tx(2),
      I2 => \txeq_txcoeff[9]_i_2__0_n_0\,
      I3 => fsm_tx(1),
      I4 => fsm_tx(0),
      I5 => \txeq_txcoeff_reg_n_0_[15]\,
      O => \txeq_txcoeff[9]_i_1__0_n_0\
    );
\txeq_txcoeff[9]_i_2__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"FB08FFFFFB080000"
    )
        port map (
      I0 => \txeq_txcoeff_reg_n_0_[16]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I2 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I3 => \txeq_txcoeff_reg_n_0_[15]\,
      I4 => fsm_tx(0),
      I5 => \txeq_preset_reg_n_0_[9]\,
      O => \txeq_txcoeff[9]_i_2__0_n_0\
    );
\txeq_txcoeff_cnt[0]_i_1__0\: unisim.vcomponents.LUT6
    generic map(
      INIT => X"000004000F000400"
    )
        port map (
      I0 => txeq_control_reg2(0),
      I1 => txeq_control_reg2(1),
      I2 => fsm_tx(2),
      I3 => fsm_tx(0),
      I4 => fsm_tx(1),
      I5 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      O => txeq_txcoeff_cnt(0)
    );
\txeq_txcoeff_cnt[1]_i_1__0\: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00006000"
    )
        port map (
      I0 => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      I1 => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      I2 => fsm_tx(0),
      I3 => fsm_tx(1),
      I4 => fsm_tx(2),
      O => txeq_txcoeff_cnt(1)
    );
\txeq_txcoeff_cnt_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_txcoeff_cnt(0),
      Q => \txeq_txcoeff_cnt_reg_n_0_[0]\,
      R => \out\
    );
\txeq_txcoeff_cnt_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => '1',
      D => txeq_txcoeff_cnt(1),
      Q => \txeq_txcoeff_cnt_reg_n_0_[1]\,
      R => \out\
    );
\txeq_txcoeff_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[0]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[0]\,
      R => \out\
    );
\txeq_txcoeff_reg[10]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[10]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[10]\,
      R => \out\
    );
\txeq_txcoeff_reg[11]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[11]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[11]\,
      R => \out\
    );
\txeq_txcoeff_reg[12]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[12]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[12]\,
      R => \out\
    );
\txeq_txcoeff_reg[13]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[13]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[13]\,
      R => \out\
    );
\txeq_txcoeff_reg[14]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[14]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[14]\,
      R => \out\
    );
\txeq_txcoeff_reg[15]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[15]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[15]\,
      R => \out\
    );
\txeq_txcoeff_reg[16]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[16]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[16]\,
      R => \out\
    );
\txeq_txcoeff_reg[17]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[17]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[17]\,
      R => \out\
    );
\txeq_txcoeff_reg[18]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[18]_i_2__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[18]\,
      R => \out\
    );
\txeq_txcoeff_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[1]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[1]\,
      R => \out\
    );
\txeq_txcoeff_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[2]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[2]\,
      R => \out\
    );
\txeq_txcoeff_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[3]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[3]\,
      R => \out\
    );
\txeq_txcoeff_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[4]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[4]\,
      R => \out\
    );
\txeq_txcoeff_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[5]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[5]\,
      R => \out\
    );
\txeq_txcoeff_reg[6]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[6]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[6]\,
      R => \out\
    );
\txeq_txcoeff_reg[7]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[7]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[7]\,
      R => \out\
    );
\txeq_txcoeff_reg[8]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[8]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[8]\,
      R => \out\
    );
\txeq_txcoeff_reg[9]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \fs_reg2_reg[5]\,
      CE => txeq_txcoeff,
      D => \txeq_txcoeff[9]_i_1__0_n_0\,
      Q => \txeq_txcoeff_reg_n_0_[9]\,
      R => \out\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_top is
  port (
    trn_rsrc_dsc_d : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    m_axis_rx_tvalid_xhdl2_reg : out STD_LOGIC;
    m_axis_rx_tlast : out STD_LOGIC;
    trn_teof : out STD_LOGIC;
    trn_tsrc_rdy : out STD_LOGIC;
    trn_trem : out STD_LOGIC_VECTOR ( 0 to 0 );
    reg_tcfg_gnt : out STD_LOGIC;
    tready_thrtl_xhdl1_reg : out STD_LOGIC;
    trn_in_packet : out STD_LOGIC;
    reg_dsc_detect : out STD_LOGIC;
    ppm_L1_thrtl : out STD_LOGIC;
    reg_to_turnoff : out STD_LOGIC;
    lnk_up_thrtl : out STD_LOGIC;
    m_axis_rx_tuser : out STD_LOGIC_VECTOR ( 12 downto 0 );
    cfg_pm_turnoff_ok_n : out STD_LOGIC;
    trn_tcfg_gnt : out STD_LOGIC;
    trn_tsof : out STD_LOGIC;
    ppm_L1_trig : out STD_LOGIC;
    m_axis_rx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_rx_tkeep : out STD_LOGIC_VECTOR ( 1 downto 0 );
    Q : out STD_LOGIC_VECTOR ( 63 downto 0 );
    \xhdl12.reg_tuser_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
    \tbuf_gap_cnt_reg[0]\ : in STD_LOGIC;
    CLK : in STD_LOGIC;
    trn_rsrc_dsc : in STD_LOGIC;
    rsrc_rdy_filtered6_out : in STD_LOGIC;
    trn_rrem : in STD_LOGIC_VECTOR ( 0 to 0 );
    trn_reof : in STD_LOGIC;
    trn_rsrc_dsc_prev0 : in STD_LOGIC;
    trn_rsof : in STD_LOGIC;
    trn_recrc_err : in STD_LOGIC;
    trn_rerrfwd : in STD_LOGIC;
    s_axis_tx_tlast : in STD_LOGIC;
    s_axis_tx_tvalid : in STD_LOGIC;
    s_axis_tx_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
    tx_cfg_gnt : in STD_LOGIC;
    trn_tdst_rdy : in STD_LOGIC;
    trn_tcfg_req : in STD_LOGIC;
    cfg_turnoff_ok : in STD_LOGIC;
    tbuf_av_min_trig : in STD_LOGIC;
    trn_in_packet_reg : in STD_LOGIC;
    ppm_L1_thrtl_reg : in STD_LOGIC;
    \xhdl12.xhdl14.xhdl15.reg_to_turnoff_reg\ : in STD_LOGIC;
    lnk_up_thrtl_reg : in STD_LOGIC;
    m_axis_rx_tready : in STD_LOGIC;
    dsc_detect : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axis_tx_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
    tready_thrtl_xhdl1_i_4 : in STD_LOGIC;
    trn_tbuf_av : in STD_LOGIC_VECTOR ( 5 downto 0 );
    tcfg_req_trig : in STD_LOGIC;
    cfg_pcie_link_state : in STD_LOGIC_VECTOR ( 2 downto 0 );
    trn_rd : in STD_LOGIC_VECTOR ( 63 downto 0 );
    trn_rbar_hit : in STD_LOGIC_VECTOR ( 6 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_top : entity is "spec7_pcie_7x_0_axi_basic_top";
end spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_top;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_top is
begin
rx_inst: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_rx
     port map (
      CLK => CLK,
      E(0) => E(0),
      dsc_detect => dsc_detect,
      m_axis_rx_tdata(63 downto 0) => m_axis_rx_tdata(63 downto 0),
      m_axis_rx_tkeep(1 downto 0) => m_axis_rx_tkeep(1 downto 0),
      m_axis_rx_tlast => m_axis_rx_tlast,
      m_axis_rx_tready => m_axis_rx_tready,
      m_axis_rx_tuser(12 downto 0) => m_axis_rx_tuser(12 downto 0),
      m_axis_rx_tvalid_xhdl2_reg => m_axis_rx_tvalid_xhdl2_reg,
      reg_dsc_detect_reg => reg_dsc_detect,
      rsrc_rdy_filtered6_out => rsrc_rdy_filtered6_out,
      trn_in_packet => trn_in_packet,
      trn_in_packet_reg => trn_in_packet_reg,
      trn_rbar_hit(6 downto 0) => trn_rbar_hit(6 downto 0),
      \trn_rbar_hit_prev_reg[0]\ => \tbuf_gap_cnt_reg[0]\,
      trn_rd(63 downto 0) => trn_rd(63 downto 0),
      trn_recrc_err => trn_recrc_err,
      trn_reof => trn_reof,
      trn_rerrfwd => trn_rerrfwd,
      trn_rrem(0) => trn_rrem(0),
      trn_rsof => trn_rsof,
      trn_rsrc_dsc => trn_rsrc_dsc,
      trn_rsrc_dsc_d => trn_rsrc_dsc_d,
      trn_rsrc_dsc_prev0 => trn_rsrc_dsc_prev0
    );
tx_inst: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_tx
     port map (
      CLK => CLK,
      Q(63 downto 0) => Q(63 downto 0),
      cfg_pcie_link_state(2 downto 0) => cfg_pcie_link_state(2 downto 0),
      cfg_pm_turnoff_ok_n => cfg_pm_turnoff_ok_n,
      cfg_turnoff_ok => cfg_turnoff_ok,
      lnk_up_thrtl => lnk_up_thrtl,
      lnk_up_thrtl_reg => lnk_up_thrtl_reg,
      \out\ => \out\,
      ppm_L1_thrtl => ppm_L1_thrtl,
      ppm_L1_thrtl_reg => ppm_L1_thrtl_reg,
      ppm_L1_trig => ppm_L1_trig,
      reg_tcfg_gnt => reg_tcfg_gnt,
      s_axis_tx_tdata(63 downto 0) => s_axis_tx_tdata(63 downto 0),
      s_axis_tx_tkeep(0) => s_axis_tx_tkeep(0),
      s_axis_tx_tlast => s_axis_tx_tlast,
      s_axis_tx_tuser(3 downto 0) => s_axis_tx_tuser(3 downto 0),
      s_axis_tx_tvalid => s_axis_tx_tvalid,
      tbuf_av_min_trig => tbuf_av_min_trig,
      \tbuf_gap_cnt_reg[0]\ => \tbuf_gap_cnt_reg[0]\,
      tcfg_req_trig => tcfg_req_trig,
      tready_thrtl_xhdl1_i_4 => tready_thrtl_xhdl1_i_4,
      tready_thrtl_xhdl1_reg => tready_thrtl_xhdl1_reg,
      trn_tbuf_av(5 downto 0) => trn_tbuf_av(5 downto 0),
      trn_tcfg_gnt => trn_tcfg_gnt,
      trn_tcfg_req => trn_tcfg_req,
      trn_tdst_rdy => trn_tdst_rdy,
      trn_teof => trn_teof,
      trn_trem(0) => trn_trem(0),
      trn_tsof => trn_tsof,
      trn_tsrc_rdy => trn_tsrc_rdy,
      tx_cfg_gnt => tx_cfg_gnt,
      \xhdl12.reg_tuser_reg[3]\(3 downto 0) => \xhdl12.reg_tuser_reg[3]\(3 downto 0),
      \xhdl12.xhdl14.xhdl15.reg_to_turnoff_reg\ => reg_to_turnoff,
      \xhdl12.xhdl14.xhdl15.reg_to_turnoff_reg_0\ => \xhdl12.xhdl14.xhdl15.reg_to_turnoff_reg\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_brams_7x is
  port (
    \ramb_bl.ramb36_dp_bl.ram36_bl\ : out STD_LOGIC_VECTOR ( 67 downto 0 );
    CLK : in STD_LOGIC;
    mim_rx_wen : in STD_LOGIC;
    mim_rx_ren : in STD_LOGIC;
    MIMRXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMRXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_0\ : in STD_LOGIC_VECTOR ( 67 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_brams_7x : entity is "spec7_pcie_7x_0_pcie_brams_7x";
end spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_brams_7x;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_brams_7x is
begin
\brams[0].ram\: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_7
     port map (
      CLK => CLK,
      MIMRXRADDR(10 downto 0) => MIMRXRADDR(10 downto 0),
      MIMRXWADDR(10 downto 0) => MIMRXWADDR(10 downto 0),
      mim_rx_ren => mim_rx_ren,
      mim_rx_wen => mim_rx_wen,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(17 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl\(17 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_0\(17 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(17 downto 0)
    );
\brams[1].ram\: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_8
     port map (
      CLK => CLK,
      MIMRXRADDR(10 downto 0) => MIMRXRADDR(10 downto 0),
      MIMRXWADDR(10 downto 0) => MIMRXWADDR(10 downto 0),
      mim_rx_ren => mim_rx_ren,
      mim_rx_wen => mim_rx_wen,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(17 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl\(35 downto 18),
      \ramb_bl.ramb36_dp_bl.ram36_bl_0\(17 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(35 downto 18)
    );
\brams[2].ram\: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_9
     port map (
      CLK => CLK,
      MIMRXRADDR(10 downto 0) => MIMRXRADDR(10 downto 0),
      MIMRXWADDR(10 downto 0) => MIMRXWADDR(10 downto 0),
      mim_rx_ren => mim_rx_ren,
      mim_rx_wen => mim_rx_wen,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(17 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl\(53 downto 36),
      \ramb_bl.ramb36_dp_bl.ram36_bl_0\(17 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(53 downto 36)
    );
\brams[3].ram\: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_10
     port map (
      CLK => CLK,
      MIMRXRADDR(10 downto 0) => MIMRXRADDR(10 downto 0),
      MIMRXWADDR(10 downto 0) => MIMRXWADDR(10 downto 0),
      mim_rx_ren => mim_rx_ren,
      mim_rx_wen => mim_rx_wen,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(13 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl\(67 downto 54),
      \ramb_bl.ramb36_dp_bl.ram36_bl_0\(13 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(67 downto 54)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_brams_7x_0 is
  port (
    rdata : out STD_LOGIC_VECTOR ( 68 downto 0 );
    CLK : in STD_LOGIC;
    mim_tx_wen : in STD_LOGIC;
    mim_tx_ren : in STD_LOGIC;
    MIMTXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMTXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    wdata : in STD_LOGIC_VECTOR ( 68 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_brams_7x_0 : entity is "spec7_pcie_7x_0_pcie_brams_7x";
end spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_brams_7x_0;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_brams_7x_0 is
begin
\brams[0].ram\: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x
     port map (
      CLK => CLK,
      MIMTXRADDR(10 downto 0) => MIMTXRADDR(10 downto 0),
      MIMTXWADDR(10 downto 0) => MIMTXWADDR(10 downto 0),
      mim_tx_ren => mim_tx_ren,
      mim_tx_wen => mim_tx_wen,
      rdata(17 downto 0) => rdata(17 downto 0),
      wdata(17 downto 0) => wdata(17 downto 0)
    );
\brams[1].ram\: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_1
     port map (
      CLK => CLK,
      MIMTXRADDR(10 downto 0) => MIMTXRADDR(10 downto 0),
      MIMTXWADDR(10 downto 0) => MIMTXWADDR(10 downto 0),
      mim_tx_ren => mim_tx_ren,
      mim_tx_wen => mim_tx_wen,
      rdata(17 downto 0) => rdata(35 downto 18),
      wdata(17 downto 0) => wdata(35 downto 18)
    );
\brams[2].ram\: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_2
     port map (
      CLK => CLK,
      MIMTXRADDR(10 downto 0) => MIMTXRADDR(10 downto 0),
      MIMTXWADDR(10 downto 0) => MIMTXWADDR(10 downto 0),
      mim_tx_ren => mim_tx_ren,
      mim_tx_wen => mim_tx_wen,
      rdata(17 downto 0) => rdata(53 downto 36),
      wdata(17 downto 0) => wdata(53 downto 36)
    );
\brams[3].ram\: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_7x_3
     port map (
      CLK => CLK,
      MIMTXRADDR(10 downto 0) => MIMTXRADDR(10 downto 0),
      MIMTXWADDR(10 downto 0) => MIMTXWADDR(10 downto 0),
      mim_tx_ren => mim_tx_ren,
      mim_tx_wen => mim_tx_wen,
      rdata(14 downto 0) => rdata(68 downto 54),
      wdata(14 downto 0) => wdata(68 downto 54)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_wrapper is
  port (
    pipe_txoutclk_out : out STD_LOGIC;
    pclk_sel_reg : out STD_LOGIC;
    CLK : out STD_LOGIC;
    mmcm_i : out STD_LOGIC;
    mmcm_i_i_1 : out STD_LOGIC;
    QRST_IDLE : out STD_LOGIC;
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    QPLL_QPLLLOCK : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ext_ch_gt_drprdy : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gen3_reg : out STD_LOGIC;
    pclk_sel_reg_0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxstatus : out STD_LOGIC_VECTOR ( 5 downto 0 );
    pipe_eyescandataerror : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_txn : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_txp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rx0_chanisaligned : out STD_LOGIC;
    pipe_rxcommadet : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxdlysresetdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    PIPE_RXELECIDLE : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxphaligndone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxprbserr : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_txdlysresetdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_txphaligndone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_txphinitdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ext_ch_gt_drpdo : out STD_LOGIC_VECTOR ( 31 downto 0 );
    pipe_rxbufstatus : out STD_LOGIC_VECTOR ( 5 downto 0 );
    sys_clk_0 : out STD_LOGIC_VECTOR ( 31 downto 0 );
    pipe_dmonitorout : out STD_LOGIC_VECTOR ( 15 downto 0 );
    sys_clk_1 : out STD_LOGIC_VECTOR ( 3 downto 0 );
    pipe_rxdisperr : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_rxnotintable : out STD_LOGIC_VECTOR ( 15 downto 0 );
    int_qplloutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    int_qplloutrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    \FSM_onehot_txsync_fsm.fsm_tx_reg[6]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    pipe_rx1_chanisaligned : out STD_LOGIC;
    \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    sys_rst_n : out STD_LOGIC;
    \fsm_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    mmcm_i_0 : out STD_LOGIC;
    gt_rxvalid_q : out STD_LOGIC;
    pipe_rst_fsm : out STD_LOGIC_VECTOR ( 3 downto 0 );
    pipe_rate_fsm : out STD_LOGIC_VECTOR ( 9 downto 0 );
    gt_rxvalid_q_reg : out STD_LOGIC;
    pipe_rate_idle : out STD_LOGIC;
    rst_idle_reg2_reg : out STD_LOGIC;
    gt_rxvalid_q_reg_0 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    gt_rxvalid_q_reg_1 : out STD_LOGIC_VECTOR ( 2 downto 0 );
    PIPE_PHYSTATUS : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_sync_fsm_rx : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \fsm_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    gt_ch_drp_rdy : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_qrst_fsm : out STD_LOGIC_VECTOR ( 3 downto 0 );
    pipe_tx0_elec_idle : in STD_LOGIC;
    pipe_tx0_compliance : in STD_LOGIC;
    sys_clk : in STD_LOGIC;
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rx0_polarity : in STD_LOGIC;
    pipe_tx_deemph : in STD_LOGIC;
    pipe_tx_rcvr_det : in STD_LOGIC;
    pipe_txinhibit : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx0_powerdown : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx_margin : in STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_tx0_data : in STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_tx0_char_is_k : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx1_elec_idle : in STD_LOGIC;
    pipe_tx1_compliance : in STD_LOGIC;
    pipe_rx1_polarity : in STD_LOGIC;
    pipe_tx1_powerdown : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx1_data : in STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_tx1_char_is_k : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ext_ch_gt_drpaddr : in STD_LOGIC_VECTOR ( 17 downto 0 );
    pipe_mmcm_rst_n : in STD_LOGIC;
    reset_n_reg2_reg_0 : in STD_LOGIC;
    gt_rxvalid_q_reg_2 : in STD_LOGIC;
    gt_rxvalid_q_reg_3 : in STD_LOGIC_VECTOR ( 0 to 0 );
    \gt_rx_status_q_reg[2]\ : in STD_LOGIC;
    \gt_rx_status_q_reg[0]\ : in STD_LOGIC;
    reg_clock_locked : in STD_LOGIC;
    \gt_rx_status_q_reg[0]_0\ : in STD_LOGIC;
    pipe_tx_rate : in STD_LOGIC;
    int_pclk_sel_slave : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ext_ch_gt_drpen : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ext_ch_gt_drpwe : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ext_ch_gt_drpdi : in STD_LOGIC_VECTOR ( 31 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_wrapper : entity is "spec7_pcie_7x_0_pipe_wrapper";
end spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_wrapper;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_wrapper is
  signal \^clk\ : STD_LOGIC;
  signal CPLLRESET0 : STD_LOGIC;
  signal CPLLRESET0_5 : STD_LOGIC;
  signal \^d\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^fsm_onehot_txsync_fsm.fsm_tx_reg[6]\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \^fsm_onehot_txsync_fsm.fsm_tx_reg[6]_0\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \^pipe_rxelecidle\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^qpll_qplllock\ : STD_LOGIC;
  signal \^qrst_idle\ : STD_LOGIC;
  signal SYNC_TXSYNC_START0 : STD_LOGIC;
  signal SYNC_TXSYNC_START02_out : STD_LOGIC;
  signal cpllrst : STD_LOGIC;
  signal cpllrst_1 : STD_LOGIC;
  signal drp_mux_addr_0 : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal drp_mux_addr_9 : STD_LOGIC_VECTOR ( 8 downto 0 );
  signal drp_mux_di_0 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal drp_mux_di_16 : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal drp_mux_en_0 : STD_LOGIC;
  signal drp_mux_en_1 : STD_LOGIC;
  signal drp_mux_we_0 : STD_LOGIC;
  signal drp_mux_we_1 : STD_LOGIC;
  signal eq_txeq_maincursor_0 : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal eq_txeq_maincursor_7 : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal eq_txeq_postcursor_0 : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal eq_txeq_postcursor_5 : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal eq_txeq_precursor_0 : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal eq_txeq_precursor_5 : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal \^ext_ch_gt_drpdo\ : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal \^ext_ch_gt_drprdy\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^gen3_reg\ : STD_LOGIC;
  signal gt_cpllpdrefclk : STD_LOGIC;
  signal gt_phystatus_0 : STD_LOGIC;
  signal gt_phystatus_1 : STD_LOGIC;
  signal gt_rxcdrlock_0 : STD_LOGIC;
  signal gt_rxcdrlock_1 : STD_LOGIC;
  signal \gt_rxchbondo[1]_0\ : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal gt_rxratedone_0 : STD_LOGIC;
  signal gt_rxratedone_1 : STD_LOGIC;
  signal gt_rxresetdone_0 : STD_LOGIC;
  signal gt_rxresetdone_1 : STD_LOGIC;
  signal gt_rxvalid_0 : STD_LOGIC;
  signal gt_rxvalid_1 : STD_LOGIC;
  signal gt_txratedone_0 : STD_LOGIC;
  signal gt_txratedone_1 : STD_LOGIC;
  signal gt_txresetdone_0 : STD_LOGIC;
  signal gt_txresetdone_1 : STD_LOGIC;
  signal \^int_qplloutclk_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^int_qplloutrefclk_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^mmcm_i_i_1\ : STD_LOGIC;
  signal p_0_in1_in : STD_LOGIC;
  signal p_0_in1_in_3 : STD_LOGIC;
  signal p_103_out : STD_LOGIC;
  signal p_1_in : STD_LOGIC;
  signal p_1_in0_in : STD_LOGIC;
  signal p_1_in0_in_2 : STD_LOGIC;
  signal p_1_in2_in : STD_LOGIC;
  signal p_1_in2_in_4 : STD_LOGIC;
  signal p_1_in_0 : STD_LOGIC;
  signal p_30_out : STD_LOGIC;
  signal p_36_out : STD_LOGIC;
  signal p_48_out : STD_LOGIC;
  signal p_85_out : STD_LOGIC;
  signal p_91_out : STD_LOGIC;
  signal \^pclk_sel_reg\ : STD_LOGIC;
  signal \^pclk_sel_reg_0\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \pipe_lane[0].pipe_drp.pipe_drp_i_n_4\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_eq.pipe_eq_i_n_0\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_rate.pipe_rate_i_n_21\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_sync_i_n_1\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_sync_i_n_3\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_user_i_n_10\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_user_i_n_2\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_user_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_user_i_n_8\ : STD_LOGIC;
  signal \pipe_lane[0].pipe_user_i_n_9\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_eq.pipe_eq_i_n_0\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_sync_i_n_1\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_user_i_n_11\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_user_i_n_12\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_user_i_n_3\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_user_i_n_7\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_user_i_n_8\ : STD_LOGIC;
  signal \pipe_lane[1].pipe_user_i_n_9\ : STD_LOGIC;
  signal \pipe_reset.pipe_reset_i_n_3\ : STD_LOGIC;
  signal \^pipe_rxdlysresetdone\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^pipe_rxphaligndone\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^pipe_rxstatus\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \^pipe_txdlysresetdone\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^pipe_txoutclk_out\ : STD_LOGIC;
  signal \^pipe_txphaligndone\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \^pipe_txphinitdone\ : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal qdrp_done : STD_LOGIC;
  signal qpllpd : STD_LOGIC;
  signal qrst_drp_start : STD_LOGIC;
  signal qrst_qpllreset : STD_LOGIC;
  signal rate_cpllpd_0 : STD_LOGIC;
  signal rate_cpllpd_1 : STD_LOGIC;
  signal rate_cpllreset_0 : STD_LOGIC;
  signal rate_done_0 : STD_LOGIC;
  signal rate_done_1 : STD_LOGIC;
  signal rate_drp_start_0 : STD_LOGIC;
  signal rate_drp_start_1 : STD_LOGIC;
  signal rate_drp_x16x20_mode_0 : STD_LOGIC;
  signal rate_drp_x16x20_mode_1 : STD_LOGIC;
  signal rate_gen3_1 : STD_LOGIC;
  signal rate_idle : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rate_qpllpd : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rate_qpllreset : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal rate_rate_0 : STD_LOGIC_VECTOR ( 0 to 0 );
  signal rate_rate_3 : STD_LOGIC_VECTOR ( 0 to 0 );
  signal rate_rxpmareset_0 : STD_LOGIC;
  signal rate_rxpmareset_1 : STD_LOGIC;
  signal rate_sysclksel_0 : STD_LOGIC_VECTOR ( 0 to 0 );
  signal rate_sysclksel_2 : STD_LOGIC_VECTOR ( 0 to 0 );
  signal rate_txsync_start_0 : STD_LOGIC;
  signal rate_txsync_start_1 : STD_LOGIC;
  signal reset_n_reg1 : STD_LOGIC;
  attribute SHIFT_EXTRACT : string;
  attribute SHIFT_EXTRACT of reset_n_reg1 : signal is "NO";
  attribute async_reg : string;
  attribute async_reg of reset_n_reg1 : signal is "true";
  signal reset_n_reg2 : STD_LOGIC;
  attribute SHIFT_EXTRACT of reset_n_reg2 : signal is "NO";
  attribute async_reg of reset_n_reg2 : signal is "true";
  signal rst_cpllreset : STD_LOGIC;
  signal rst_dclk_reset : STD_LOGIC;
  signal rst_gtreset : STD_LOGIC;
  signal rst_userrdy : STD_LOGIC;
  signal rxchbonden_0 : STD_LOGIC;
  signal rxchbonden_1 : STD_LOGIC;
  signal rxdlysresetdone_1 : STD_LOGIC;
  signal sync_txdlyen_0 : STD_LOGIC;
  signal \^sys_rst_n\ : STD_LOGIC;
  signal txdlysresetdone_1 : STD_LOGIC;
  signal txsyncallin : STD_LOGIC;
  signal user_oobclk_0 : STD_LOGIC;
  signal user_oobclk_1 : STD_LOGIC;
  signal user_resetdone : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute box_type : string;
  attribute box_type of cpllpd_refclk_inst : label is "PRIMITIVE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of reset_n_reg1_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of reset_n_reg1_reg : label is "yes";
  attribute SHIFT_EXTRACT of reset_n_reg1_reg : label is "NO";
  attribute ASYNC_REG_boolean of reset_n_reg2_reg : label is std.standard.true;
  attribute KEEP of reset_n_reg2_reg : label is "yes";
  attribute SHIFT_EXTRACT of reset_n_reg2_reg : label is "NO";
begin
  CLK <= \^clk\;
  D(1 downto 0) <= \^d\(1 downto 0);
  \FSM_onehot_txsync_fsm.fsm_tx_reg[6]\(5 downto 0) <= \^fsm_onehot_txsync_fsm.fsm_tx_reg[6]\(5 downto 0);
  \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\(5 downto 0) <= \^fsm_onehot_txsync_fsm.fsm_tx_reg[6]_0\(5 downto 0);
  PIPE_RXELECIDLE(1 downto 0) <= \^pipe_rxelecidle\(1 downto 0);
  Q(1 downto 0) <= \^q\(1 downto 0);
  QPLL_QPLLLOCK <= \^qpll_qplllock\;
  QRST_IDLE <= \^qrst_idle\;
  ext_ch_gt_drpdo(31 downto 0) <= \^ext_ch_gt_drpdo\(31 downto 0);
  ext_ch_gt_drprdy(1 downto 0) <= \^ext_ch_gt_drprdy\(1 downto 0);
  gen3_reg <= \^gen3_reg\;
  int_qplloutclk_out(0) <= \^int_qplloutclk_out\(0);
  int_qplloutrefclk_out(0) <= \^int_qplloutrefclk_out\(0);
  mmcm_i_i_1 <= \^mmcm_i_i_1\;
  pclk_sel_reg <= \^pclk_sel_reg\;
  pclk_sel_reg_0(1 downto 0) <= \^pclk_sel_reg_0\(1 downto 0);
  pipe_rxdlysresetdone(1 downto 0) <= \^pipe_rxdlysresetdone\(1 downto 0);
  pipe_rxphaligndone(1 downto 0) <= \^pipe_rxphaligndone\(1 downto 0);
  pipe_rxstatus(5 downto 0) <= \^pipe_rxstatus\(5 downto 0);
  pipe_txdlysresetdone(1 downto 0) <= \^pipe_txdlysresetdone\(1 downto 0);
  pipe_txoutclk_out <= \^pipe_txoutclk_out\;
  pipe_txphaligndone(1 downto 0) <= \^pipe_txphaligndone\(1 downto 0);
  pipe_txphinitdone(1 downto 0) <= \^pipe_txphinitdone\(1 downto 0);
  sys_rst_n <= \^sys_rst_n\;
cpllpd_refclk_inst: unisim.vcomponents.BUFG
     port map (
      I => sys_clk,
      O => gt_cpllpdrefclk
    );
\pipe_clock_int.pipe_clock_i\: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_clock
     port map (
      CLK => \^clk\,
      D(1 downto 0) => \^pclk_sel_reg_0\(1 downto 0),
      SYNC_GEN3 => \^gen3_reg\,
      SYNC_MMCM_LOCK => \^mmcm_i_i_1\,
      int_pclk_sel_slave(1 downto 0) => int_pclk_sel_slave(1 downto 0),
      mmcm_i_0 => mmcm_i,
      mmcm_i_1 => mmcm_i_0,
      pclk_sel_reg_0 => \^pclk_sel_reg\,
      pipe_mmcm_rst_n => pipe_mmcm_rst_n,
      pipe_txoutclk_out => \^pipe_txoutclk_out\
    );
\pipe_lane[0].gt_wrapper_i\: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_gt_wrapper
     port map (
      CLK => \^clk\,
      CLKRSVD(0) => user_oobclk_0,
      CPLLRESET0 => CPLLRESET0_5,
      D(0) => \^d\(0),
      DRPADDR(8) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_4\,
      DRPADDR(7 downto 0) => drp_mux_addr_0(7 downto 0),
      DRPDI(15 downto 0) => drp_mux_di_0(15 downto 0),
      PIPE_RXELECIDLE(0) => \^pipe_rxelecidle\(0),
      Q(2 downto 0) => \^fsm_onehot_txsync_fsm.fsm_tx_reg[6]\(4 downto 2),
      RXCHBONDO(4 downto 0) => \gt_rxchbondo[1]_0\(4 downto 0),
      RXRATE(0) => rate_rate_0(0),
      RXSYSCLKSEL(0) => rate_sysclksel_0(0),
      SYNC_RXDLYSRESETDONE => rxdlysresetdone_1,
      SYNC_TXDLYSRESETDONE => txdlysresetdone_1,
      TXMAINCURSOR(6 downto 0) => eq_txeq_maincursor_0(6 downto 0),
      TXPOSTCURSOR(4 downto 0) => eq_txeq_postcursor_0(4 downto 0),
      TXPRECURSOR(4 downto 0) => eq_txeq_precursor_0(4 downto 0),
      \cplllock_reg1_reg[0]\ => \pipe_lane[0].pipe_user_i_n_7\,
      \cplllock_reg1_reg[0]_0\ => \^pclk_sel_reg\,
      cpllrst => cpllrst,
      drp_mux_en_0 => drp_mux_en_0,
      drp_mux_we_0 => drp_mux_we_0,
      ext_ch_gt_drpdo(15 downto 0) => \^ext_ch_gt_drpdo\(15 downto 0),
      ext_ch_gt_drprdy(0) => \^ext_ch_gt_drprdy\(0),
      gt_cpllpdrefclk => gt_cpllpdrefclk,
      \gt_rx_status_q_reg[0]\ => \gt_rx_status_q_reg[0]_0\,
      \gt_rx_status_q_reg[2]\ => \gt_rx_status_q_reg[2]\,
      gt_rxcdrlock_0 => gt_rxcdrlock_0,
      gt_rxratedone_0 => gt_rxratedone_0,
      gt_rxresetdone_0 => gt_rxresetdone_0,
      gt_rxvalid_0 => gt_rxvalid_0,
      gt_rxvalid_q_reg(2 downto 0) => gt_rxvalid_q_reg_1(2 downto 0),
      gt_txratedone_0 => gt_txratedone_0,
      gt_txresetdone_0 => gt_txresetdone_0,
      int_qplloutclk_out(0) => \^int_qplloutclk_out\(0),
      int_qplloutrefclk_out(0) => \^int_qplloutrefclk_out\(0),
      pci_exp_rxn(0) => pci_exp_rxn(0),
      pci_exp_rxp(0) => pci_exp_rxp(0),
      pci_exp_txn(0) => pci_exp_txn(0),
      pci_exp_txp(0) => pci_exp_txp(0),
      pipe_dmonitorout(7 downto 0) => pipe_dmonitorout(7 downto 0),
      pipe_eyescandataerror(0) => pipe_eyescandataerror(0),
      pipe_rx0_chanisaligned => pipe_rx0_chanisaligned,
      pipe_rx0_polarity => pipe_rx0_polarity,
      pipe_rxbufstatus(2 downto 0) => pipe_rxbufstatus(2 downto 0),
      pipe_rxcommadet(0) => pipe_rxcommadet(0),
      pipe_rxdisperr(7 downto 0) => pipe_rxdisperr(7 downto 0),
      pipe_rxdlysresetdone(0) => \^pipe_rxdlysresetdone\(0),
      pipe_rxnotintable(7 downto 0) => pipe_rxnotintable(7 downto 0),
      pipe_rxoutclk_out(0) => pipe_rxoutclk_out(0),
      pipe_rxphaligndone(0) => \^pipe_rxphaligndone\(0),
      pipe_rxprbserr(0) => pipe_rxprbserr(0),
      pipe_rxstatus(2 downto 0) => \^pipe_rxstatus\(2 downto 0),
      pipe_tx0_char_is_k(1 downto 0) => pipe_tx0_char_is_k(1 downto 0),
      pipe_tx0_compliance => pipe_tx0_compliance,
      pipe_tx0_data(15 downto 0) => pipe_tx0_data(15 downto 0),
      pipe_tx0_elec_idle => pipe_tx0_elec_idle,
      pipe_tx0_powerdown(1 downto 0) => pipe_tx0_powerdown(1 downto 0),
      pipe_tx_deemph => pipe_tx_deemph,
      pipe_tx_margin(2 downto 0) => pipe_tx_margin(2 downto 0),
      pipe_tx_rcvr_det => pipe_tx_rcvr_det,
      pipe_txdlysresetdone(0) => \^pipe_txdlysresetdone\(0),
      pipe_txinhibit(0) => pipe_txinhibit(0),
      pipe_txoutclk_out => \^pipe_txoutclk_out\,
      pipe_txphaligndone(0) => \^pipe_txphaligndone\(0),
      pipe_txphinitdone(0) => \^pipe_txphinitdone\(0),
      rate_cpllpd_0 => rate_cpllpd_0,
      rate_rxpmareset_0 => rate_rxpmareset_0,
      rst_gtreset => rst_gtreset,
      rst_userrdy => rst_userrdy,
      rxchbonden_0 => rxchbonden_0,
      rxdlysresetdone_reg1_reg(0) => \^pipe_rxdlysresetdone\(1),
      sync_txdlyen_0 => sync_txdlyen_0,
      sys_clk => sys_clk,
      sys_clk_0(0) => gt_phystatus_0,
      sys_clk_1(15 downto 0) => sys_clk_0(15 downto 0),
      sys_clk_2(1 downto 0) => sys_clk_1(1 downto 0),
      txdlysresetdone_reg1_reg(0) => \^pipe_txdlysresetdone\(1)
    );
\pipe_lane[0].pipe_drp.pipe_drp_i\: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_drp
     port map (
      CLK => \^clk\,
      D(0) => p_103_out,
      DRPADDR(8) => \pipe_lane[0].pipe_drp.pipe_drp_i_n_4\,
      DRPADDR(7 downto 0) => drp_mux_addr_0(7 downto 0),
      DRPDI(15 downto 0) => drp_mux_di_0(15 downto 0),
      Q(2 downto 0) => \fsm_reg[2]\(2 downto 0),
      SR(0) => rst_dclk_reset,
      drp_mux_en_0 => drp_mux_en_0,
      drp_mux_we_0 => drp_mux_we_0,
      ext_ch_gt_drpaddr(8 downto 0) => ext_ch_gt_drpaddr(8 downto 0),
      ext_ch_gt_drpdi(15 downto 0) => ext_ch_gt_drpdi(15 downto 0),
      ext_ch_gt_drpdo(15 downto 0) => \^ext_ch_gt_drpdo\(15 downto 0),
      ext_ch_gt_drpen(0) => ext_ch_gt_drpen(0),
      ext_ch_gt_drprdy(0) => \^ext_ch_gt_drprdy\(0),
      ext_ch_gt_drpwe(0) => ext_ch_gt_drpwe(0),
      gt_ch_drp_rdy(0) => gt_ch_drp_rdy(0),
      pipe_tx_rate => pipe_tx_rate,
      rate_drp_start_0 => rate_drp_start_0,
      rate_drp_x16x20_mode_0 => rate_drp_x16x20_mode_0,
      rst_gtreset => rst_gtreset
    );
\pipe_lane[0].pipe_eq.pipe_eq_i\: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_eq
     port map (
      SYNC_GEN3 => \^gen3_reg\,
      TXMAINCURSOR(6 downto 0) => eq_txeq_maincursor_0(6 downto 0),
      TXPOSTCURSOR(4 downto 0) => eq_txeq_postcursor_0(4 downto 0),
      TXPRECURSOR(4 downto 0) => eq_txeq_precursor_0(4 downto 0),
      \fs_reg2_reg[5]\ => \^pclk_sel_reg\,
      \out\ => rst_cpllreset,
      rxeq_adapt_done_reg_0 => \pipe_lane[0].pipe_eq.pipe_eq_i_n_0\
    );
\pipe_lane[0].pipe_quad.gt_common_enabled.gt_common_int.gt_common_i\: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_gt_common
     port map (
      CLK => \^clk\,
      QPLL_DRP_DONE => qdrp_done,
      QPLL_DRP_GEN3 => \pipe_lane[0].pipe_rate.pipe_rate_i_n_21\,
      QPLL_QPLLLOCK => \^qpll_qplllock\,
      QPLL_QPLLPD => qpllpd,
      QPLL_QPLLRESET => qrst_qpllreset,
      QRST_DRP_START => qrst_drp_start,
      int_qplloutclk_out(0) => \^int_qplloutclk_out\(0),
      int_qplloutrefclk_out(0) => \^int_qplloutrefclk_out\(0),
      \out\ => rst_dclk_reset,
      sys_clk => sys_clk
    );
\pipe_lane[0].pipe_rate.pipe_rate_i\: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_rate
     port map (
      D(0) => gt_phystatus_0,
      \FSM_onehot_fsm_reg[14]_0\ => \pipe_lane[0].pipe_user_i_n_10\,
      \FSM_onehot_fsm_reg[18]_0\(2) => rate_txsync_start_0,
      \FSM_onehot_fsm_reg[18]_0\(1) => rate_done_0,
      \FSM_onehot_fsm_reg[18]_0\(0) => rate_idle(0),
      \FSM_onehot_fsm_reg[20]_0\ => p_0_in1_in,
      \FSM_onehot_fsm_reg[20]_1\ => p_1_in2_in,
      Q(0) => \^q\(1),
      QPLL_DRP_GEN3 => \pipe_lane[0].pipe_rate.pipe_rate_i_n_21\,
      QRST_QPLLLOCK(0) => \^qpll_qplllock\,
      RXRATE(0) => rate_rate_0(0),
      RXSYSCLKSEL(0) => rate_sysclksel_0(0),
      SYNC_GEN3 => \^gen3_reg\,
      SYNC_MMCM_LOCK => \^mmcm_i_i_1\,
      cplllock_reg1_reg_0(0) => \^d\(0),
      drp_done_reg1_reg_0(0) => p_103_out,
      gt_rxratedone_0 => gt_rxratedone_0,
      gt_rxresetdone_0 => gt_rxresetdone_0,
      gt_txratedone_0 => gt_txratedone_0,
      gt_txresetdone_0 => gt_txresetdone_0,
      \out\ => rst_cpllreset,
      pclk_sel_reg_0(0) => \^pclk_sel_reg_0\(0),
      pipe_rate_fsm(4 downto 0) => pipe_rate_fsm(4 downto 0),
      pipe_rate_idle => pipe_rate_idle,
      pipe_rate_idle_INST_0_0(0) => rate_idle(1),
      pipe_tx_rate => pipe_tx_rate,
      qpllpd_reg_0(0) => rate_qpllpd(0),
      qpllreset_reg_0(0) => rate_qpllreset(0),
      rate_cpllpd_0 => rate_cpllpd_0,
      rate_cpllreset_0 => rate_cpllreset_0,
      rate_drp_start_0 => rate_drp_start_0,
      rate_drp_x16x20_mode_0 => rate_drp_x16x20_mode_0,
      rate_gen3_1 => rate_gen3_1,
      \rate_out_reg[0]_0\ => \^pclk_sel_reg\,
      rate_rxpmareset_0 => rate_rxpmareset_0,
      rxchbonden_0 => rxchbonden_0,
      txsync_done_reg1_reg_0(0) => p_85_out
    );
\pipe_lane[0].pipe_sync_i\: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_sync
     port map (
      D(0) => p_85_out,
      \FSM_onehot_txsync_fsm.fsm_tx_reg[4]_0\ => \pipe_lane[0].pipe_user_i_n_8\,
      \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0\ => \pipe_lane[0].pipe_user_i_n_10\,
      \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\ => p_0_in1_in,
      \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1\ => p_1_in2_in,
      PIPE_RXELECIDLE(0) => \^pipe_rxelecidle\(0),
      Q(5 downto 0) => \^fsm_onehot_txsync_fsm.fsm_tx_reg[6]\(5 downto 0),
      SYNC_GEN3 => \^gen3_reg\,
      SYNC_MMCM_LOCK => \^mmcm_i_i_1\,
      SYNC_RATE_IDLE => rate_idle(0),
      SYNC_RXCDRLOCK => p_91_out,
      SYNC_RXDLYSRESETDONE => rxdlysresetdone_1,
      SYNC_TXDLYSRESETDONE => txdlysresetdone_1,
      SYNC_TXPHALIGNDONE => txsyncallin,
      SYNC_TXPHINITDONE => \pipe_lane[1].pipe_user_i_n_9\,
      SYNC_TXSYNC_START => SYNC_TXSYNC_START0,
      \out\ => \pipe_lane[0].pipe_sync_i_n_1\,
      p_1_in => p_1_in_0,
      p_1_in0_in => p_1_in0_in,
      pipe_rxphaligndone(1 downto 0) => \^pipe_rxphaligndone\(1 downto 0),
      pipe_sync_fsm_rx(0) => pipe_sync_fsm_rx(0),
      rxphaligndone_s_reg2_reg_0 => rst_cpllreset,
      rxphaligndone_s_reg2_reg_1 => \^pclk_sel_reg\,
      sync_txdlyen_0 => sync_txdlyen_0,
      txphinitdone_reg3_reg_0 => \pipe_lane[0].pipe_sync_i_n_3\,
      \txsync_fsm.txsync_done_reg_0\ => \pipe_lane[0].pipe_user_i_n_9\
    );
\pipe_lane[0].pipe_user_i\: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_user
     port map (
      CLKRSVD(0) => user_oobclk_0,
      D(0) => user_resetdone(0),
      \FSM_onehot_txsync_fsm.fsm_tx_reg[4]\ => \pipe_lane[0].pipe_sync_i_n_3\,
      PIPE_PHYSTATUS(0) => PIPE_PHYSTATUS(0),
      PIPE_RXELECIDLE(0) => \^pipe_rxelecidle\(0),
      Q(0) => \^q\(1),
      SR(0) => p_1_in,
      SYNC_GEN3 => \^gen3_reg\,
      converge_gen3_reg_0 => \pipe_lane[0].pipe_user_i_n_7\,
      \cplllock_reg1_reg[1]\ => \pipe_lane[1].pipe_user_i_n_3\,
      \cplllock_reg1_reg[1]_0\ => \pipe_lane[1].pipe_user_i_n_8\,
      \cplllock_reg1_reg[1]_1\ => \pipe_lane[1].pipe_user_i_n_7\,
      gt_rx_phy_status_q_reg(0) => gt_phystatus_0,
      gt_rxcdrlock_0 => gt_rxcdrlock_0,
      gt_rxresetdone_0 => gt_rxresetdone_0,
      gt_rxvalid_0 => gt_rxvalid_0,
      gt_rxvalid_q => gt_rxvalid_q,
      gt_rxvalid_q_reg => gt_rxvalid_q_reg_2,
      gt_rxvalid_q_reg_0(0) => gt_rxvalid_q_reg_3(0),
      gt_rxvalid_q_reg_1 => \gt_rx_status_q_reg[2]\,
      gt_rxvalid_q_reg_2 => \gt_rx_status_q_reg[0]_0\,
      gt_txresetdone_0 => gt_txresetdone_0,
      \out\ => p_1_in2_in,
      p_1_in => p_1_in_0,
      p_1_in0_in => p_1_in0_in,
      pclk_sel_reg1_reg_0(0) => \^pclk_sel_reg_0\(0),
      pipe_rxstatus(0) => \^pipe_rxstatus\(2),
      pipe_tx0_compliance => pipe_tx0_compliance,
      pipe_tx0_elec_idle => pipe_tx0_elec_idle,
      rate_done_reg1_reg_0(1) => rate_done_0,
      rate_done_reg1_reg_0(0) => rate_idle(0),
      resetovrd_start_reg2_reg_0 => rst_cpllreset,
      resetovrd_start_reg2_reg_1 => \^pclk_sel_reg\,
      rst_idle_reg2_reg_0 => \pipe_lane[0].pipe_user_i_n_2\,
      \rxcdrlock_cnt_reg[2]_0\(0) => p_91_out,
      rxeq_adapt_done_reg1_reg_0 => \pipe_lane[0].pipe_eq.pipe_eq_i_n_0\,
      txcompliance_reg2_reg_0 => p_0_in1_in,
      txcompliance_reg2_reg_1 => \pipe_lane[0].pipe_user_i_n_8\,
      txcompliance_reg2_reg_2 => \pipe_lane[0].pipe_user_i_n_9\,
      txelecidle_reg2_reg_0 => \pipe_lane[0].pipe_user_i_n_10\,
      \txsync_fsm.txsync_done_reg\ => \pipe_lane[0].pipe_sync_i_n_1\
    );
\pipe_lane[1].gt_wrapper_i\: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_gt_wrapper_16
     port map (
      CLK => \^clk\,
      CLKRSVD(0) => user_oobclk_1,
      CPLLRESET0 => CPLLRESET0,
      D(0) => \^d\(1),
      DRPADDR(8 downto 0) => drp_mux_addr_9(8 downto 0),
      DRPDI(15 downto 0) => drp_mux_di_16(15 downto 0),
      PIPE_RXELECIDLE(0) => \^pipe_rxelecidle\(1),
      Q(2 downto 0) => \^fsm_onehot_txsync_fsm.fsm_tx_reg[6]_0\(4 downto 2),
      RXCHBONDO(4 downto 0) => \gt_rxchbondo[1]_0\(4 downto 0),
      RXRATE(0) => rate_rate_3(0),
      RXSYSCLKSEL(0) => rate_sysclksel_2(0),
      TXMAINCURSOR(6 downto 0) => eq_txeq_maincursor_7(6 downto 0),
      TXPOSTCURSOR(4 downto 0) => eq_txeq_postcursor_5(4 downto 0),
      TXPRECURSOR(4 downto 0) => eq_txeq_precursor_5(4 downto 0),
      \cplllock_reg1_reg[1]\ => \pipe_lane[0].pipe_user_i_n_7\,
      \cplllock_reg1_reg[1]_0\ => \^pclk_sel_reg\,
      cpllrst => cpllrst_1,
      drp_mux_en_1 => drp_mux_en_1,
      drp_mux_we_1 => drp_mux_we_1,
      ext_ch_gt_drpdo(15 downto 0) => \^ext_ch_gt_drpdo\(31 downto 16),
      ext_ch_gt_drprdy(0) => \^ext_ch_gt_drprdy\(1),
      gt_cpllpdrefclk => gt_cpllpdrefclk,
      \gt_rx_status_q_reg[0]\ => \gt_rx_status_q_reg[0]\,
      \gt_rx_status_q_reg[2]\ => \gt_rx_status_q_reg[2]\,
      gt_rxcdrlock_1 => gt_rxcdrlock_1,
      gt_rxratedone_1 => gt_rxratedone_1,
      gt_rxresetdone_1 => gt_rxresetdone_1,
      gt_rxvalid_1 => gt_rxvalid_1,
      gt_rxvalid_q_reg(2 downto 0) => gt_rxvalid_q_reg_0(2 downto 0),
      gt_txratedone_1 => gt_txratedone_1,
      gt_txresetdone_1 => gt_txresetdone_1,
      int_qplloutclk_out(0) => \^int_qplloutclk_out\(0),
      int_qplloutrefclk_out(0) => \^int_qplloutrefclk_out\(0),
      pci_exp_rxn(0) => pci_exp_rxn(1),
      pci_exp_rxp(0) => pci_exp_rxp(1),
      pci_exp_txn(0) => pci_exp_txn(1),
      pci_exp_txp(0) => pci_exp_txp(1),
      pipe_dmonitorout(7 downto 0) => pipe_dmonitorout(15 downto 8),
      pipe_eyescandataerror(0) => pipe_eyescandataerror(1),
      pipe_rx1_chanisaligned => pipe_rx1_chanisaligned,
      pipe_rx1_polarity => pipe_rx1_polarity,
      pipe_rxbufstatus(2 downto 0) => pipe_rxbufstatus(5 downto 3),
      pipe_rxcommadet(0) => pipe_rxcommadet(1),
      pipe_rxdisperr(7 downto 0) => pipe_rxdisperr(15 downto 8),
      pipe_rxdlysresetdone(0) => \^pipe_rxdlysresetdone\(1),
      pipe_rxnotintable(7 downto 0) => pipe_rxnotintable(15 downto 8),
      pipe_rxoutclk_out(0) => pipe_rxoutclk_out(1),
      pipe_rxphaligndone(0) => \^pipe_rxphaligndone\(1),
      pipe_rxprbserr(0) => pipe_rxprbserr(1),
      pipe_rxstatus(2 downto 0) => \^pipe_rxstatus\(5 downto 3),
      pipe_tx1_char_is_k(1 downto 0) => pipe_tx1_char_is_k(1 downto 0),
      pipe_tx1_compliance => pipe_tx1_compliance,
      pipe_tx1_data(15 downto 0) => pipe_tx1_data(15 downto 0),
      pipe_tx1_elec_idle => pipe_tx1_elec_idle,
      pipe_tx1_powerdown(1 downto 0) => pipe_tx1_powerdown(1 downto 0),
      pipe_tx_deemph => pipe_tx_deemph,
      pipe_tx_margin(2 downto 0) => pipe_tx_margin(2 downto 0),
      pipe_tx_rcvr_det => pipe_tx_rcvr_det,
      pipe_txdlysresetdone(0) => \^pipe_txdlysresetdone\(1),
      pipe_txinhibit(0) => pipe_txinhibit(1),
      pipe_txphaligndone(0) => \^pipe_txphaligndone\(1),
      pipe_txphinitdone(0) => \^pipe_txphinitdone\(1),
      rate_cpllpd_1 => rate_cpllpd_1,
      rate_rxpmareset_1 => rate_rxpmareset_1,
      rst_gtreset => rst_gtreset,
      rst_userrdy => rst_userrdy,
      rxchbonden_1 => rxchbonden_1,
      sys_clk => sys_clk,
      sys_clk_0(0) => gt_phystatus_1,
      sys_clk_1(15 downto 0) => sys_clk_0(31 downto 16),
      sys_clk_2(1 downto 0) => sys_clk_1(3 downto 2)
    );
\pipe_lane[1].pipe_drp.pipe_drp_i\: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_drp_17
     port map (
      CLK => \^clk\,
      D(0) => p_48_out,
      DRPADDR(8 downto 0) => drp_mux_addr_9(8 downto 0),
      DRPDI(15 downto 0) => drp_mux_di_16(15 downto 0),
      Q(2 downto 0) => \fsm_reg[2]_0\(2 downto 0),
      drp_mux_en_1 => drp_mux_en_1,
      drp_mux_we_1 => drp_mux_we_1,
      ext_ch_gt_drpaddr(8 downto 0) => ext_ch_gt_drpaddr(17 downto 9),
      ext_ch_gt_drpdi(15 downto 0) => ext_ch_gt_drpdi(31 downto 16),
      ext_ch_gt_drpdo(15 downto 0) => \^ext_ch_gt_drpdo\(31 downto 16),
      ext_ch_gt_drpen(0) => ext_ch_gt_drpen(1),
      ext_ch_gt_drprdy(0) => \^ext_ch_gt_drprdy\(1),
      ext_ch_gt_drpwe(0) => ext_ch_gt_drpwe(1),
      gt_ch_drp_rdy(0) => gt_ch_drp_rdy(1),
      \out\ => rst_dclk_reset,
      pipe_tx_rate => pipe_tx_rate,
      rate_drp_start_1 => rate_drp_start_1,
      rate_drp_x16x20_mode_1 => rate_drp_x16x20_mode_1,
      rst_gtreset => rst_gtreset
    );
\pipe_lane[1].pipe_eq.pipe_eq_i\: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_eq_18
     port map (
      TXMAINCURSOR(6 downto 0) => eq_txeq_maincursor_7(6 downto 0),
      TXPOSTCURSOR(4 downto 0) => eq_txeq_postcursor_5(4 downto 0),
      TXPRECURSOR(4 downto 0) => eq_txeq_precursor_5(4 downto 0),
      \fs_reg2_reg[5]\ => \^pclk_sel_reg\,
      \out\ => rst_cpllreset,
      rate_gen3_1 => rate_gen3_1,
      rxeq_adapt_done_reg_0 => \pipe_lane[1].pipe_eq.pipe_eq_i_n_0\
    );
\pipe_lane[1].pipe_rate.pipe_rate_i\: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_rate_19
     port map (
      CPLLRESET0 => CPLLRESET0,
      D(0) => gt_phystatus_1,
      \FSM_onehot_fsm_reg[14]_0\ => \pipe_lane[1].pipe_user_i_n_12\,
      \FSM_onehot_fsm_reg[18]_0\(2) => rate_txsync_start_1,
      \FSM_onehot_fsm_reg[18]_0\(1) => rate_done_1,
      \FSM_onehot_fsm_reg[18]_0\(0) => rate_idle(1),
      \FSM_onehot_fsm_reg[20]_0\ => p_0_in1_in_3,
      \FSM_onehot_fsm_reg[20]_1\ => p_1_in2_in_4,
      Q(0) => \^q\(1),
      QRST_QPLLLOCK(0) => \^qpll_qplllock\,
      RXRATE(0) => rate_rate_3(0),
      RXSYSCLKSEL(0) => rate_sysclksel_2(0),
      SYNC_MMCM_LOCK => \^mmcm_i_i_1\,
      cplllock_reg1_reg_0(0) => \^d\(1),
      cpllrst => cpllrst_1,
      drp_done_reg1_reg_0(0) => p_48_out,
      gt_rxratedone_1 => gt_rxratedone_1,
      gt_rxresetdone_1 => gt_rxresetdone_1,
      gt_txratedone_1 => gt_txratedone_1,
      gt_txresetdone_1 => gt_txresetdone_1,
      \out\ => rst_cpllreset,
      pclk_sel_reg_0(0) => \^pclk_sel_reg_0\(1),
      pipe_rate_fsm(4 downto 0) => pipe_rate_fsm(9 downto 5),
      pipe_tx_rate => pipe_tx_rate,
      qpllpd_reg_0(0) => rate_qpllpd(1),
      qpllreset_reg_0(0) => rate_qpllreset(1),
      rate_cpllpd_1 => rate_cpllpd_1,
      rate_drp_start_1 => rate_drp_start_1,
      rate_drp_x16x20_mode_1 => rate_drp_x16x20_mode_1,
      rate_gen3_1 => rate_gen3_1,
      \rate_out_reg[0]_0\ => \^pclk_sel_reg\,
      rate_rxpmareset_1 => rate_rxpmareset_1,
      rxchbonden_1 => rxchbonden_1,
      txsync_done_reg1_reg_0(0) => p_30_out
    );
\pipe_lane[1].pipe_sync_i\: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_sync_20
     port map (
      D(0) => p_30_out,
      \FSM_onehot_txsync_fsm.fsm_tx_reg[4]_0\ => \pipe_lane[1].pipe_user_i_n_11\,
      \FSM_onehot_txsync_fsm.fsm_tx_reg[5]_0\ => \pipe_lane[1].pipe_user_i_n_12\,
      \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\ => p_1_in2_in_4,
      \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_1\ => p_0_in1_in_3,
      PIPE_RXELECIDLE(0) => \^pipe_rxelecidle\(1),
      Q(5 downto 0) => \^fsm_onehot_txsync_fsm.fsm_tx_reg[6]_0\(5 downto 0),
      SYNC_GEN3 => rate_gen3_1,
      SYNC_MMCM_LOCK => \^mmcm_i_i_1\,
      SYNC_RATE_IDLE => rate_idle(1),
      SYNC_RXCDRLOCK => p_36_out,
      SYNC_RXDLYSRESETDONE => rxdlysresetdone_1,
      SYNC_TXDLYSRESETDONE => txdlysresetdone_1,
      SYNC_TXPHALIGNDONE => txsyncallin,
      SYNC_TXPHINITDONE => \pipe_lane[1].pipe_user_i_n_9\,
      SYNC_TXSYNC_START => SYNC_TXSYNC_START02_out,
      \out\ => \pipe_lane[1].pipe_sync_i_n_1\,
      p_1_in0_in => p_1_in0_in_2,
      pipe_rxphaligndone(1 downto 0) => \^pipe_rxphaligndone\(1 downto 0),
      pipe_sync_fsm_rx(0) => pipe_sync_fsm_rx(1),
      rxphaligndone_s_reg2_reg_0 => rst_cpllreset,
      rxphaligndone_s_reg2_reg_1 => \^pclk_sel_reg\
    );
\pipe_lane[1].pipe_user_i\: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_user_21
     port map (
      CLKRSVD(0) => user_oobclk_1,
      D(0) => user_resetdone(1),
      \FSM_onehot_txsync_fsm.fsm_tx_reg[4]\ => \pipe_lane[1].pipe_sync_i_n_1\,
      PIPE_PHYSTATUS(0) => PIPE_PHYSTATUS(1),
      PIPE_RXELECIDLE(0) => \^pipe_rxelecidle\(1),
      Q(0) => \^q\(1),
      SR(0) => p_1_in,
      SYNC_TXPHALIGNDONE => txsyncallin,
      SYNC_TXPHINITDONE => \pipe_lane[1].pipe_user_i_n_9\,
      \converge_cnt_reg[0]_0\ => \pipe_lane[1].pipe_user_i_n_7\,
      \converge_cnt_reg[11]_0\ => \pipe_lane[1].pipe_user_i_n_8\,
      converge_gen3_reg_0 => \pipe_lane[1].pipe_user_i_n_3\,
      gt_rx_phy_status_q_reg(0) => gt_phystatus_1,
      gt_rxcdrlock_1 => gt_rxcdrlock_1,
      gt_rxresetdone_1 => gt_rxresetdone_1,
      gt_rxvalid_1 => gt_rxvalid_1,
      gt_rxvalid_q_reg => gt_rxvalid_q_reg,
      gt_rxvalid_q_reg_0 => \gt_rx_status_q_reg[0]\,
      gt_txresetdone_1 => gt_txresetdone_1,
      \out\ => p_1_in2_in_4,
      p_1_in0_in => p_1_in0_in_2,
      pclk_sel_reg1_reg_0(0) => \^pclk_sel_reg_0\(1),
      phy_rdy_n_int_reg => \pipe_lane[0].pipe_user_i_n_2\,
      pipe_rxstatus(0) => \^pipe_rxstatus\(5),
      pipe_tx1_compliance => pipe_tx1_compliance,
      pipe_tx1_elec_idle => pipe_tx1_elec_idle,
      pipe_txphaligndone(1 downto 0) => \^pipe_txphaligndone\(1 downto 0),
      pipe_txphinitdone(1 downto 0) => \^pipe_txphinitdone\(1 downto 0),
      rate_done_reg1_reg_0(1) => rate_done_1,
      rate_done_reg1_reg_0(0) => rate_idle(1),
      rate_gen3_1 => rate_gen3_1,
      reg_clock_locked => reg_clock_locked,
      resetovrd_start_reg2_reg_0 => rst_cpllreset,
      resetovrd_start_reg2_reg_1 => \^pclk_sel_reg\,
      rst_idle_reg2_reg_0 => rst_idle_reg2_reg,
      \rxcdrlock_cnt_reg[2]_0\(0) => p_36_out,
      rxeq_adapt_done_reg1_reg_0 => \pipe_lane[1].pipe_eq.pipe_eq_i_n_0\,
      txcompliance_reg2_reg_0 => p_0_in1_in_3,
      txcompliance_reg2_reg_1 => \pipe_lane[1].pipe_user_i_n_11\,
      txelecidle_reg2_reg_0 => \pipe_lane[1].pipe_user_i_n_12\,
      txphinitdone_reg1_reg => p_1_in2_in,
      txphinitdone_reg1_reg_0 => p_0_in1_in
    );
\pipe_reset.pipe_reset_i\: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_reset
     port map (
      CLK => \^clk\,
      CPLLRESET0 => CPLLRESET0_5,
      D(1 downto 0) => user_resetdone(1 downto 0),
      \FSM_onehot_fsm_reg[3]_0\ => SYNC_TXSYNC_START02_out,
      Q(1 downto 0) => \^q\(1 downto 0),
      QRST_IDLE => \^qrst_idle\,
      SYNC_MMCM_LOCK => \^mmcm_i_i_1\,
      SYNC_TXSYNC_START => SYNC_TXSYNC_START0,
      \cfg_wait_cnt_reg[0]_0\ => reset_n_reg2,
      \cplllock_reg1_reg[1]_0\(1 downto 0) => \^d\(1 downto 0),
      cpllrst => cpllrst,
      dclk_rst_reg2_reg_0 => rst_dclk_reset,
      \drp_done_reg1_reg[1]_0\(1) => p_48_out,
      \drp_done_reg1_reg[1]_0\(0) => p_103_out,
      \out\ => rst_cpllreset,
      \phystatus_reg1_reg[1]_0\(1) => gt_phystatus_1,
      \phystatus_reg1_reg[1]_0\(0) => gt_phystatus_0,
      pipe_rst_fsm(3 downto 0) => pipe_rst_fsm(3 downto 0),
      rate_cpllreset_0 => rate_cpllreset_0,
      reset_n_reg2_reg => \pipe_reset.pipe_reset_i_n_3\,
      rst_gtreset => rst_gtreset,
      rst_userrdy => rst_userrdy,
      \rxcdrlock_reg1_reg[1]_0\(1) => p_36_out,
      \rxcdrlock_reg1_reg[1]_0\(0) => p_91_out,
      \rxcdrlock_reg2_reg[1]_0\ => \^pclk_sel_reg\,
      rxusrclk_rst_reg2_reg_0 => p_1_in,
      \txsync_done_reg1_reg[1]_0\(1) => p_30_out,
      \txsync_done_reg1_reg[1]_0\(0) => p_85_out,
      txsync_start_reg1_reg(1) => rate_txsync_start_0,
      txsync_start_reg1_reg(0) => rate_idle(0),
      txsync_start_reg1_reg_0(1) => rate_txsync_start_1,
      txsync_start_reg1_reg_0(0) => rate_idle(1)
    );
pl_phy_lnk_up_q_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => reset_n_reg2_reg_0,
      O => \^sys_rst_n\
    );
\qpll_reset.qpll_reset_i\: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_qpll_reset
     port map (
      Q(1) => \^qrst_idle\,
      Q(0) => qrst_drp_start,
      QPLL_QPLLPD => qpllpd,
      QPLL_QPLLRESET => qrst_qpllreset,
      QRST_CPLLLOCK(1 downto 0) => \^d\(1 downto 0),
      QRST_DRP_DONE(0) => qdrp_done,
      QRST_QPLLLOCK(0) => \^qpll_qplllock\,
      QRST_QPLLPD_IN(1 downto 0) => rate_qpllpd(1 downto 0),
      QRST_QPLLRESET_IN(1 downto 0) => rate_qpllreset(1 downto 0),
      SS(0) => \pipe_reset.pipe_reset_i_n_3\,
      SYNC_MMCM_LOCK => \^mmcm_i_i_1\,
      pipe_qrst_fsm(3 downto 0) => pipe_qrst_fsm(3 downto 0),
      pipe_tx_rate => pipe_tx_rate,
      qpllreset_reg_0 => \^pclk_sel_reg\
    );
reset_n_reg1_reg: unisim.vcomponents.FDCE
     port map (
      C => \^pclk_sel_reg\,
      CE => '1',
      CLR => \^sys_rst_n\,
      D => '1',
      Q => reset_n_reg1
    );
reset_n_reg2_reg: unisim.vcomponents.FDCE
     port map (
      C => \^pclk_sel_reg\,
      CE => '1',
      CLR => \^sys_rst_n\,
      D => reset_n_reg1,
      Q => reset_n_reg2
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_gt_top is
  port (
    pipe_txoutclk_out : out STD_LOGIC;
    pclk_sel_reg : out STD_LOGIC;
    CLK : out STD_LOGIC;
    mmcm_i : out STD_LOGIC;
    SYNC_MMCM_LOCK : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 0 to 0 );
    D : out STD_LOGIC_VECTOR ( 1 downto 0 );
    QPLL_QPLLLOCK : out STD_LOGIC;
    \FSM_onehot_fsm_reg[10]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ext_ch_gt_drprdy : out STD_LOGIC_VECTOR ( 1 downto 0 );
    SYNC_GEN3 : out STD_LOGIC;
    pclk_sel_reg_0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxstatus : out STD_LOGIC_VECTOR ( 5 downto 0 );
    pipe_eyescandataerror : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_txn : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_txp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rx0_chanisaligned : out STD_LOGIC;
    pipe_rxcommadet : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxdlysresetdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxphaligndone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxprbserr : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_txdlysresetdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_txphaligndone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_txphinitdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ext_ch_gt_drpdo : out STD_LOGIC_VECTOR ( 31 downto 0 );
    pipe_rxbufstatus : out STD_LOGIC_VECTOR ( 5 downto 0 );
    pipe_dmonitorout : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_rxdisperr : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_rxnotintable : out STD_LOGIC_VECTOR ( 15 downto 0 );
    int_qplloutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    int_qplloutrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    \FSM_onehot_txsync_fsm.fsm_tx_reg[6]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    pipe_rx1_chanisaligned : out STD_LOGIC;
    \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    sys_rst_n_0 : out STD_LOGIC;
    pipe_rx0_valid_gt : out STD_LOGIC;
    pipe_rx0_elec_idle : out STD_LOGIC;
    pipe_rx0_phy_status : out STD_LOGIC;
    pipe_rx1_valid_gt : out STD_LOGIC;
    pipe_rx1_elec_idle : out STD_LOGIC;
    pipe_rx1_phy_status : out STD_LOGIC;
    \gt_rxdata_q_reg[15]\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \gt_rxdata_q_reg[15]_0\ : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \fsm_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    sys_rst_n : out STD_LOGIC;
    pipe_sync_fsm_rx : out STD_LOGIC_VECTOR ( 1 downto 0 );
    \fsm_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \gt_rx_status_q_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \gt_rx_status_q_reg[2]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    gt_ch_drp_rdy : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rst_fsm : out STD_LOGIC_VECTOR ( 3 downto 0 );
    pipe_rate_fsm : out STD_LOGIC_VECTOR ( 9 downto 0 );
    pipe_rate_idle : out STD_LOGIC;
    pipe_rx0_char_is_k : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rx1_char_is_k : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_qrst_fsm : out STD_LOGIC_VECTOR ( 3 downto 0 );
    pipe_tx0_elec_idle : in STD_LOGIC;
    pipe_tx0_compliance : in STD_LOGIC;
    sys_clk : in STD_LOGIC;
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rx0_polarity : in STD_LOGIC;
    pipe_tx_deemph : in STD_LOGIC;
    pipe_tx_rcvr_det : in STD_LOGIC;
    pipe_txinhibit : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx0_powerdown : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx_margin : in STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_tx0_data : in STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_tx0_char_is_k : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx1_elec_idle : in STD_LOGIC;
    pipe_tx1_compliance : in STD_LOGIC;
    pipe_rx1_polarity : in STD_LOGIC;
    pipe_tx1_powerdown : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx1_data : in STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_tx1_char_is_k : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ext_ch_gt_drpaddr : in STD_LOGIC_VECTOR ( 17 downto 0 );
    pipe_mmcm_rst_n : in STD_LOGIC;
    reset_n_reg2_reg : in STD_LOGIC;
    pipe_tx_rate : in STD_LOGIC;
    int_pclk_sel_slave : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_ltssm_state : in STD_LOGIC_VECTOR ( 5 downto 0 );
    ext_ch_gt_drpen : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ext_ch_gt_drpwe : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ext_ch_gt_drpdi : in STD_LOGIC_VECTOR ( 31 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_gt_top : entity is "spec7_pcie_7x_0_gt_top";
end spec7_pcie_7x_0_spec7_pcie_7x_0_gt_top;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_gt_top is
  signal PIPE_PHYSTATUS : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal PIPE_RXDATA : STD_LOGIC_VECTOR ( 47 downto 0 );
  signal PIPE_RXDATAK : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal PIPE_RXELECIDLE : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_19\ : STD_LOGIC;
  signal \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_20\ : STD_LOGIC;
  signal \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_21\ : STD_LOGIC;
  signal gt_rxvalid_q : STD_LOGIC;
  signal \^pclk_sel_reg\ : STD_LOGIC;
  signal phy_rdy_n : STD_LOGIC;
  signal \^pipe_rx0_valid_gt\ : STD_LOGIC;
  signal \^pipe_rx1_valid_gt\ : STD_LOGIC;
  signal pipe_wrapper_i_n_188 : STD_LOGIC;
  signal pipe_wrapper_i_n_204 : STD_LOGIC;
  signal pipe_wrapper_i_n_206 : STD_LOGIC;
  signal pipe_wrapper_i_n_207 : STD_LOGIC;
  signal pipe_wrapper_i_n_208 : STD_LOGIC;
  signal pipe_wrapper_i_n_209 : STD_LOGIC;
  signal pipe_wrapper_i_n_210 : STD_LOGIC;
  signal pipe_wrapper_i_n_211 : STD_LOGIC;
  signal pipe_wrapper_i_n_212 : STD_LOGIC;
  signal pl_ltssm_state_q : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal reg_clock_locked : STD_LOGIC;
begin
  pclk_sel_reg <= \^pclk_sel_reg\;
  pipe_rx0_valid_gt <= \^pipe_rx0_valid_gt\;
  pipe_rx1_valid_gt <= \^pipe_rx1_valid_gt\;
\gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst\: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_gt_rx_valid_filter_7x
     port map (
      D(15 downto 0) => PIPE_RXDATA(15 downto 0),
      \FSM_onehot_reg_state_eios_det_reg[3]_0\ => \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_20\,
      \FSM_onehot_reg_state_eios_det_reg[5]_0\(0) => \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_19\,
      PIPE_PHYSTATUS(0) => PIPE_PHYSTATUS(0),
      Q(15 downto 0) => \gt_rxdata_q_reg[15]\(15 downto 0),
      SR(0) => phy_rdy_n,
      SYNC_RXELECIDLE => PIPE_RXELECIDLE(0),
      gt_rx_phy_status_q_reg_0 => \^pclk_sel_reg\,
      \gt_rx_status_q_reg[2]_0\(2 downto 0) => \gt_rx_status_q_reg[2]\(2 downto 0),
      \gt_rx_status_q_reg[2]_1\(5 downto 0) => pl_ltssm_state_q(5 downto 0),
      \gt_rx_status_q_reg[2]_2\(2) => pipe_wrapper_i_n_210,
      \gt_rx_status_q_reg[2]_2\(1) => pipe_wrapper_i_n_211,
      \gt_rx_status_q_reg[2]_2\(0) => pipe_wrapper_i_n_212,
      \gt_rxcharisk_q_reg[1]_0\(1 downto 0) => PIPE_RXDATAK(1 downto 0),
      gt_rxvalid_q => gt_rxvalid_q,
      gt_rxvalid_q_reg_0 => \^pipe_rx0_valid_gt\,
      pipe_rx0_char_is_k(1 downto 0) => pipe_rx0_char_is_k(1 downto 0),
      pipe_rx0_elec_idle => pipe_rx0_elec_idle,
      pipe_rx0_phy_status => pipe_rx0_phy_status,
      \pl_ltssm_state_q_reg[5]\ => \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_21\
    );
\gt_rx_valid_filter[1].GT_RX_VALID_FILTER_7x_inst\: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_gt_rx_valid_filter_7x_15
     port map (
      D(15 downto 0) => PIPE_RXDATA(47 downto 32),
      PIPE_PHYSTATUS(0) => PIPE_PHYSTATUS(1),
      Q(15 downto 0) => \gt_rxdata_q_reg[15]_0\(15 downto 0),
      SR(0) => phy_rdy_n,
      SYNC_RXELECIDLE => PIPE_RXELECIDLE(1),
      \gt_rx_status_q_reg[2]_0\(2 downto 0) => \gt_rx_status_q_reg[2]_0\(2 downto 0),
      \gt_rx_status_q_reg[2]_1\ => \^pclk_sel_reg\,
      \gt_rx_status_q_reg[2]_2\(2) => pipe_wrapper_i_n_207,
      \gt_rx_status_q_reg[2]_2\(1) => pipe_wrapper_i_n_208,
      \gt_rx_status_q_reg[2]_2\(0) => pipe_wrapper_i_n_209,
      \gt_rxcharisk_q_reg[1]_0\(1 downto 0) => PIPE_RXDATAK(5 downto 4),
      gt_rxvalid_q_reg_0 => \^pipe_rx1_valid_gt\,
      gt_rxvalid_q_reg_1 => pipe_wrapper_i_n_204,
      gt_rxvalid_q_reg_2 => \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_21\,
      pipe_rx1_char_is_k(1 downto 0) => pipe_rx1_char_is_k(1 downto 0),
      pipe_rx1_elec_idle => pipe_rx1_elec_idle,
      pipe_rx1_phy_status => pipe_rx1_phy_status
    );
pcie_block_i_i_29: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => phy_rdy_n,
      O => sys_rst_n
    );
phy_rdy_n_int_reg: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^pclk_sel_reg\,
      CE => '1',
      D => pipe_wrapper_i_n_206,
      Q => phy_rdy_n,
      R => '0'
    );
pipe_wrapper_i: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_pipe_wrapper
     port map (
      CLK => CLK,
      D(1 downto 0) => D(1 downto 0),
      \FSM_onehot_txsync_fsm.fsm_tx_reg[6]\(5 downto 0) => \FSM_onehot_txsync_fsm.fsm_tx_reg[6]\(5 downto 0),
      \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\(5 downto 0) => \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\(5 downto 0),
      PIPE_PHYSTATUS(1 downto 0) => PIPE_PHYSTATUS(1 downto 0),
      PIPE_RXELECIDLE(1 downto 0) => PIPE_RXELECIDLE(1 downto 0),
      Q(1 downto 0) => \FSM_onehot_fsm_reg[10]\(1 downto 0),
      QPLL_QPLLLOCK => QPLL_QPLLLOCK,
      QRST_IDLE => Q(0),
      ext_ch_gt_drpaddr(17 downto 0) => ext_ch_gt_drpaddr(17 downto 0),
      ext_ch_gt_drpdi(31 downto 0) => ext_ch_gt_drpdi(31 downto 0),
      ext_ch_gt_drpdo(31 downto 0) => ext_ch_gt_drpdo(31 downto 0),
      ext_ch_gt_drpen(1 downto 0) => ext_ch_gt_drpen(1 downto 0),
      ext_ch_gt_drprdy(1 downto 0) => ext_ch_gt_drprdy(1 downto 0),
      ext_ch_gt_drpwe(1 downto 0) => ext_ch_gt_drpwe(1 downto 0),
      \fsm_reg[2]\(2 downto 0) => \fsm_reg[2]\(2 downto 0),
      \fsm_reg[2]_0\(2 downto 0) => \fsm_reg[2]_0\(2 downto 0),
      gen3_reg => SYNC_GEN3,
      gt_ch_drp_rdy(1 downto 0) => gt_ch_drp_rdy(1 downto 0),
      \gt_rx_status_q_reg[0]\ => \^pipe_rx1_valid_gt\,
      \gt_rx_status_q_reg[0]_0\ => \^pipe_rx0_valid_gt\,
      \gt_rx_status_q_reg[2]\ => \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_21\,
      gt_rxvalid_q => gt_rxvalid_q,
      gt_rxvalid_q_reg => pipe_wrapper_i_n_204,
      gt_rxvalid_q_reg_0(2) => pipe_wrapper_i_n_207,
      gt_rxvalid_q_reg_0(1) => pipe_wrapper_i_n_208,
      gt_rxvalid_q_reg_0(0) => pipe_wrapper_i_n_209,
      gt_rxvalid_q_reg_1(2) => pipe_wrapper_i_n_210,
      gt_rxvalid_q_reg_1(1) => pipe_wrapper_i_n_211,
      gt_rxvalid_q_reg_1(0) => pipe_wrapper_i_n_212,
      gt_rxvalid_q_reg_2 => \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_20\,
      gt_rxvalid_q_reg_3(0) => \gt_rx_valid_filter[0].GT_RX_VALID_FILTER_7x_inst_n_19\,
      int_pclk_sel_slave(1 downto 0) => int_pclk_sel_slave(1 downto 0),
      int_qplloutclk_out(0) => int_qplloutclk_out(0),
      int_qplloutrefclk_out(0) => int_qplloutrefclk_out(0),
      mmcm_i => mmcm_i,
      mmcm_i_0 => pipe_wrapper_i_n_188,
      mmcm_i_i_1 => SYNC_MMCM_LOCK,
      pci_exp_rxn(1 downto 0) => pci_exp_rxn(1 downto 0),
      pci_exp_rxp(1 downto 0) => pci_exp_rxp(1 downto 0),
      pci_exp_txn(1 downto 0) => pci_exp_txn(1 downto 0),
      pci_exp_txp(1 downto 0) => pci_exp_txp(1 downto 0),
      pclk_sel_reg => \^pclk_sel_reg\,
      pclk_sel_reg_0(1 downto 0) => pclk_sel_reg_0(1 downto 0),
      pipe_dmonitorout(15 downto 0) => pipe_dmonitorout(15 downto 0),
      pipe_eyescandataerror(1 downto 0) => pipe_eyescandataerror(1 downto 0),
      pipe_mmcm_rst_n => pipe_mmcm_rst_n,
      pipe_qrst_fsm(3 downto 0) => pipe_qrst_fsm(3 downto 0),
      pipe_rate_fsm(9 downto 0) => pipe_rate_fsm(9 downto 0),
      pipe_rate_idle => pipe_rate_idle,
      pipe_rst_fsm(3 downto 0) => pipe_rst_fsm(3 downto 0),
      pipe_rx0_chanisaligned => pipe_rx0_chanisaligned,
      pipe_rx0_polarity => pipe_rx0_polarity,
      pipe_rx1_chanisaligned => pipe_rx1_chanisaligned,
      pipe_rx1_polarity => pipe_rx1_polarity,
      pipe_rxbufstatus(5 downto 0) => pipe_rxbufstatus(5 downto 0),
      pipe_rxcommadet(1 downto 0) => pipe_rxcommadet(1 downto 0),
      pipe_rxdisperr(15 downto 0) => pipe_rxdisperr(15 downto 0),
      pipe_rxdlysresetdone(1 downto 0) => pipe_rxdlysresetdone(1 downto 0),
      pipe_rxnotintable(15 downto 0) => pipe_rxnotintable(15 downto 0),
      pipe_rxoutclk_out(1 downto 0) => pipe_rxoutclk_out(1 downto 0),
      pipe_rxphaligndone(1 downto 0) => pipe_rxphaligndone(1 downto 0),
      pipe_rxprbserr(1 downto 0) => pipe_rxprbserr(1 downto 0),
      pipe_rxstatus(5 downto 0) => pipe_rxstatus(5 downto 0),
      pipe_sync_fsm_rx(1 downto 0) => pipe_sync_fsm_rx(1 downto 0),
      pipe_tx0_char_is_k(1 downto 0) => pipe_tx0_char_is_k(1 downto 0),
      pipe_tx0_compliance => pipe_tx0_compliance,
      pipe_tx0_data(15 downto 0) => pipe_tx0_data(15 downto 0),
      pipe_tx0_elec_idle => pipe_tx0_elec_idle,
      pipe_tx0_powerdown(1 downto 0) => pipe_tx0_powerdown(1 downto 0),
      pipe_tx1_char_is_k(1 downto 0) => pipe_tx1_char_is_k(1 downto 0),
      pipe_tx1_compliance => pipe_tx1_compliance,
      pipe_tx1_data(15 downto 0) => pipe_tx1_data(15 downto 0),
      pipe_tx1_elec_idle => pipe_tx1_elec_idle,
      pipe_tx1_powerdown(1 downto 0) => pipe_tx1_powerdown(1 downto 0),
      pipe_tx_deemph => pipe_tx_deemph,
      pipe_tx_margin(2 downto 0) => pipe_tx_margin(2 downto 0),
      pipe_tx_rate => pipe_tx_rate,
      pipe_tx_rcvr_det => pipe_tx_rcvr_det,
      pipe_txdlysresetdone(1 downto 0) => pipe_txdlysresetdone(1 downto 0),
      pipe_txinhibit(1 downto 0) => pipe_txinhibit(1 downto 0),
      pipe_txoutclk_out => pipe_txoutclk_out,
      pipe_txphaligndone(1 downto 0) => pipe_txphaligndone(1 downto 0),
      pipe_txphinitdone(1 downto 0) => pipe_txphinitdone(1 downto 0),
      reg_clock_locked => reg_clock_locked,
      reset_n_reg2_reg_0 => reset_n_reg2_reg,
      rst_idle_reg2_reg => pipe_wrapper_i_n_206,
      sys_clk => sys_clk,
      sys_clk_0(31 downto 16) => PIPE_RXDATA(47 downto 32),
      sys_clk_0(15 downto 0) => PIPE_RXDATA(15 downto 0),
      sys_clk_1(3 downto 2) => PIPE_RXDATAK(5 downto 4),
      sys_clk_1(1 downto 0) => PIPE_RXDATAK(1 downto 0),
      sys_rst_n => sys_rst_n_0
    );
\pl_ltssm_state_q_reg[0]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^pclk_sel_reg\,
      CE => '1',
      CLR => pipe_wrapper_i_n_188,
      D => pl_ltssm_state(0),
      Q => pl_ltssm_state_q(0)
    );
\pl_ltssm_state_q_reg[1]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^pclk_sel_reg\,
      CE => '1',
      CLR => pipe_wrapper_i_n_188,
      D => pl_ltssm_state(1),
      Q => pl_ltssm_state_q(1)
    );
\pl_ltssm_state_q_reg[2]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^pclk_sel_reg\,
      CE => '1',
      CLR => pipe_wrapper_i_n_188,
      D => pl_ltssm_state(2),
      Q => pl_ltssm_state_q(2)
    );
\pl_ltssm_state_q_reg[3]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^pclk_sel_reg\,
      CE => '1',
      CLR => pipe_wrapper_i_n_188,
      D => pl_ltssm_state(3),
      Q => pl_ltssm_state_q(3)
    );
\pl_ltssm_state_q_reg[4]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^pclk_sel_reg\,
      CE => '1',
      CLR => pipe_wrapper_i_n_188,
      D => pl_ltssm_state(4),
      Q => pl_ltssm_state_q(4)
    );
\pl_ltssm_state_q_reg[5]\: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^pclk_sel_reg\,
      CE => '1',
      CLR => pipe_wrapper_i_n_188,
      D => pl_ltssm_state(5),
      Q => pl_ltssm_state_q(5)
    );
reg_clock_locked_reg: unisim.vcomponents.FDCE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^pclk_sel_reg\,
      CE => '1',
      CLR => pipe_wrapper_i_n_188,
      D => '1',
      Q => reg_clock_locked
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_top_7x is
  port (
    rdata : out STD_LOGIC_VECTOR ( 68 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl\ : out STD_LOGIC_VECTOR ( 67 downto 0 );
    CLK : in STD_LOGIC;
    mim_tx_wen : in STD_LOGIC;
    mim_tx_ren : in STD_LOGIC;
    MIMTXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMTXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    wdata : in STD_LOGIC_VECTOR ( 68 downto 0 );
    mim_rx_wen : in STD_LOGIC;
    mim_rx_ren : in STD_LOGIC;
    MIMRXWADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    MIMRXRADDR : in STD_LOGIC_VECTOR ( 10 downto 0 );
    \ramb_bl.ramb36_dp_bl.ram36_bl_0\ : in STD_LOGIC_VECTOR ( 67 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_top_7x : entity is "spec7_pcie_7x_0_pcie_bram_top_7x";
end spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_top_7x;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_top_7x is
begin
pcie_brams_rx: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_brams_7x
     port map (
      CLK => CLK,
      MIMRXRADDR(10 downto 0) => MIMRXRADDR(10 downto 0),
      MIMRXWADDR(10 downto 0) => MIMRXWADDR(10 downto 0),
      mim_rx_ren => mim_rx_ren,
      mim_rx_wen => mim_rx_wen,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(67 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl\(67 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_0\(67 downto 0) => \ramb_bl.ramb36_dp_bl.ram36_bl_0\(67 downto 0)
    );
pcie_brams_tx: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_brams_7x_0
     port map (
      CLK => CLK,
      MIMTXRADDR(10 downto 0) => MIMTXRADDR(10 downto 0),
      MIMTXWADDR(10 downto 0) => MIMTXWADDR(10 downto 0),
      mim_tx_ren => mim_tx_ren,
      mim_tx_wen => mim_tx_wen,
      rdata(68 downto 0) => rdata(68 downto 0),
      wdata(68 downto 0) => wdata(68 downto 0)
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_7x is
  port (
    user_reset_int_reg : out STD_LOGIC;
    src_in : out STD_LOGIC;
    cfg_mgmt_rd_wr_done : out STD_LOGIC;
    cfg_err_aer_headerlog_set : out STD_LOGIC;
    cfg_err_cpl_rdy : out STD_LOGIC;
    cfg_interrupt_rdy : out STD_LOGIC;
    E : out STD_LOGIC_VECTOR ( 0 to 0 );
    cfg_msg_received : out STD_LOGIC;
    cfg_received_func_lvl_rst : out STD_LOGIC;
    trn_in_packet_reg : out STD_LOGIC;
    trn_reof : out STD_LOGIC;
    trn_rsof : out STD_LOGIC;
    trn_rsrc_dsc : out STD_LOGIC;
    ppm_L1_thrtl_reg : out STD_LOGIC;
    cfg_pcie_link_state : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \xhdl12.xhdl14.xhdl15.reg_to_turnoff_reg\ : out STD_LOGIC;
    cfg_to_turnoff : out STD_LOGIC;
    dsc_detect : out STD_LOGIC;
    rsrc_rdy_filtered6_out : out STD_LOGIC;
    trn_rsrc_dsc_prev0 : out STD_LOGIC;
    tcfg_req_trig : out STD_LOGIC;
    trn_tcfg_req : out STD_LOGIC;
    gt_rxelecidle_q_reg : out STD_LOGIC;
    trn_tbuf_av : out STD_LOGIC_VECTOR ( 5 downto 0 );
    tbuf_av_min_trig : out STD_LOGIC;
    lnk_up_thrtl_reg : out STD_LOGIC;
    trn_tdst_rdy : out STD_LOGIC;
    cfg_aer_ecrc_check_en : out STD_LOGIC;
    cfg_aer_ecrc_gen_en : out STD_LOGIC;
    cfg_aer_rooterr_corr_err_received : out STD_LOGIC;
    cfg_aer_rooterr_corr_err_reporting_en : out STD_LOGIC;
    cfg_aer_rooterr_fatal_err_received : out STD_LOGIC;
    cfg_aer_rooterr_fatal_err_reporting_en : out STD_LOGIC;
    cfg_aer_rooterr_non_fatal_err_received : out STD_LOGIC;
    cfg_aer_rooterr_non_fatal_err_reporting_en : out STD_LOGIC;
    cfg_bridge_serr_en : out STD_LOGIC;
    cfg_command : out STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_dcommand2 : out STD_LOGIC_VECTOR ( 11 downto 0 );
    cfg_dcommand : out STD_LOGIC_VECTOR ( 14 downto 0 );
    cfg_dstatus : out STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_interrupt_msienable : out STD_LOGIC;
    cfg_interrupt_msixenable : out STD_LOGIC;
    cfg_interrupt_msixfm : out STD_LOGIC;
    cfg_lcommand : out STD_LOGIC_VECTOR ( 10 downto 0 );
    cfg_lstatus : out STD_LOGIC_VECTOR ( 9 downto 0 );
    cfg_msg_received_assert_int_a : out STD_LOGIC;
    cfg_msg_received_assert_int_b : out STD_LOGIC;
    cfg_msg_received_assert_int_c : out STD_LOGIC;
    cfg_msg_received_assert_int_d : out STD_LOGIC;
    cfg_msg_received_deassert_int_a : out STD_LOGIC;
    cfg_msg_received_deassert_int_b : out STD_LOGIC;
    cfg_msg_received_deassert_int_c : out STD_LOGIC;
    cfg_msg_received_deassert_int_d : out STD_LOGIC;
    cfg_msg_received_err_cor : out STD_LOGIC;
    cfg_msg_received_err_fatal : out STD_LOGIC;
    cfg_msg_received_err_non_fatal : out STD_LOGIC;
    cfg_msg_received_pm_as_nak : out STD_LOGIC;
    cfg_msg_received_pme_to_ack : out STD_LOGIC;
    cfg_msg_received_pm_pme : out STD_LOGIC;
    cfg_msg_received_setslotpowerlimit : out STD_LOGIC;
    cfg_pmcsr_pme_en : out STD_LOGIC;
    cfg_pmcsr_pme_status : out STD_LOGIC;
    cfg_root_control_pme_int_en : out STD_LOGIC;
    cfg_root_control_syserr_corr_err_en : out STD_LOGIC;
    cfg_root_control_syserr_fatal_err_en : out STD_LOGIC;
    cfg_root_control_syserr_non_fatal_err_en : out STD_LOGIC;
    cfg_slot_control_electromech_il_ctl_pulse : out STD_LOGIC;
    pcie_drp_rdy : out STD_LOGIC;
    pipe_rx0_polarity : out STD_LOGIC;
    pipe_rx1_polarity : out STD_LOGIC;
    pipe_tx0_compliance : out STD_LOGIC;
    pipe_tx0_elec_idle : out STD_LOGIC;
    pipe_tx1_compliance : out STD_LOGIC;
    pipe_tx1_elec_idle : out STD_LOGIC;
    pipe_tx_deemph : out STD_LOGIC;
    pipe_tx_rate : out STD_LOGIC;
    pipe_tx_rcvr_det : out STD_LOGIC;
    pl_directed_change_done : out STD_LOGIC;
    pl_link_gen2_cap : out STD_LOGIC;
    pl_link_partner_gen2_supported : out STD_LOGIC;
    pl_link_upcfg_cap : out STD_LOGIC;
    pl_received_hot_rst : out STD_LOGIC;
    pl_sel_lnk_rate : out STD_LOGIC;
    trn_lnk_up : out STD_LOGIC;
    trn_recrc_err : out STD_LOGIC;
    trn_rerrfwd : out STD_LOGIC;
    tx_err_drop : out STD_LOGIC;
    fc_cpld : out STD_LOGIC_VECTOR ( 11 downto 0 );
    fc_npd : out STD_LOGIC_VECTOR ( 11 downto 0 );
    fc_pd : out STD_LOGIC_VECTOR ( 11 downto 0 );
    trn_rd : out STD_LOGIC_VECTOR ( 63 downto 0 );
    cfg_msg_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pcie_drp_do : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_tx0_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_tx1_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_pmcsr_powerstate : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx0_char_is_k : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx0_powerdown : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx1_char_is_k : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx1_powerdown : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_lane_reversal_mode : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_rx_pm_state : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_sel_lnk_width : out STD_LOGIC_VECTOR ( 1 downto 0 );
    trn_rrem : out STD_LOGIC_VECTOR ( 0 to 0 );
    cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_tx_margin : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pl_initial_link_width : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pl_tx_pm_state : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_mgmt_do : out STD_LOGIC_VECTOR ( 31 downto 0 );
    pl_ltssm_state : out STD_LOGIC_VECTOR ( 5 downto 0 );
    cfg_vc_tcvc_map : out STD_LOGIC_VECTOR ( 6 downto 0 );
    cfg_interrupt_do : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_cplh : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_nph : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_ph : out STD_LOGIC_VECTOR ( 7 downto 0 );
    trn_rbar_hit : out STD_LOGIC_VECTOR ( 6 downto 0 );
    bridge_reset_int : in STD_LOGIC;
    pl_phy_lnk_up : in STD_LOGIC;
    cfg_trn_pending : in STD_LOGIC;
    cfg_mgmt_wr_rw1c_as_rw : in STD_LOGIC;
    cfg_mgmt_wr_readonly : in STD_LOGIC;
    cfg_mgmt_wr_en : in STD_LOGIC;
    cfg_mgmt_rd_en : in STD_LOGIC;
    cfg_err_malformed : in STD_LOGIC;
    cfg_err_cor : in STD_LOGIC;
    cfg_err_ur : in STD_LOGIC;
    cfg_err_ecrc : in STD_LOGIC;
    cfg_err_cpl_timeout : in STD_LOGIC;
    cfg_err_cpl_abort : in STD_LOGIC;
    cfg_err_cpl_unexpect : in STD_LOGIC;
    cfg_err_poisoned : in STD_LOGIC;
    cfg_err_atomic_egress_blocked : in STD_LOGIC;
    cfg_err_mc_blocked : in STD_LOGIC;
    cfg_err_internal_uncor : in STD_LOGIC;
    cfg_err_internal_cor : in STD_LOGIC;
    cfg_err_posted : in STD_LOGIC;
    cfg_err_locked : in STD_LOGIC;
    cfg_err_norecovery : in STD_LOGIC;
    cfg_interrupt : in STD_LOGIC;
    cfg_interrupt_assert : in STD_LOGIC;
    cfg_interrupt_stat : in STD_LOGIC;
    cfg_pm_halt_aspm_l0s : in STD_LOGIC;
    cfg_pm_halt_aspm_l1 : in STD_LOGIC;
    cfg_pm_force_state_en : in STD_LOGIC;
    cfg_pm_wake : in STD_LOGIC;
    trn_in_packet : in STD_LOGIC;
    trn_rdst_rdy : in STD_LOGIC;
    ppm_L1_trig : in STD_LOGIC;
    ppm_L1_thrtl : in STD_LOGIC;
    reg_to_turnoff : in STD_LOGIC;
    trn_rsrc_dsc_d : in STD_LOGIC;
    reg_dsc_detect : in STD_LOGIC;
    reg_tcfg_gnt : in STD_LOGIC;
    lnk_up_thrtl : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    CLK : in STD_LOGIC;
    cfg_pm_turnoff_ok_n : in STD_LOGIC;
    pcie_drp_clk : in STD_LOGIC;
    pcie_drp_en : in STD_LOGIC;
    pcie_drp_we : in STD_LOGIC;
    pipe_clk : in STD_LOGIC;
    pipe_rx0_chanisaligned : in STD_LOGIC;
    pipe_rx0_elec_idle : in STD_LOGIC;
    pipe_rx0_phy_status : in STD_LOGIC;
    pipe_rx0_valid : in STD_LOGIC;
    pipe_rx1_chanisaligned : in STD_LOGIC;
    pipe_rx1_elec_idle : in STD_LOGIC;
    pipe_rx1_phy_status : in STD_LOGIC;
    pipe_rx1_valid : in STD_LOGIC;
    pl_directed_link_auton : in STD_LOGIC;
    pl_directed_link_speed : in STD_LOGIC;
    pl_downstream_deemph_source : in STD_LOGIC;
    pl_transmit_hot_rst : in STD_LOGIC;
    pl_upstream_prefer_deemph : in STD_LOGIC;
    sys_rst_n : in STD_LOGIC;
    rx_np_ok : in STD_LOGIC;
    rx_np_req : in STD_LOGIC;
    trn_tcfg_gnt : in STD_LOGIC;
    cfg_aer_ecrc_check_en_0 : in STD_LOGIC_VECTOR ( 3 downto 0 );
    trn_teof : in STD_LOGIC;
    trn_tsof : in STD_LOGIC;
    trn_tsrc_rdy : in STD_LOGIC;
    cfg_err_aer_headerlog : in STD_LOGIC_VECTOR ( 127 downto 0 );
    trn_td : in STD_LOGIC_VECTOR ( 63 downto 0 );
    pcie_drp_di : in STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_rx0_data : in STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_rx1_data : in STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_pm_force_state : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rx0_char_is_k : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rx1_char_is_k : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_directed_link_change : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_directed_link_width : in STD_LOGIC_VECTOR ( 1 downto 0 );
    trn_trem : in STD_LOGIC_VECTOR ( 0 to 0 );
    cfg_ds_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_rx0_status : in STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_rx1_status : in STD_LOGIC_VECTOR ( 2 downto 0 );
    fc_sel : in STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_mgmt_di : in STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_mgmt_byte_en_n : in STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_err_tlp_cpl_header : in STD_LOGIC_VECTOR ( 47 downto 0 );
    cfg_aer_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_ds_device_number : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_pciecap_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 );
    cfg_ds_bus_number : in STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_interrupt_di : in STD_LOGIC_VECTOR ( 7 downto 0 );
    pcie_drp_addr : in STD_LOGIC_VECTOR ( 8 downto 0 );
    cfg_mgmt_dwaddr : in STD_LOGIC_VECTOR ( 9 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_7x : entity is "spec7_pcie_7x_0_pcie_7x";
end spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_7x;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_7x is
  signal cfg_err_aer_headerlog_set_n : STD_LOGIC;
  signal cfg_err_atomic_egress_blocked_n : STD_LOGIC;
  signal cfg_err_cor_n : STD_LOGIC;
  signal cfg_err_cpl_abort_n : STD_LOGIC;
  signal cfg_err_cpl_rdy_n : STD_LOGIC;
  signal cfg_err_cpl_timeout_n : STD_LOGIC;
  signal cfg_err_cpl_unexpect_n : STD_LOGIC;
  signal cfg_err_ecrc_n : STD_LOGIC;
  signal cfg_err_internal_cor_n : STD_LOGIC;
  signal cfg_err_internal_uncor_n : STD_LOGIC;
  signal cfg_err_locked_n : STD_LOGIC;
  signal cfg_err_malformed_n : STD_LOGIC;
  signal cfg_err_mc_blocked_n : STD_LOGIC;
  signal cfg_err_norecovery_n : STD_LOGIC;
  signal cfg_err_poisoned_n : STD_LOGIC;
  signal cfg_err_posted_n : STD_LOGIC;
  signal cfg_err_ur_n : STD_LOGIC;
  signal cfg_interrupt_assert_n : STD_LOGIC;
  signal cfg_interrupt_n : STD_LOGIC;
  signal cfg_interrupt_rdy_n : STD_LOGIC;
  signal cfg_interrupt_stat_n : STD_LOGIC;
  signal cfg_mgmt_rd_en_n : STD_LOGIC;
  signal cfg_mgmt_rd_wr_done_n : STD_LOGIC;
  signal cfg_mgmt_wr_en_n : STD_LOGIC;
  signal cfg_mgmt_wr_readonly_n : STD_LOGIC;
  signal cfg_mgmt_wr_rw1c_as_rw_n : STD_LOGIC;
  signal \^cfg_msg_received\ : STD_LOGIC;
  signal \^cfg_pcie_link_state\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal cfg_pm_force_state_en_n : STD_LOGIC;
  signal cfg_pm_halt_aspm_l0s_n : STD_LOGIC;
  signal cfg_pm_halt_aspm_l1_n : STD_LOGIC;
  signal cfg_pm_wake_n : STD_LOGIC;
  signal \^cfg_to_turnoff\ : STD_LOGIC;
  signal cfg_trn_pending_n : STD_LOGIC;
  signal mim_rx_raddr : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal mim_rx_rdata_int : STD_LOGIC_VECTOR ( 67 downto 0 );
  signal mim_rx_ren : STD_LOGIC;
  signal mim_rx_waddr : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal mim_rx_wdata : STD_LOGIC_VECTOR ( 67 downto 0 );
  signal mim_rx_wen : STD_LOGIC;
  signal mim_tx_raddr : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal mim_tx_rdata_int : STD_LOGIC_VECTOR ( 68 downto 0 );
  signal mim_tx_ren : STD_LOGIC;
  signal mim_tx_waddr : STD_LOGIC_VECTOR ( 12 downto 0 );
  signal mim_tx_wdata : STD_LOGIC_VECTOR ( 68 downto 0 );
  signal mim_tx_wen : STD_LOGIC;
  signal pcie_block_i_n_100 : STD_LOGIC;
  signal pcie_block_i_n_101 : STD_LOGIC;
  signal pcie_block_i_n_102 : STD_LOGIC;
  signal pcie_block_i_n_103 : STD_LOGIC;
  signal pcie_block_i_n_104 : STD_LOGIC;
  signal pcie_block_i_n_105 : STD_LOGIC;
  signal pcie_block_i_n_106 : STD_LOGIC;
  signal pcie_block_i_n_107 : STD_LOGIC;
  signal pcie_block_i_n_108 : STD_LOGIC;
  signal pcie_block_i_n_1097 : STD_LOGIC;
  signal pcie_block_i_n_1098 : STD_LOGIC;
  signal pcie_block_i_n_1099 : STD_LOGIC;
  signal pcie_block_i_n_1100 : STD_LOGIC;
  signal pcie_block_i_n_1101 : STD_LOGIC;
  signal pcie_block_i_n_1102 : STD_LOGIC;
  signal pcie_block_i_n_1103 : STD_LOGIC;
  signal pcie_block_i_n_1143 : STD_LOGIC;
  signal pcie_block_i_n_140 : STD_LOGIC;
  signal pcie_block_i_n_141 : STD_LOGIC;
  signal pcie_block_i_n_142 : STD_LOGIC;
  signal pcie_block_i_n_143 : STD_LOGIC;
  signal pcie_block_i_n_144 : STD_LOGIC;
  signal pcie_block_i_n_145 : STD_LOGIC;
  signal pcie_block_i_n_146 : STD_LOGIC;
  signal pcie_block_i_n_155 : STD_LOGIC;
  signal pcie_block_i_n_156 : STD_LOGIC;
  signal pcie_block_i_n_157 : STD_LOGIC;
  signal pcie_block_i_n_158 : STD_LOGIC;
  signal pcie_block_i_n_159 : STD_LOGIC;
  signal pcie_block_i_n_160 : STD_LOGIC;
  signal pcie_block_i_n_169 : STD_LOGIC;
  signal pcie_block_i_n_172 : STD_LOGIC;
  signal pcie_block_i_n_173 : STD_LOGIC;
  signal pcie_block_i_n_174 : STD_LOGIC;
  signal pcie_block_i_n_175 : STD_LOGIC;
  signal pcie_block_i_n_176 : STD_LOGIC;
  signal pcie_block_i_n_177 : STD_LOGIC;
  signal pcie_block_i_n_178 : STD_LOGIC;
  signal pcie_block_i_n_179 : STD_LOGIC;
  signal pcie_block_i_n_180 : STD_LOGIC;
  signal pcie_block_i_n_181 : STD_LOGIC;
  signal pcie_block_i_n_182 : STD_LOGIC;
  signal pcie_block_i_n_183 : STD_LOGIC;
  signal pcie_block_i_n_184 : STD_LOGIC;
  signal pcie_block_i_n_185 : STD_LOGIC;
  signal pcie_block_i_n_186 : STD_LOGIC;
  signal pcie_block_i_n_187 : STD_LOGIC;
  signal pcie_block_i_n_188 : STD_LOGIC;
  signal pcie_block_i_n_189 : STD_LOGIC;
  signal pcie_block_i_n_190 : STD_LOGIC;
  signal pcie_block_i_n_191 : STD_LOGIC;
  signal pcie_block_i_n_192 : STD_LOGIC;
  signal pcie_block_i_n_193 : STD_LOGIC;
  signal pcie_block_i_n_194 : STD_LOGIC;
  signal pcie_block_i_n_195 : STD_LOGIC;
  signal pcie_block_i_n_610 : STD_LOGIC;
  signal pcie_block_i_n_611 : STD_LOGIC;
  signal pcie_block_i_n_618 : STD_LOGIC;
  signal pcie_block_i_n_619 : STD_LOGIC;
  signal pcie_block_i_n_687 : STD_LOGIC;
  signal pcie_block_i_n_688 : STD_LOGIC;
  signal pcie_block_i_n_689 : STD_LOGIC;
  signal pcie_block_i_n_690 : STD_LOGIC;
  signal pcie_block_i_n_691 : STD_LOGIC;
  signal pcie_block_i_n_704 : STD_LOGIC;
  signal pcie_block_i_n_705 : STD_LOGIC;
  signal pcie_block_i_n_706 : STD_LOGIC;
  signal pcie_block_i_n_707 : STD_LOGIC;
  signal pcie_block_i_n_708 : STD_LOGIC;
  signal pcie_block_i_n_709 : STD_LOGIC;
  signal pcie_block_i_n_710 : STD_LOGIC;
  signal pcie_block_i_n_711 : STD_LOGIC;
  signal pcie_block_i_n_712 : STD_LOGIC;
  signal pcie_block_i_n_713 : STD_LOGIC;
  signal pcie_block_i_n_714 : STD_LOGIC;
  signal pcie_block_i_n_715 : STD_LOGIC;
  signal pcie_block_i_n_716 : STD_LOGIC;
  signal pcie_block_i_n_717 : STD_LOGIC;
  signal pcie_block_i_n_718 : STD_LOGIC;
  signal pcie_block_i_n_719 : STD_LOGIC;
  signal pcie_block_i_n_72 : STD_LOGIC;
  signal pcie_block_i_n_720 : STD_LOGIC;
  signal pcie_block_i_n_721 : STD_LOGIC;
  signal pcie_block_i_n_722 : STD_LOGIC;
  signal pcie_block_i_n_723 : STD_LOGIC;
  signal pcie_block_i_n_724 : STD_LOGIC;
  signal pcie_block_i_n_725 : STD_LOGIC;
  signal pcie_block_i_n_726 : STD_LOGIC;
  signal pcie_block_i_n_727 : STD_LOGIC;
  signal pcie_block_i_n_728 : STD_LOGIC;
  signal pcie_block_i_n_729 : STD_LOGIC;
  signal pcie_block_i_n_730 : STD_LOGIC;
  signal pcie_block_i_n_731 : STD_LOGIC;
  signal pcie_block_i_n_732 : STD_LOGIC;
  signal pcie_block_i_n_733 : STD_LOGIC;
  signal pcie_block_i_n_734 : STD_LOGIC;
  signal pcie_block_i_n_735 : STD_LOGIC;
  signal pcie_block_i_n_736 : STD_LOGIC;
  signal pcie_block_i_n_737 : STD_LOGIC;
  signal pcie_block_i_n_738 : STD_LOGIC;
  signal pcie_block_i_n_739 : STD_LOGIC;
  signal pcie_block_i_n_740 : STD_LOGIC;
  signal pcie_block_i_n_741 : STD_LOGIC;
  signal pcie_block_i_n_742 : STD_LOGIC;
  signal pcie_block_i_n_743 : STD_LOGIC;
  signal pcie_block_i_n_744 : STD_LOGIC;
  signal pcie_block_i_n_745 : STD_LOGIC;
  signal pcie_block_i_n_746 : STD_LOGIC;
  signal pcie_block_i_n_747 : STD_LOGIC;
  signal pcie_block_i_n_748 : STD_LOGIC;
  signal pcie_block_i_n_749 : STD_LOGIC;
  signal pcie_block_i_n_75 : STD_LOGIC;
  signal pcie_block_i_n_750 : STD_LOGIC;
  signal pcie_block_i_n_751 : STD_LOGIC;
  signal pcie_block_i_n_752 : STD_LOGIC;
  signal pcie_block_i_n_753 : STD_LOGIC;
  signal pcie_block_i_n_754 : STD_LOGIC;
  signal pcie_block_i_n_755 : STD_LOGIC;
  signal pcie_block_i_n_756 : STD_LOGIC;
  signal pcie_block_i_n_757 : STD_LOGIC;
  signal pcie_block_i_n_758 : STD_LOGIC;
  signal pcie_block_i_n_759 : STD_LOGIC;
  signal pcie_block_i_n_76 : STD_LOGIC;
  signal pcie_block_i_n_760 : STD_LOGIC;
  signal pcie_block_i_n_761 : STD_LOGIC;
  signal pcie_block_i_n_762 : STD_LOGIC;
  signal pcie_block_i_n_763 : STD_LOGIC;
  signal pcie_block_i_n_764 : STD_LOGIC;
  signal pcie_block_i_n_765 : STD_LOGIC;
  signal pcie_block_i_n_766 : STD_LOGIC;
  signal pcie_block_i_n_767 : STD_LOGIC;
  signal pcie_block_i_n_768 : STD_LOGIC;
  signal pcie_block_i_n_769 : STD_LOGIC;
  signal pcie_block_i_n_77 : STD_LOGIC;
  signal pcie_block_i_n_770 : STD_LOGIC;
  signal pcie_block_i_n_771 : STD_LOGIC;
  signal pcie_block_i_n_772 : STD_LOGIC;
  signal pcie_block_i_n_773 : STD_LOGIC;
  signal pcie_block_i_n_774 : STD_LOGIC;
  signal pcie_block_i_n_775 : STD_LOGIC;
  signal pcie_block_i_n_776 : STD_LOGIC;
  signal pcie_block_i_n_777 : STD_LOGIC;
  signal pcie_block_i_n_778 : STD_LOGIC;
  signal pcie_block_i_n_779 : STD_LOGIC;
  signal pcie_block_i_n_78 : STD_LOGIC;
  signal pcie_block_i_n_780 : STD_LOGIC;
  signal pcie_block_i_n_781 : STD_LOGIC;
  signal pcie_block_i_n_782 : STD_LOGIC;
  signal pcie_block_i_n_783 : STD_LOGIC;
  signal pcie_block_i_n_784 : STD_LOGIC;
  signal pcie_block_i_n_785 : STD_LOGIC;
  signal pcie_block_i_n_786 : STD_LOGIC;
  signal pcie_block_i_n_787 : STD_LOGIC;
  signal pcie_block_i_n_788 : STD_LOGIC;
  signal pcie_block_i_n_789 : STD_LOGIC;
  signal pcie_block_i_n_790 : STD_LOGIC;
  signal pcie_block_i_n_791 : STD_LOGIC;
  signal pcie_block_i_n_792 : STD_LOGIC;
  signal pcie_block_i_n_793 : STD_LOGIC;
  signal pcie_block_i_n_794 : STD_LOGIC;
  signal pcie_block_i_n_795 : STD_LOGIC;
  signal pcie_block_i_n_796 : STD_LOGIC;
  signal pcie_block_i_n_797 : STD_LOGIC;
  signal pcie_block_i_n_798 : STD_LOGIC;
  signal pcie_block_i_n_799 : STD_LOGIC;
  signal pcie_block_i_n_800 : STD_LOGIC;
  signal pcie_block_i_n_801 : STD_LOGIC;
  signal pcie_block_i_n_802 : STD_LOGIC;
  signal pcie_block_i_n_803 : STD_LOGIC;
  signal pcie_block_i_n_804 : STD_LOGIC;
  signal pcie_block_i_n_805 : STD_LOGIC;
  signal pcie_block_i_n_806 : STD_LOGIC;
  signal pcie_block_i_n_807 : STD_LOGIC;
  signal pcie_block_i_n_808 : STD_LOGIC;
  signal pcie_block_i_n_809 : STD_LOGIC;
  signal pcie_block_i_n_810 : STD_LOGIC;
  signal pcie_block_i_n_811 : STD_LOGIC;
  signal pcie_block_i_n_812 : STD_LOGIC;
  signal pcie_block_i_n_813 : STD_LOGIC;
  signal pcie_block_i_n_814 : STD_LOGIC;
  signal pcie_block_i_n_815 : STD_LOGIC;
  signal pcie_block_i_n_816 : STD_LOGIC;
  signal pcie_block_i_n_817 : STD_LOGIC;
  signal pcie_block_i_n_818 : STD_LOGIC;
  signal pcie_block_i_n_819 : STD_LOGIC;
  signal pcie_block_i_n_820 : STD_LOGIC;
  signal pcie_block_i_n_821 : STD_LOGIC;
  signal pcie_block_i_n_822 : STD_LOGIC;
  signal pcie_block_i_n_823 : STD_LOGIC;
  signal pcie_block_i_n_824 : STD_LOGIC;
  signal pcie_block_i_n_825 : STD_LOGIC;
  signal pcie_block_i_n_826 : STD_LOGIC;
  signal pcie_block_i_n_827 : STD_LOGIC;
  signal pcie_block_i_n_828 : STD_LOGIC;
  signal pcie_block_i_n_829 : STD_LOGIC;
  signal pcie_block_i_n_830 : STD_LOGIC;
  signal pcie_block_i_n_831 : STD_LOGIC;
  signal pcie_block_i_n_832 : STD_LOGIC;
  signal pcie_block_i_n_833 : STD_LOGIC;
  signal pcie_block_i_n_834 : STD_LOGIC;
  signal pcie_block_i_n_835 : STD_LOGIC;
  signal pcie_block_i_n_836 : STD_LOGIC;
  signal pcie_block_i_n_837 : STD_LOGIC;
  signal pcie_block_i_n_838 : STD_LOGIC;
  signal pcie_block_i_n_839 : STD_LOGIC;
  signal pcie_block_i_n_84 : STD_LOGIC;
  signal pcie_block_i_n_840 : STD_LOGIC;
  signal pcie_block_i_n_841 : STD_LOGIC;
  signal pcie_block_i_n_842 : STD_LOGIC;
  signal pcie_block_i_n_843 : STD_LOGIC;
  signal pcie_block_i_n_844 : STD_LOGIC;
  signal pcie_block_i_n_845 : STD_LOGIC;
  signal pcie_block_i_n_846 : STD_LOGIC;
  signal pcie_block_i_n_847 : STD_LOGIC;
  signal pcie_block_i_n_848 : STD_LOGIC;
  signal pcie_block_i_n_849 : STD_LOGIC;
  signal pcie_block_i_n_85 : STD_LOGIC;
  signal pcie_block_i_n_850 : STD_LOGIC;
  signal pcie_block_i_n_851 : STD_LOGIC;
  signal pcie_block_i_n_852 : STD_LOGIC;
  signal pcie_block_i_n_853 : STD_LOGIC;
  signal pcie_block_i_n_854 : STD_LOGIC;
  signal pcie_block_i_n_855 : STD_LOGIC;
  signal pcie_block_i_n_856 : STD_LOGIC;
  signal pcie_block_i_n_857 : STD_LOGIC;
  signal pcie_block_i_n_858 : STD_LOGIC;
  signal pcie_block_i_n_859 : STD_LOGIC;
  signal pcie_block_i_n_86 : STD_LOGIC;
  signal pcie_block_i_n_860 : STD_LOGIC;
  signal pcie_block_i_n_861 : STD_LOGIC;
  signal pcie_block_i_n_862 : STD_LOGIC;
  signal pcie_block_i_n_863 : STD_LOGIC;
  signal pcie_block_i_n_864 : STD_LOGIC;
  signal pcie_block_i_n_865 : STD_LOGIC;
  signal pcie_block_i_n_866 : STD_LOGIC;
  signal pcie_block_i_n_867 : STD_LOGIC;
  signal pcie_block_i_n_868 : STD_LOGIC;
  signal pcie_block_i_n_869 : STD_LOGIC;
  signal pcie_block_i_n_87 : STD_LOGIC;
  signal pcie_block_i_n_870 : STD_LOGIC;
  signal pcie_block_i_n_871 : STD_LOGIC;
  signal pcie_block_i_n_872 : STD_LOGIC;
  signal pcie_block_i_n_873 : STD_LOGIC;
  signal pcie_block_i_n_874 : STD_LOGIC;
  signal pcie_block_i_n_875 : STD_LOGIC;
  signal pcie_block_i_n_876 : STD_LOGIC;
  signal pcie_block_i_n_877 : STD_LOGIC;
  signal pcie_block_i_n_878 : STD_LOGIC;
  signal pcie_block_i_n_879 : STD_LOGIC;
  signal pcie_block_i_n_88 : STD_LOGIC;
  signal pcie_block_i_n_880 : STD_LOGIC;
  signal pcie_block_i_n_881 : STD_LOGIC;
  signal pcie_block_i_n_882 : STD_LOGIC;
  signal pcie_block_i_n_883 : STD_LOGIC;
  signal pcie_block_i_n_884 : STD_LOGIC;
  signal pcie_block_i_n_885 : STD_LOGIC;
  signal pcie_block_i_n_886 : STD_LOGIC;
  signal pcie_block_i_n_887 : STD_LOGIC;
  signal pcie_block_i_n_888 : STD_LOGIC;
  signal pcie_block_i_n_889 : STD_LOGIC;
  signal pcie_block_i_n_89 : STD_LOGIC;
  signal pcie_block_i_n_890 : STD_LOGIC;
  signal pcie_block_i_n_891 : STD_LOGIC;
  signal pcie_block_i_n_892 : STD_LOGIC;
  signal pcie_block_i_n_893 : STD_LOGIC;
  signal pcie_block_i_n_894 : STD_LOGIC;
  signal pcie_block_i_n_895 : STD_LOGIC;
  signal pcie_block_i_n_896 : STD_LOGIC;
  signal pcie_block_i_n_897 : STD_LOGIC;
  signal pcie_block_i_n_898 : STD_LOGIC;
  signal pcie_block_i_n_899 : STD_LOGIC;
  signal pcie_block_i_n_90 : STD_LOGIC;
  signal pcie_block_i_n_900 : STD_LOGIC;
  signal pcie_block_i_n_901 : STD_LOGIC;
  signal pcie_block_i_n_902 : STD_LOGIC;
  signal pcie_block_i_n_903 : STD_LOGIC;
  signal pcie_block_i_n_904 : STD_LOGIC;
  signal pcie_block_i_n_905 : STD_LOGIC;
  signal pcie_block_i_n_906 : STD_LOGIC;
  signal pcie_block_i_n_907 : STD_LOGIC;
  signal pcie_block_i_n_908 : STD_LOGIC;
  signal pcie_block_i_n_909 : STD_LOGIC;
  signal pcie_block_i_n_91 : STD_LOGIC;
  signal pcie_block_i_n_910 : STD_LOGIC;
  signal pcie_block_i_n_911 : STD_LOGIC;
  signal pcie_block_i_n_912 : STD_LOGIC;
  signal pcie_block_i_n_913 : STD_LOGIC;
  signal pcie_block_i_n_914 : STD_LOGIC;
  signal pcie_block_i_n_915 : STD_LOGIC;
  signal pcie_block_i_n_916 : STD_LOGIC;
  signal pcie_block_i_n_917 : STD_LOGIC;
  signal pcie_block_i_n_918 : STD_LOGIC;
  signal pcie_block_i_n_919 : STD_LOGIC;
  signal pcie_block_i_n_92 : STD_LOGIC;
  signal pcie_block_i_n_920 : STD_LOGIC;
  signal pcie_block_i_n_921 : STD_LOGIC;
  signal pcie_block_i_n_922 : STD_LOGIC;
  signal pcie_block_i_n_923 : STD_LOGIC;
  signal pcie_block_i_n_924 : STD_LOGIC;
  signal pcie_block_i_n_925 : STD_LOGIC;
  signal pcie_block_i_n_926 : STD_LOGIC;
  signal pcie_block_i_n_927 : STD_LOGIC;
  signal pcie_block_i_n_928 : STD_LOGIC;
  signal pcie_block_i_n_929 : STD_LOGIC;
  signal pcie_block_i_n_93 : STD_LOGIC;
  signal pcie_block_i_n_930 : STD_LOGIC;
  signal pcie_block_i_n_931 : STD_LOGIC;
  signal pcie_block_i_n_932 : STD_LOGIC;
  signal pcie_block_i_n_933 : STD_LOGIC;
  signal pcie_block_i_n_934 : STD_LOGIC;
  signal pcie_block_i_n_935 : STD_LOGIC;
  signal pcie_block_i_n_936 : STD_LOGIC;
  signal pcie_block_i_n_937 : STD_LOGIC;
  signal pcie_block_i_n_938 : STD_LOGIC;
  signal pcie_block_i_n_939 : STD_LOGIC;
  signal pcie_block_i_n_94 : STD_LOGIC;
  signal pcie_block_i_n_940 : STD_LOGIC;
  signal pcie_block_i_n_941 : STD_LOGIC;
  signal pcie_block_i_n_942 : STD_LOGIC;
  signal pcie_block_i_n_943 : STD_LOGIC;
  signal pcie_block_i_n_944 : STD_LOGIC;
  signal pcie_block_i_n_945 : STD_LOGIC;
  signal pcie_block_i_n_946 : STD_LOGIC;
  signal pcie_block_i_n_947 : STD_LOGIC;
  signal pcie_block_i_n_948 : STD_LOGIC;
  signal pcie_block_i_n_949 : STD_LOGIC;
  signal pcie_block_i_n_95 : STD_LOGIC;
  signal pcie_block_i_n_950 : STD_LOGIC;
  signal pcie_block_i_n_951 : STD_LOGIC;
  signal pcie_block_i_n_952 : STD_LOGIC;
  signal pcie_block_i_n_953 : STD_LOGIC;
  signal pcie_block_i_n_954 : STD_LOGIC;
  signal pcie_block_i_n_955 : STD_LOGIC;
  signal pcie_block_i_n_956 : STD_LOGIC;
  signal pcie_block_i_n_957 : STD_LOGIC;
  signal pcie_block_i_n_958 : STD_LOGIC;
  signal pcie_block_i_n_959 : STD_LOGIC;
  signal pcie_block_i_n_96 : STD_LOGIC;
  signal pcie_block_i_n_98 : STD_LOGIC;
  signal pcie_block_i_n_99 : STD_LOGIC;
  signal pipe_rx2_polarity : STD_LOGIC;
  signal pipe_rx3_polarity : STD_LOGIC;
  signal pipe_rx4_polarity : STD_LOGIC;
  signal pipe_rx5_polarity : STD_LOGIC;
  signal pipe_rx6_polarity : STD_LOGIC;
  signal pipe_rx7_polarity : STD_LOGIC;
  signal pipe_tx2_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx2_compliance : STD_LOGIC;
  signal pipe_tx2_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx2_elec_idle : STD_LOGIC;
  signal pipe_tx2_powerdown : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx3_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx3_compliance : STD_LOGIC;
  signal pipe_tx3_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx3_elec_idle : STD_LOGIC;
  signal pipe_tx3_powerdown : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx4_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx4_compliance : STD_LOGIC;
  signal pipe_tx4_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx4_elec_idle : STD_LOGIC;
  signal pipe_tx4_powerdown : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx5_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx5_compliance : STD_LOGIC;
  signal pipe_tx5_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx5_elec_idle : STD_LOGIC;
  signal pipe_tx5_powerdown : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx6_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx6_compliance : STD_LOGIC;
  signal pipe_tx6_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx6_elec_idle : STD_LOGIC;
  signal pipe_tx6_powerdown : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx7_char_is_k : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx7_compliance : STD_LOGIC;
  signal pipe_tx7_data : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx7_elec_idle : STD_LOGIC;
  signal pipe_tx7_powerdown : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pl_phy_lnk_up_n : STD_LOGIC;
  signal received_func_lvl_rst_n : STD_LOGIC;
  signal \^trn_reof\ : STD_LOGIC;
  signal \^trn_rsof\ : STD_LOGIC;
  signal \^trn_rsrc_dsc\ : STD_LOGIC;
  signal trn_rsrc_rdy : STD_LOGIC;
  signal \^trn_tbuf_av\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \^trn_tcfg_req\ : STD_LOGIC;
  signal \^trn_tdst_rdy\ : STD_LOGIC;
  signal user_rst_n : STD_LOGIC;
  signal NLW_pcie_block_i_TRNRD_UNCONNECTED : STD_LOGIC_VECTOR ( 127 downto 64 );
  signal NLW_pcie_block_i_TRNRREM_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
  signal NLW_pcie_block_i_TRNTDSTRDY_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 1 );
  attribute box_type : string;
  attribute box_type of pcie_block_i : label is "PRIMITIVE";
  attribute SOFT_HLUTNM : string;
  attribute SOFT_HLUTNM of trn_rsrc_dsc_prev_i_1 : label is "soft_lutpair128";
  attribute SOFT_HLUTNM of trn_rsrc_rdy_prev_i_1 : label is "soft_lutpair128";
begin
  cfg_msg_received <= \^cfg_msg_received\;
  cfg_pcie_link_state(2 downto 0) <= \^cfg_pcie_link_state\(2 downto 0);
  cfg_to_turnoff <= \^cfg_to_turnoff\;
  trn_reof <= \^trn_reof\;
  trn_rsof <= \^trn_rsof\;
  trn_rsrc_dsc <= \^trn_rsrc_dsc\;
  trn_tbuf_av(5 downto 0) <= \^trn_tbuf_av\(5 downto 0);
  trn_tcfg_req <= \^trn_tcfg_req\;
  trn_tdst_rdy <= \^trn_tdst_rdy\;
\cfg_bus_number_d[7]_i_2\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \^cfg_msg_received\,
      O => E(0)
    );
cfg_err_aer_headerlog_set_INST_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_aer_headerlog_set_n,
      O => cfg_err_aer_headerlog_set
    );
cfg_err_cpl_rdy_INST_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_cpl_rdy_n,
      O => cfg_err_cpl_rdy
    );
cfg_interrupt_rdy_INST_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_interrupt_rdy_n,
      O => cfg_interrupt_rdy
    );
cfg_mgmt_rd_wr_done_INST_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_mgmt_rd_wr_done_n,
      O => cfg_mgmt_rd_wr_done
    );
cfg_received_func_lvl_rst_INST_0: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => received_func_lvl_rst_n,
      O => cfg_received_func_lvl_rst
    );
lnk_up_thrtl_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"4F"
    )
        port map (
      I0 => \^trn_tdst_rdy\,
      I1 => lnk_up_thrtl,
      I2 => \out\,
      O => lnk_up_thrtl_reg
    );
m_axis_rx_tvalid_xhdl2_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000027000000"
    )
        port map (
      I0 => \^trn_reof\,
      I1 => trn_rdst_rdy,
      I2 => \^trn_rsof\,
      I3 => \^trn_rsrc_dsc\,
      I4 => trn_in_packet,
      I5 => trn_rsrc_dsc_d,
      O => dsc_detect
    );
pcie_block_i: unisim.vcomponents.PCIE_2_1
    generic map(
      AER_BASE_PTR => X"000",
      AER_CAP_ECRC_CHECK_CAPABLE => "FALSE",
      AER_CAP_ECRC_GEN_CAPABLE => "FALSE",
      AER_CAP_ID => X"0001",
      AER_CAP_MULTIHEADER => "FALSE",
      AER_CAP_NEXTPTR => X"000",
      AER_CAP_ON => "FALSE",
      AER_CAP_OPTIONAL_ERR_SUPPORT => X"000000",
      AER_CAP_PERMIT_ROOTERR_UPDATE => "FALSE",
      AER_CAP_VERSION => X"1",
      ALLOW_X8_GEN2 => "FALSE",
      BAR0 => X"FFFF0000",
      BAR1 => X"00000000",
      BAR2 => X"00000000",
      BAR3 => X"00000000",
      BAR4 => X"00000000",
      BAR5 => X"00000000",
      CAPABILITIES_PTR => X"40",
      CARDBUS_CIS_POINTER => X"00000000",
      CFG_ECRC_ERR_CPLSTAT => 0,
      CLASS_CODE => X"058000",
      CMD_INTX_IMPLEMENTED => "TRUE",
      CPL_TIMEOUT_DISABLE_SUPPORTED => "FALSE",
      CPL_TIMEOUT_RANGES_SUPPORTED => X"2",
      CRM_MODULE_RSTS => X"00",
      DEV_CAP2_ARI_FORWARDING_SUPPORTED => "FALSE",
      DEV_CAP2_ATOMICOP32_COMPLETER_SUPPORTED => "FALSE",
      DEV_CAP2_ATOMICOP64_COMPLETER_SUPPORTED => "FALSE",
      DEV_CAP2_ATOMICOP_ROUTING_SUPPORTED => "FALSE",
      DEV_CAP2_CAS128_COMPLETER_SUPPORTED => "FALSE",
      DEV_CAP2_ENDEND_TLP_PREFIX_SUPPORTED => "FALSE",
      DEV_CAP2_EXTENDED_FMT_FIELD_SUPPORTED => "FALSE",
      DEV_CAP2_LTR_MECHANISM_SUPPORTED => "FALSE",
      DEV_CAP2_MAX_ENDEND_TLP_PREFIXES => X"0",
      DEV_CAP2_NO_RO_ENABLED_PRPR_PASSING => "FALSE",
      DEV_CAP2_TPH_COMPLETER_SUPPORTED => X"0",
      DEV_CAP_ENABLE_SLOT_PWR_LIMIT_SCALE => "TRUE",
      DEV_CAP_ENABLE_SLOT_PWR_LIMIT_VALUE => "TRUE",
      DEV_CAP_ENDPOINT_L0S_LATENCY => 0,
      DEV_CAP_ENDPOINT_L1_LATENCY => 7,
      DEV_CAP_EXT_TAG_SUPPORTED => "FALSE",
      DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE => "FALSE",
      DEV_CAP_MAX_PAYLOAD_SUPPORTED => 2,
      DEV_CAP_PHANTOM_FUNCTIONS_SUPPORT => 0,
      DEV_CAP_ROLE_BASED_ERROR => "TRUE",
      DEV_CAP_RSVD_14_12 => 0,
      DEV_CAP_RSVD_17_16 => 0,
      DEV_CAP_RSVD_31_29 => 0,
      DEV_CONTROL_AUX_POWER_SUPPORTED => "FALSE",
      DEV_CONTROL_EXT_TAG_DEFAULT => "FALSE",
      DISABLE_ASPM_L1_TIMER => "FALSE",
      DISABLE_BAR_FILTERING => "FALSE",
      DISABLE_ERR_MSG => "FALSE",
      DISABLE_ID_CHECK => "FALSE",
      DISABLE_LANE_REVERSAL => "TRUE",
      DISABLE_LOCKED_FILTER => "FALSE",
      DISABLE_PPM_FILTER => "FALSE",
      DISABLE_RX_POISONED_RESP => "FALSE",
      DISABLE_RX_TC_FILTER => "FALSE",
      DISABLE_SCRAMBLING => "FALSE",
      DNSTREAM_LINK_NUM => X"00",
      DSN_BASE_PTR => X"100",
      DSN_CAP_ID => X"0003",
      DSN_CAP_NEXTPTR => X"000",
      DSN_CAP_ON => "TRUE",
      DSN_CAP_VERSION => X"1",
      ENABLE_MSG_ROUTE => X"000",
      ENABLE_RX_TD_ECRC_TRIM => "FALSE",
      ENDEND_TLP_PREFIX_FORWARDING_SUPPORTED => "FALSE",
      ENTER_RVRY_EI_L0 => "TRUE",
      EXIT_LOOPBACK_ON_EI => "TRUE",
      EXPANSION_ROM => X"00000000",
      EXT_CFG_CAP_PTR => X"3F",
      EXT_CFG_XP_CAP_PTR => X"3FF",
      HEADER_TYPE => X"00",
      INFER_EI => X"00",
      INTERRUPT_PIN => X"01",
      INTERRUPT_STAT_AUTO => "TRUE",
      IS_SWITCH => "FALSE",
      LAST_CONFIG_DWORD => X"3FF",
      LINK_CAP_ASPM_OPTIONALITY => "FALSE",
      LINK_CAP_ASPM_SUPPORT => 1,
      LINK_CAP_CLOCK_POWER_MANAGEMENT => "FALSE",
      LINK_CAP_DLL_LINK_ACTIVE_REPORTING_CAP => "FALSE",
      LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 => 7,
      LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 => 7,
      LINK_CAP_L0S_EXIT_LATENCY_GEN1 => 7,
      LINK_CAP_L0S_EXIT_LATENCY_GEN2 => 7,
      LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 => 7,
      LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 => 7,
      LINK_CAP_L1_EXIT_LATENCY_GEN1 => 7,
      LINK_CAP_L1_EXIT_LATENCY_GEN2 => 7,
      LINK_CAP_LINK_BANDWIDTH_NOTIFICATION_CAP => "FALSE",
      LINK_CAP_MAX_LINK_SPEED => X"1",
      LINK_CAP_MAX_LINK_WIDTH => X"02",
      LINK_CAP_RSVD_23 => 0,
      LINK_CAP_SURPRISE_DOWN_ERROR_CAPABLE => "FALSE",
      LINK_CONTROL_RCB => 0,
      LINK_CTRL2_DEEMPHASIS => "FALSE",
      LINK_CTRL2_HW_AUTONOMOUS_SPEED_DISABLE => "FALSE",
      LINK_CTRL2_TARGET_LINK_SPEED => X"0",
      LINK_STATUS_SLOT_CLOCK_CONFIG => "TRUE",
      LL_ACK_TIMEOUT => X"0000",
      LL_ACK_TIMEOUT_EN => "FALSE",
      LL_ACK_TIMEOUT_FUNC => 0,
      LL_REPLAY_TIMEOUT => X"0000",
      LL_REPLAY_TIMEOUT_EN => "FALSE",
      LL_REPLAY_TIMEOUT_FUNC => 1,
      LTSSM_MAX_LINK_WIDTH => X"02",
      MPS_FORCE => "FALSE",
      MSIX_BASE_PTR => X"9C",
      MSIX_CAP_ID => X"11",
      MSIX_CAP_NEXTPTR => X"00",
      MSIX_CAP_ON => "FALSE",
      MSIX_CAP_PBA_BIR => 0,
      MSIX_CAP_PBA_OFFSET => X"00000000",
      MSIX_CAP_TABLE_BIR => 0,
      MSIX_CAP_TABLE_OFFSET => X"00000000",
      MSIX_CAP_TABLE_SIZE => X"000",
      MSI_BASE_PTR => X"48",
      MSI_CAP_64_BIT_ADDR_CAPABLE => "TRUE",
      MSI_CAP_ID => X"05",
      MSI_CAP_MULTIMSGCAP => 0,
      MSI_CAP_MULTIMSG_EXTENSION => 0,
      MSI_CAP_NEXTPTR => X"60",
      MSI_CAP_ON => "TRUE",
      MSI_CAP_PER_VECTOR_MASKING_CAPABLE => "FALSE",
      N_FTS_COMCLK_GEN1 => 255,
      N_FTS_COMCLK_GEN2 => 255,
      N_FTS_GEN1 => 255,
      N_FTS_GEN2 => 255,
      PCIE_BASE_PTR => X"60",
      PCIE_CAP_CAPABILITY_ID => X"10",
      PCIE_CAP_CAPABILITY_VERSION => X"2",
      PCIE_CAP_DEVICE_PORT_TYPE => X"0",
      PCIE_CAP_NEXTPTR => X"00",
      PCIE_CAP_ON => "TRUE",
      PCIE_CAP_RSVD_15_14 => 0,
      PCIE_CAP_SLOT_IMPLEMENTED => "FALSE",
      PCIE_REVISION => 2,
      PL_AUTO_CONFIG => 0,
      PL_FAST_TRAIN => "TRUE",
      PM_ASPML0S_TIMEOUT => X"0000",
      PM_ASPML0S_TIMEOUT_EN => "FALSE",
      PM_ASPML0S_TIMEOUT_FUNC => 0,
      PM_ASPM_FASTEXIT => "FALSE",
      PM_BASE_PTR => X"40",
      PM_CAP_AUXCURRENT => 0,
      PM_CAP_D1SUPPORT => "FALSE",
      PM_CAP_D2SUPPORT => "FALSE",
      PM_CAP_DSI => "FALSE",
      PM_CAP_ID => X"01",
      PM_CAP_NEXTPTR => X"48",
      PM_CAP_ON => "TRUE",
      PM_CAP_PMESUPPORT => X"0F",
      PM_CAP_PME_CLOCK => "FALSE",
      PM_CAP_RSVD_04 => 0,
      PM_CAP_VERSION => 3,
      PM_CSR_B2B3 => "FALSE",
      PM_CSR_BPCCEN => "FALSE",
      PM_CSR_NOSOFTRST => "TRUE",
      PM_DATA0 => X"00",
      PM_DATA1 => X"00",
      PM_DATA2 => X"00",
      PM_DATA3 => X"00",
      PM_DATA4 => X"00",
      PM_DATA5 => X"00",
      PM_DATA6 => X"00",
      PM_DATA7 => X"00",
      PM_DATA_SCALE0 => X"0",
      PM_DATA_SCALE1 => X"0",
      PM_DATA_SCALE2 => X"0",
      PM_DATA_SCALE3 => X"0",
      PM_DATA_SCALE4 => X"0",
      PM_DATA_SCALE5 => X"0",
      PM_DATA_SCALE6 => X"0",
      PM_DATA_SCALE7 => X"0",
      PM_MF => "FALSE",
      RBAR_BASE_PTR => X"000",
      RBAR_CAP_CONTROL_ENCODEDBAR0 => X"00",
      RBAR_CAP_CONTROL_ENCODEDBAR1 => X"00",
      RBAR_CAP_CONTROL_ENCODEDBAR2 => X"00",
      RBAR_CAP_CONTROL_ENCODEDBAR3 => X"00",
      RBAR_CAP_CONTROL_ENCODEDBAR4 => X"00",
      RBAR_CAP_CONTROL_ENCODEDBAR5 => X"00",
      RBAR_CAP_ID => X"0015",
      RBAR_CAP_INDEX0 => X"0",
      RBAR_CAP_INDEX1 => X"0",
      RBAR_CAP_INDEX2 => X"0",
      RBAR_CAP_INDEX3 => X"0",
      RBAR_CAP_INDEX4 => X"0",
      RBAR_CAP_INDEX5 => X"0",
      RBAR_CAP_NEXTPTR => X"000",
      RBAR_CAP_ON => "FALSE",
      RBAR_CAP_SUP0 => X"00000001",
      RBAR_CAP_SUP1 => X"00000001",
      RBAR_CAP_SUP2 => X"00000001",
      RBAR_CAP_SUP3 => X"00000001",
      RBAR_CAP_SUP4 => X"00000001",
      RBAR_CAP_SUP5 => X"00000001",
      RBAR_CAP_VERSION => X"1",
      RBAR_NUM => X"0",
      RECRC_CHK => 0,
      RECRC_CHK_TRIM => "FALSE",
      ROOT_CAP_CRS_SW_VISIBILITY => "FALSE",
      RP_AUTO_SPD => X"1",
      RP_AUTO_SPD_LOOPCNT => X"1F",
      SELECT_DLL_IF => "FALSE",
      SIM_VERSION => "1.0",
      SLOT_CAP_ATT_BUTTON_PRESENT => "FALSE",
      SLOT_CAP_ATT_INDICATOR_PRESENT => "FALSE",
      SLOT_CAP_ELEC_INTERLOCK_PRESENT => "FALSE",
      SLOT_CAP_HOTPLUG_CAPABLE => "FALSE",
      SLOT_CAP_HOTPLUG_SURPRISE => "FALSE",
      SLOT_CAP_MRL_SENSOR_PRESENT => "FALSE",
      SLOT_CAP_NO_CMD_COMPLETED_SUPPORT => "FALSE",
      SLOT_CAP_PHYSICAL_SLOT_NUM => X"0000",
      SLOT_CAP_POWER_CONTROLLER_PRESENT => "FALSE",
      SLOT_CAP_POWER_INDICATOR_PRESENT => "FALSE",
      SLOT_CAP_SLOT_POWER_LIMIT_SCALE => 0,
      SLOT_CAP_SLOT_POWER_LIMIT_VALUE => X"00",
      SPARE_BIT0 => 0,
      SPARE_BIT1 => 0,
      SPARE_BIT2 => 0,
      SPARE_BIT3 => 0,
      SPARE_BIT4 => 0,
      SPARE_BIT5 => 0,
      SPARE_BIT6 => 0,
      SPARE_BIT7 => 0,
      SPARE_BIT8 => 0,
      SPARE_BYTE0 => X"00",
      SPARE_BYTE1 => X"00",
      SPARE_BYTE2 => X"00",
      SPARE_BYTE3 => X"00",
      SPARE_WORD0 => X"00000000",
      SPARE_WORD1 => X"00000000",
      SPARE_WORD2 => X"00000000",
      SPARE_WORD3 => X"00000000",
      SSL_MESSAGE_AUTO => "FALSE",
      TECRC_EP_INV => "FALSE",
      TL_RBYPASS => "FALSE",
      TL_RX_RAM_RADDR_LATENCY => 0,
      TL_RX_RAM_RDATA_LATENCY => 2,
      TL_RX_RAM_WRITE_LATENCY => 0,
      TL_TFC_DISABLE => "FALSE",
      TL_TX_CHECKS_DISABLE => "FALSE",
      TL_TX_RAM_RADDR_LATENCY => 0,
      TL_TX_RAM_RDATA_LATENCY => 2,
      TL_TX_RAM_WRITE_LATENCY => 0,
      TRN_DW => "FALSE",
      TRN_NP_FC => "TRUE",
      UPCONFIG_CAPABLE => "TRUE",
      UPSTREAM_FACING => "TRUE",
      UR_ATOMIC => "FALSE",
      UR_CFG1 => "TRUE",
      UR_INV_REQ => "TRUE",
      UR_PRS_RESPONSE => "TRUE",
      USER_CLK2_DIV2 => "FALSE",
      USER_CLK_FREQ => 1,
      USE_RID_PINS => "FALSE",
      VC0_CPL_INFINITE => "TRUE",
      VC0_RX_RAM_LIMIT => X"07FF",
      VC0_TOTAL_CREDITS_CD => 461,
      VC0_TOTAL_CREDITS_CH => 36,
      VC0_TOTAL_CREDITS_NPD => 24,
      VC0_TOTAL_CREDITS_NPH => 12,
      VC0_TOTAL_CREDITS_PD => 437,
      VC0_TOTAL_CREDITS_PH => 32,
      VC0_TX_LASTPACKET => 29,
      VC_BASE_PTR => X"000",
      VC_CAP_ID => X"0002",
      VC_CAP_NEXTPTR => X"000",
      VC_CAP_ON => "FALSE",
      VC_CAP_REJECT_SNOOP_TRANSACTIONS => "FALSE",
      VC_CAP_VERSION => X"1",
      VSEC_BASE_PTR => X"000",
      VSEC_CAP_HDR_ID => X"1234",
      VSEC_CAP_HDR_LENGTH => X"018",
      VSEC_CAP_HDR_REVISION => X"1",
      VSEC_CAP_ID => X"000B",
      VSEC_CAP_IS_LINK_VISIBLE => "TRUE",
      VSEC_CAP_NEXTPTR => X"000",
      VSEC_CAP_ON => "FALSE",
      VSEC_CAP_VERSION => X"1"
    )
        port map (
      CFGAERECRCCHECKEN => cfg_aer_ecrc_check_en,
      CFGAERECRCGENEN => cfg_aer_ecrc_gen_en,
      CFGAERINTERRUPTMSGNUM(4 downto 0) => cfg_aer_interrupt_msgnum(4 downto 0),
      CFGAERROOTERRCORRERRRECEIVED => cfg_aer_rooterr_corr_err_received,
      CFGAERROOTERRCORRERRREPORTINGEN => cfg_aer_rooterr_corr_err_reporting_en,
      CFGAERROOTERRFATALERRRECEIVED => cfg_aer_rooterr_fatal_err_received,
      CFGAERROOTERRFATALERRREPORTINGEN => cfg_aer_rooterr_fatal_err_reporting_en,
      CFGAERROOTERRNONFATALERRRECEIVED => cfg_aer_rooterr_non_fatal_err_received,
      CFGAERROOTERRNONFATALERRREPORTINGEN => cfg_aer_rooterr_non_fatal_err_reporting_en,
      CFGBRIDGESERREN => cfg_bridge_serr_en,
      CFGCOMMANDBUSMASTERENABLE => cfg_command(2),
      CFGCOMMANDINTERRUPTDISABLE => cfg_command(4),
      CFGCOMMANDIOENABLE => cfg_command(0),
      CFGCOMMANDMEMENABLE => cfg_command(1),
      CFGCOMMANDSERREN => cfg_command(3),
      CFGDEVCONTROL2ARIFORWARDEN => cfg_dcommand2(5),
      CFGDEVCONTROL2ATOMICEGRESSBLOCK => cfg_dcommand2(7),
      CFGDEVCONTROL2ATOMICREQUESTEREN => cfg_dcommand2(6),
      CFGDEVCONTROL2CPLTIMEOUTDIS => cfg_dcommand2(4),
      CFGDEVCONTROL2CPLTIMEOUTVAL(3 downto 0) => cfg_dcommand2(3 downto 0),
      CFGDEVCONTROL2IDOCPLEN => cfg_dcommand2(9),
      CFGDEVCONTROL2IDOREQEN => cfg_dcommand2(8),
      CFGDEVCONTROL2LTREN => cfg_dcommand2(10),
      CFGDEVCONTROL2TLPPREFIXBLOCK => cfg_dcommand2(11),
      CFGDEVCONTROLAUXPOWEREN => cfg_dcommand(10),
      CFGDEVCONTROLCORRERRREPORTINGEN => cfg_dcommand(0),
      CFGDEVCONTROLENABLERO => cfg_dcommand(4),
      CFGDEVCONTROLEXTTAGEN => cfg_dcommand(8),
      CFGDEVCONTROLFATALERRREPORTINGEN => cfg_dcommand(2),
      CFGDEVCONTROLMAXPAYLOAD(2 downto 0) => cfg_dcommand(7 downto 5),
      CFGDEVCONTROLMAXREADREQ(2 downto 0) => cfg_dcommand(14 downto 12),
      CFGDEVCONTROLNONFATALREPORTINGEN => cfg_dcommand(1),
      CFGDEVCONTROLNOSNOOPEN => cfg_dcommand(11),
      CFGDEVCONTROLPHANTOMEN => cfg_dcommand(9),
      CFGDEVCONTROLURERRREPORTINGEN => cfg_dcommand(3),
      CFGDEVID(15 downto 0) => B"0111000000010010",
      CFGDEVSTATUSCORRERRDETECTED => cfg_dstatus(0),
      CFGDEVSTATUSFATALERRDETECTED => cfg_dstatus(2),
      CFGDEVSTATUSNONFATALERRDETECTED => cfg_dstatus(1),
      CFGDEVSTATUSURDETECTED => cfg_dstatus(3),
      CFGDSBUSNUMBER(7 downto 0) => cfg_ds_bus_number(7 downto 0),
      CFGDSDEVICENUMBER(4 downto 0) => cfg_ds_device_number(4 downto 0),
      CFGDSFUNCTIONNUMBER(2 downto 0) => cfg_ds_function_number(2 downto 0),
      CFGDSN(63 downto 0) => cfg_dsn(63 downto 0),
      CFGERRACSN => '1',
      CFGERRAERHEADERLOG(127 downto 0) => cfg_err_aer_headerlog(127 downto 0),
      CFGERRAERHEADERLOGSETN => cfg_err_aer_headerlog_set_n,
      CFGERRATOMICEGRESSBLOCKEDN => cfg_err_atomic_egress_blocked_n,
      CFGERRCORN => cfg_err_cor_n,
      CFGERRCPLABORTN => cfg_err_cpl_abort_n,
      CFGERRCPLRDYN => cfg_err_cpl_rdy_n,
      CFGERRCPLTIMEOUTN => cfg_err_cpl_timeout_n,
      CFGERRCPLUNEXPECTN => cfg_err_cpl_unexpect_n,
      CFGERRECRCN => cfg_err_ecrc_n,
      CFGERRINTERNALCORN => cfg_err_internal_cor_n,
      CFGERRINTERNALUNCORN => cfg_err_internal_uncor_n,
      CFGERRLOCKEDN => cfg_err_locked_n,
      CFGERRMALFORMEDN => cfg_err_malformed_n,
      CFGERRMCBLOCKEDN => cfg_err_mc_blocked_n,
      CFGERRNORECOVERYN => cfg_err_norecovery_n,
      CFGERRPOISONEDN => cfg_err_poisoned_n,
      CFGERRPOSTEDN => cfg_err_posted_n,
      CFGERRTLPCPLHEADER(47 downto 0) => cfg_err_tlp_cpl_header(47 downto 0),
      CFGERRURN => cfg_err_ur_n,
      CFGFORCECOMMONCLOCKOFF => '0',
      CFGFORCEEXTENDEDSYNCON => '0',
      CFGFORCEMPS(2 downto 0) => B"000",
      CFGINTERRUPTASSERTN => cfg_interrupt_assert_n,
      CFGINTERRUPTDI(7 downto 0) => cfg_interrupt_di(7 downto 0),
      CFGINTERRUPTDO(7 downto 0) => cfg_interrupt_do(7 downto 0),
      CFGINTERRUPTMMENABLE(2 downto 0) => cfg_interrupt_mmenable(2 downto 0),
      CFGINTERRUPTMSIENABLE => cfg_interrupt_msienable,
      CFGINTERRUPTMSIXENABLE => cfg_interrupt_msixenable,
      CFGINTERRUPTMSIXFM => cfg_interrupt_msixfm,
      CFGINTERRUPTN => cfg_interrupt_n,
      CFGINTERRUPTRDYN => cfg_interrupt_rdy_n,
      CFGINTERRUPTSTATN => cfg_interrupt_stat_n,
      CFGLINKCONTROLASPMCONTROL(1 downto 0) => cfg_lcommand(1 downto 0),
      CFGLINKCONTROLAUTOBANDWIDTHINTEN => cfg_lcommand(10),
      CFGLINKCONTROLBANDWIDTHINTEN => cfg_lcommand(9),
      CFGLINKCONTROLCLOCKPMEN => cfg_lcommand(7),
      CFGLINKCONTROLCOMMONCLOCK => cfg_lcommand(5),
      CFGLINKCONTROLEXTENDEDSYNC => cfg_lcommand(6),
      CFGLINKCONTROLHWAUTOWIDTHDIS => cfg_lcommand(8),
      CFGLINKCONTROLLINKDISABLE => cfg_lcommand(3),
      CFGLINKCONTROLRCB => cfg_lcommand(2),
      CFGLINKCONTROLRETRAINLINK => cfg_lcommand(4),
      CFGLINKSTATUSAUTOBANDWIDTHSTATUS => cfg_lstatus(9),
      CFGLINKSTATUSBANDWIDTHSTATUS => cfg_lstatus(8),
      CFGLINKSTATUSCURRENTSPEED(1 downto 0) => cfg_lstatus(1 downto 0),
      CFGLINKSTATUSDLLACTIVE => cfg_lstatus(7),
      CFGLINKSTATUSLINKTRAINING => cfg_lstatus(6),
      CFGLINKSTATUSNEGOTIATEDWIDTH(3 downto 0) => cfg_lstatus(5 downto 2),
      CFGMGMTBYTEENN(3 downto 0) => cfg_mgmt_byte_en_n(3 downto 0),
      CFGMGMTDI(31 downto 0) => cfg_mgmt_di(31 downto 0),
      CFGMGMTDO(31 downto 0) => cfg_mgmt_do(31 downto 0),
      CFGMGMTDWADDR(9 downto 0) => cfg_mgmt_dwaddr(9 downto 0),
      CFGMGMTRDENN => cfg_mgmt_rd_en_n,
      CFGMGMTRDWRDONEN => cfg_mgmt_rd_wr_done_n,
      CFGMGMTWRENN => cfg_mgmt_wr_en_n,
      CFGMGMTWRREADONLYN => cfg_mgmt_wr_readonly_n,
      CFGMGMTWRRW1CASRWN => cfg_mgmt_wr_rw1c_as_rw_n,
      CFGMSGDATA(15 downto 0) => cfg_msg_data(15 downto 0),
      CFGMSGRECEIVED => \^cfg_msg_received\,
      CFGMSGRECEIVEDASSERTINTA => cfg_msg_received_assert_int_a,
      CFGMSGRECEIVEDASSERTINTB => cfg_msg_received_assert_int_b,
      CFGMSGRECEIVEDASSERTINTC => cfg_msg_received_assert_int_c,
      CFGMSGRECEIVEDASSERTINTD => cfg_msg_received_assert_int_d,
      CFGMSGRECEIVEDDEASSERTINTA => cfg_msg_received_deassert_int_a,
      CFGMSGRECEIVEDDEASSERTINTB => cfg_msg_received_deassert_int_b,
      CFGMSGRECEIVEDDEASSERTINTC => cfg_msg_received_deassert_int_c,
      CFGMSGRECEIVEDDEASSERTINTD => cfg_msg_received_deassert_int_d,
      CFGMSGRECEIVEDERRCOR => cfg_msg_received_err_cor,
      CFGMSGRECEIVEDERRFATAL => cfg_msg_received_err_fatal,
      CFGMSGRECEIVEDERRNONFATAL => cfg_msg_received_err_non_fatal,
      CFGMSGRECEIVEDPMASNAK => cfg_msg_received_pm_as_nak,
      CFGMSGRECEIVEDPMETO => \^cfg_to_turnoff\,
      CFGMSGRECEIVEDPMETOACK => cfg_msg_received_pme_to_ack,
      CFGMSGRECEIVEDPMPME => cfg_msg_received_pm_pme,
      CFGMSGRECEIVEDSETSLOTPOWERLIMIT => cfg_msg_received_setslotpowerlimit,
      CFGMSGRECEIVEDUNLOCK => pcie_block_i_n_72,
      CFGPCIECAPINTERRUPTMSGNUM(4 downto 0) => cfg_pciecap_interrupt_msgnum(4 downto 0),
      CFGPCIELINKSTATE(2 downto 0) => \^cfg_pcie_link_state\(2 downto 0),
      CFGPMCSRPMEEN => cfg_pmcsr_pme_en,
      CFGPMCSRPMESTATUS => cfg_pmcsr_pme_status,
      CFGPMCSRPOWERSTATE(1 downto 0) => cfg_pmcsr_powerstate(1 downto 0),
      CFGPMFORCESTATE(1 downto 0) => cfg_pm_force_state(1 downto 0),
      CFGPMFORCESTATEENN => cfg_pm_force_state_en_n,
      CFGPMHALTASPML0SN => cfg_pm_halt_aspm_l0s_n,
      CFGPMHALTASPML1N => cfg_pm_halt_aspm_l1_n,
      CFGPMRCVASREQL1N => pcie_block_i_n_75,
      CFGPMRCVENTERL1N => pcie_block_i_n_76,
      CFGPMRCVENTERL23N => pcie_block_i_n_77,
      CFGPMRCVREQACKN => pcie_block_i_n_78,
      CFGPMSENDPMETON => '1',
      CFGPMTURNOFFOKN => cfg_pm_turnoff_ok_n,
      CFGPMWAKEN => cfg_pm_wake_n,
      CFGPORTNUMBER(7 downto 0) => B"00000000",
      CFGREVID(7 downto 0) => B"00000000",
      CFGROOTCONTROLPMEINTEN => cfg_root_control_pme_int_en,
      CFGROOTCONTROLSYSERRCORRERREN => cfg_root_control_syserr_corr_err_en,
      CFGROOTCONTROLSYSERRFATALERREN => cfg_root_control_syserr_fatal_err_en,
      CFGROOTCONTROLSYSERRNONFATALERREN => cfg_root_control_syserr_non_fatal_err_en,
      CFGSLOTCONTROLELECTROMECHILCTLPULSE => cfg_slot_control_electromech_il_ctl_pulse,
      CFGSUBSYSID(15 downto 0) => B"0000000000000111",
      CFGSUBSYSVENDID(15 downto 0) => B"0001000011101110",
      CFGTRANSACTION => pcie_block_i_n_84,
      CFGTRANSACTIONADDR(6) => pcie_block_i_n_1097,
      CFGTRANSACTIONADDR(5) => pcie_block_i_n_1098,
      CFGTRANSACTIONADDR(4) => pcie_block_i_n_1099,
      CFGTRANSACTIONADDR(3) => pcie_block_i_n_1100,
      CFGTRANSACTIONADDR(2) => pcie_block_i_n_1101,
      CFGTRANSACTIONADDR(1) => pcie_block_i_n_1102,
      CFGTRANSACTIONADDR(0) => pcie_block_i_n_1103,
      CFGTRANSACTIONTYPE => pcie_block_i_n_85,
      CFGTRNPENDINGN => cfg_trn_pending_n,
      CFGVCTCVCMAP(6 downto 0) => cfg_vc_tcvc_map(6 downto 0),
      CFGVENDID(15 downto 0) => B"0001000011101110",
      CMRSTN => '1',
      CMSTICKYRSTN => '1',
      DBGMODE(1 downto 0) => B"00",
      DBGSCLRA => pcie_block_i_n_86,
      DBGSCLRB => pcie_block_i_n_87,
      DBGSCLRC => pcie_block_i_n_88,
      DBGSCLRD => pcie_block_i_n_89,
      DBGSCLRE => pcie_block_i_n_90,
      DBGSCLRF => pcie_block_i_n_91,
      DBGSCLRG => pcie_block_i_n_92,
      DBGSCLRH => pcie_block_i_n_93,
      DBGSCLRI => pcie_block_i_n_94,
      DBGSCLRJ => pcie_block_i_n_95,
      DBGSCLRK => pcie_block_i_n_96,
      DBGSUBMODE => '0',
      DBGVECA(63) => pcie_block_i_n_704,
      DBGVECA(62) => pcie_block_i_n_705,
      DBGVECA(61) => pcie_block_i_n_706,
      DBGVECA(60) => pcie_block_i_n_707,
      DBGVECA(59) => pcie_block_i_n_708,
      DBGVECA(58) => pcie_block_i_n_709,
      DBGVECA(57) => pcie_block_i_n_710,
      DBGVECA(56) => pcie_block_i_n_711,
      DBGVECA(55) => pcie_block_i_n_712,
      DBGVECA(54) => pcie_block_i_n_713,
      DBGVECA(53) => pcie_block_i_n_714,
      DBGVECA(52) => pcie_block_i_n_715,
      DBGVECA(51) => pcie_block_i_n_716,
      DBGVECA(50) => pcie_block_i_n_717,
      DBGVECA(49) => pcie_block_i_n_718,
      DBGVECA(48) => pcie_block_i_n_719,
      DBGVECA(47) => pcie_block_i_n_720,
      DBGVECA(46) => pcie_block_i_n_721,
      DBGVECA(45) => pcie_block_i_n_722,
      DBGVECA(44) => pcie_block_i_n_723,
      DBGVECA(43) => pcie_block_i_n_724,
      DBGVECA(42) => pcie_block_i_n_725,
      DBGVECA(41) => pcie_block_i_n_726,
      DBGVECA(40) => pcie_block_i_n_727,
      DBGVECA(39) => pcie_block_i_n_728,
      DBGVECA(38) => pcie_block_i_n_729,
      DBGVECA(37) => pcie_block_i_n_730,
      DBGVECA(36) => pcie_block_i_n_731,
      DBGVECA(35) => pcie_block_i_n_732,
      DBGVECA(34) => pcie_block_i_n_733,
      DBGVECA(33) => pcie_block_i_n_734,
      DBGVECA(32) => pcie_block_i_n_735,
      DBGVECA(31) => pcie_block_i_n_736,
      DBGVECA(30) => pcie_block_i_n_737,
      DBGVECA(29) => pcie_block_i_n_738,
      DBGVECA(28) => pcie_block_i_n_739,
      DBGVECA(27) => pcie_block_i_n_740,
      DBGVECA(26) => pcie_block_i_n_741,
      DBGVECA(25) => pcie_block_i_n_742,
      DBGVECA(24) => pcie_block_i_n_743,
      DBGVECA(23) => pcie_block_i_n_744,
      DBGVECA(22) => pcie_block_i_n_745,
      DBGVECA(21) => pcie_block_i_n_746,
      DBGVECA(20) => pcie_block_i_n_747,
      DBGVECA(19) => pcie_block_i_n_748,
      DBGVECA(18) => pcie_block_i_n_749,
      DBGVECA(17) => pcie_block_i_n_750,
      DBGVECA(16) => pcie_block_i_n_751,
      DBGVECA(15) => pcie_block_i_n_752,
      DBGVECA(14) => pcie_block_i_n_753,
      DBGVECA(13) => pcie_block_i_n_754,
      DBGVECA(12) => pcie_block_i_n_755,
      DBGVECA(11) => pcie_block_i_n_756,
      DBGVECA(10) => pcie_block_i_n_757,
      DBGVECA(9) => pcie_block_i_n_758,
      DBGVECA(8) => pcie_block_i_n_759,
      DBGVECA(7) => pcie_block_i_n_760,
      DBGVECA(6) => pcie_block_i_n_761,
      DBGVECA(5) => pcie_block_i_n_762,
      DBGVECA(4) => pcie_block_i_n_763,
      DBGVECA(3) => pcie_block_i_n_764,
      DBGVECA(2) => pcie_block_i_n_765,
      DBGVECA(1) => pcie_block_i_n_766,
      DBGVECA(0) => pcie_block_i_n_767,
      DBGVECB(63) => pcie_block_i_n_768,
      DBGVECB(62) => pcie_block_i_n_769,
      DBGVECB(61) => pcie_block_i_n_770,
      DBGVECB(60) => pcie_block_i_n_771,
      DBGVECB(59) => pcie_block_i_n_772,
      DBGVECB(58) => pcie_block_i_n_773,
      DBGVECB(57) => pcie_block_i_n_774,
      DBGVECB(56) => pcie_block_i_n_775,
      DBGVECB(55) => pcie_block_i_n_776,
      DBGVECB(54) => pcie_block_i_n_777,
      DBGVECB(53) => pcie_block_i_n_778,
      DBGVECB(52) => pcie_block_i_n_779,
      DBGVECB(51) => pcie_block_i_n_780,
      DBGVECB(50) => pcie_block_i_n_781,
      DBGVECB(49) => pcie_block_i_n_782,
      DBGVECB(48) => pcie_block_i_n_783,
      DBGVECB(47) => pcie_block_i_n_784,
      DBGVECB(46) => pcie_block_i_n_785,
      DBGVECB(45) => pcie_block_i_n_786,
      DBGVECB(44) => pcie_block_i_n_787,
      DBGVECB(43) => pcie_block_i_n_788,
      DBGVECB(42) => pcie_block_i_n_789,
      DBGVECB(41) => pcie_block_i_n_790,
      DBGVECB(40) => pcie_block_i_n_791,
      DBGVECB(39) => pcie_block_i_n_792,
      DBGVECB(38) => pcie_block_i_n_793,
      DBGVECB(37) => pcie_block_i_n_794,
      DBGVECB(36) => pcie_block_i_n_795,
      DBGVECB(35) => pcie_block_i_n_796,
      DBGVECB(34) => pcie_block_i_n_797,
      DBGVECB(33) => pcie_block_i_n_798,
      DBGVECB(32) => pcie_block_i_n_799,
      DBGVECB(31) => pcie_block_i_n_800,
      DBGVECB(30) => pcie_block_i_n_801,
      DBGVECB(29) => pcie_block_i_n_802,
      DBGVECB(28) => pcie_block_i_n_803,
      DBGVECB(27) => pcie_block_i_n_804,
      DBGVECB(26) => pcie_block_i_n_805,
      DBGVECB(25) => pcie_block_i_n_806,
      DBGVECB(24) => pcie_block_i_n_807,
      DBGVECB(23) => pcie_block_i_n_808,
      DBGVECB(22) => pcie_block_i_n_809,
      DBGVECB(21) => pcie_block_i_n_810,
      DBGVECB(20) => pcie_block_i_n_811,
      DBGVECB(19) => pcie_block_i_n_812,
      DBGVECB(18) => pcie_block_i_n_813,
      DBGVECB(17) => pcie_block_i_n_814,
      DBGVECB(16) => pcie_block_i_n_815,
      DBGVECB(15) => pcie_block_i_n_816,
      DBGVECB(14) => pcie_block_i_n_817,
      DBGVECB(13) => pcie_block_i_n_818,
      DBGVECB(12) => pcie_block_i_n_819,
      DBGVECB(11) => pcie_block_i_n_820,
      DBGVECB(10) => pcie_block_i_n_821,
      DBGVECB(9) => pcie_block_i_n_822,
      DBGVECB(8) => pcie_block_i_n_823,
      DBGVECB(7) => pcie_block_i_n_824,
      DBGVECB(6) => pcie_block_i_n_825,
      DBGVECB(5) => pcie_block_i_n_826,
      DBGVECB(4) => pcie_block_i_n_827,
      DBGVECB(3) => pcie_block_i_n_828,
      DBGVECB(2) => pcie_block_i_n_829,
      DBGVECB(1) => pcie_block_i_n_830,
      DBGVECB(0) => pcie_block_i_n_831,
      DBGVECC(11) => pcie_block_i_n_172,
      DBGVECC(10) => pcie_block_i_n_173,
      DBGVECC(9) => pcie_block_i_n_174,
      DBGVECC(8) => pcie_block_i_n_175,
      DBGVECC(7) => pcie_block_i_n_176,
      DBGVECC(6) => pcie_block_i_n_177,
      DBGVECC(5) => pcie_block_i_n_178,
      DBGVECC(4) => pcie_block_i_n_179,
      DBGVECC(3) => pcie_block_i_n_180,
      DBGVECC(2) => pcie_block_i_n_181,
      DBGVECC(1) => pcie_block_i_n_182,
      DBGVECC(0) => pcie_block_i_n_183,
      DLRSTN => '1',
      DRPADDR(8 downto 0) => pcie_drp_addr(8 downto 0),
      DRPCLK => pcie_drp_clk,
      DRPDI(15 downto 0) => pcie_drp_di(15 downto 0),
      DRPDO(15 downto 0) => pcie_drp_do(15 downto 0),
      DRPEN => pcie_drp_en,
      DRPRDY => pcie_drp_rdy,
      DRPWE => pcie_drp_we,
      FUNCLVLRSTN => '1',
      LL2BADDLLPERR => pcie_block_i_n_98,
      LL2BADTLPERR => pcie_block_i_n_99,
      LL2LINKSTATUS(4) => pcie_block_i_n_687,
      LL2LINKSTATUS(3) => pcie_block_i_n_688,
      LL2LINKSTATUS(2) => pcie_block_i_n_689,
      LL2LINKSTATUS(1) => pcie_block_i_n_690,
      LL2LINKSTATUS(0) => pcie_block_i_n_691,
      LL2PROTOCOLERR => pcie_block_i_n_100,
      LL2RECEIVERERR => pcie_block_i_n_101,
      LL2REPLAYROERR => pcie_block_i_n_102,
      LL2REPLAYTOERR => pcie_block_i_n_103,
      LL2SENDASREQL1 => '0',
      LL2SENDENTERL1 => '0',
      LL2SENDENTERL23 => '0',
      LL2SENDPMACK => '0',
      LL2SUSPENDNOW => '0',
      LL2SUSPENDOK => pcie_block_i_n_104,
      LL2TFCINIT1SEQ => pcie_block_i_n_105,
      LL2TFCINIT2SEQ => pcie_block_i_n_106,
      LL2TLPRCV => '0',
      LL2TXIDLE => pcie_block_i_n_107,
      LNKCLKEN => pcie_block_i_n_108,
      MIMRXRADDR(12 downto 0) => mim_rx_raddr(12 downto 0),
      MIMRXRDATA(67 downto 0) => mim_rx_rdata_int(67 downto 0),
      MIMRXREN => mim_rx_ren,
      MIMRXWADDR(12 downto 0) => mim_rx_waddr(12 downto 0),
      MIMRXWDATA(67 downto 0) => mim_rx_wdata(67 downto 0),
      MIMRXWEN => mim_rx_wen,
      MIMTXRADDR(12 downto 0) => mim_tx_raddr(12 downto 0),
      MIMTXRDATA(68 downto 0) => mim_tx_rdata_int(68 downto 0),
      MIMTXREN => mim_tx_ren,
      MIMTXWADDR(12 downto 0) => mim_tx_waddr(12 downto 0),
      MIMTXWDATA(68 downto 0) => mim_tx_wdata(68 downto 0),
      MIMTXWEN => mim_tx_wen,
      PIPECLK => pipe_clk,
      PIPERX0CHANISALIGNED => pipe_rx0_chanisaligned,
      PIPERX0CHARISK(1 downto 0) => pipe_rx0_char_is_k(1 downto 0),
      PIPERX0DATA(15 downto 0) => pipe_rx0_data(15 downto 0),
      PIPERX0ELECIDLE => pipe_rx0_elec_idle,
      PIPERX0PHYSTATUS => pipe_rx0_phy_status,
      PIPERX0POLARITY => pipe_rx0_polarity,
      PIPERX0STATUS(2 downto 0) => pipe_rx0_status(2 downto 0),
      PIPERX0VALID => pipe_rx0_valid,
      PIPERX1CHANISALIGNED => pipe_rx1_chanisaligned,
      PIPERX1CHARISK(1 downto 0) => pipe_rx1_char_is_k(1 downto 0),
      PIPERX1DATA(15 downto 0) => pipe_rx1_data(15 downto 0),
      PIPERX1ELECIDLE => pipe_rx1_elec_idle,
      PIPERX1PHYSTATUS => pipe_rx1_phy_status,
      PIPERX1POLARITY => pipe_rx1_polarity,
      PIPERX1STATUS(2 downto 0) => pipe_rx1_status(2 downto 0),
      PIPERX1VALID => pipe_rx1_valid,
      PIPERX2CHANISALIGNED => '0',
      PIPERX2CHARISK(1 downto 0) => B"00",
      PIPERX2DATA(15 downto 0) => B"0000000000000000",
      PIPERX2ELECIDLE => '1',
      PIPERX2PHYSTATUS => '0',
      PIPERX2POLARITY => pipe_rx2_polarity,
      PIPERX2STATUS(2 downto 0) => B"000",
      PIPERX2VALID => '0',
      PIPERX3CHANISALIGNED => '0',
      PIPERX3CHARISK(1 downto 0) => B"00",
      PIPERX3DATA(15 downto 0) => B"0000000000000000",
      PIPERX3ELECIDLE => '1',
      PIPERX3PHYSTATUS => '0',
      PIPERX3POLARITY => pipe_rx3_polarity,
      PIPERX3STATUS(2 downto 0) => B"000",
      PIPERX3VALID => '0',
      PIPERX4CHANISALIGNED => '0',
      PIPERX4CHARISK(1 downto 0) => B"00",
      PIPERX4DATA(15 downto 0) => B"0000000000000000",
      PIPERX4ELECIDLE => '1',
      PIPERX4PHYSTATUS => '0',
      PIPERX4POLARITY => pipe_rx4_polarity,
      PIPERX4STATUS(2 downto 0) => B"000",
      PIPERX4VALID => '0',
      PIPERX5CHANISALIGNED => '0',
      PIPERX5CHARISK(1 downto 0) => B"00",
      PIPERX5DATA(15 downto 0) => B"0000000000000000",
      PIPERX5ELECIDLE => '1',
      PIPERX5PHYSTATUS => '0',
      PIPERX5POLARITY => pipe_rx5_polarity,
      PIPERX5STATUS(2 downto 0) => B"000",
      PIPERX5VALID => '0',
      PIPERX6CHANISALIGNED => '0',
      PIPERX6CHARISK(1 downto 0) => B"00",
      PIPERX6DATA(15 downto 0) => B"0000000000000000",
      PIPERX6ELECIDLE => '1',
      PIPERX6PHYSTATUS => '0',
      PIPERX6POLARITY => pipe_rx6_polarity,
      PIPERX6STATUS(2 downto 0) => B"000",
      PIPERX6VALID => '0',
      PIPERX7CHANISALIGNED => '0',
      PIPERX7CHARISK(1 downto 0) => B"00",
      PIPERX7DATA(15 downto 0) => B"0000000000000000",
      PIPERX7ELECIDLE => '1',
      PIPERX7PHYSTATUS => '0',
      PIPERX7POLARITY => pipe_rx7_polarity,
      PIPERX7STATUS(2 downto 0) => B"000",
      PIPERX7VALID => '0',
      PIPETX0CHARISK(1 downto 0) => pipe_tx0_char_is_k(1 downto 0),
      PIPETX0COMPLIANCE => pipe_tx0_compliance,
      PIPETX0DATA(15 downto 0) => pipe_tx0_data(15 downto 0),
      PIPETX0ELECIDLE => pipe_tx0_elec_idle,
      PIPETX0POWERDOWN(1 downto 0) => pipe_tx0_powerdown(1 downto 0),
      PIPETX1CHARISK(1 downto 0) => pipe_tx1_char_is_k(1 downto 0),
      PIPETX1COMPLIANCE => pipe_tx1_compliance,
      PIPETX1DATA(15 downto 0) => pipe_tx1_data(15 downto 0),
      PIPETX1ELECIDLE => pipe_tx1_elec_idle,
      PIPETX1POWERDOWN(1 downto 0) => pipe_tx1_powerdown(1 downto 0),
      PIPETX2CHARISK(1 downto 0) => pipe_tx2_char_is_k(1 downto 0),
      PIPETX2COMPLIANCE => pipe_tx2_compliance,
      PIPETX2DATA(15 downto 0) => pipe_tx2_data(15 downto 0),
      PIPETX2ELECIDLE => pipe_tx2_elec_idle,
      PIPETX2POWERDOWN(1 downto 0) => pipe_tx2_powerdown(1 downto 0),
      PIPETX3CHARISK(1 downto 0) => pipe_tx3_char_is_k(1 downto 0),
      PIPETX3COMPLIANCE => pipe_tx3_compliance,
      PIPETX3DATA(15 downto 0) => pipe_tx3_data(15 downto 0),
      PIPETX3ELECIDLE => pipe_tx3_elec_idle,
      PIPETX3POWERDOWN(1 downto 0) => pipe_tx3_powerdown(1 downto 0),
      PIPETX4CHARISK(1 downto 0) => pipe_tx4_char_is_k(1 downto 0),
      PIPETX4COMPLIANCE => pipe_tx4_compliance,
      PIPETX4DATA(15 downto 0) => pipe_tx4_data(15 downto 0),
      PIPETX4ELECIDLE => pipe_tx4_elec_idle,
      PIPETX4POWERDOWN(1 downto 0) => pipe_tx4_powerdown(1 downto 0),
      PIPETX5CHARISK(1 downto 0) => pipe_tx5_char_is_k(1 downto 0),
      PIPETX5COMPLIANCE => pipe_tx5_compliance,
      PIPETX5DATA(15 downto 0) => pipe_tx5_data(15 downto 0),
      PIPETX5ELECIDLE => pipe_tx5_elec_idle,
      PIPETX5POWERDOWN(1 downto 0) => pipe_tx5_powerdown(1 downto 0),
      PIPETX6CHARISK(1 downto 0) => pipe_tx6_char_is_k(1 downto 0),
      PIPETX6COMPLIANCE => pipe_tx6_compliance,
      PIPETX6DATA(15 downto 0) => pipe_tx6_data(15 downto 0),
      PIPETX6ELECIDLE => pipe_tx6_elec_idle,
      PIPETX6POWERDOWN(1 downto 0) => pipe_tx6_powerdown(1 downto 0),
      PIPETX7CHARISK(1 downto 0) => pipe_tx7_char_is_k(1 downto 0),
      PIPETX7COMPLIANCE => pipe_tx7_compliance,
      PIPETX7DATA(15 downto 0) => pipe_tx7_data(15 downto 0),
      PIPETX7ELECIDLE => pipe_tx7_elec_idle,
      PIPETX7POWERDOWN(1 downto 0) => pipe_tx7_powerdown(1 downto 0),
      PIPETXDEEMPH => pipe_tx_deemph,
      PIPETXMARGIN(2 downto 0) => pipe_tx_margin(2 downto 0),
      PIPETXRATE => pipe_tx_rate,
      PIPETXRCVRDET => pipe_tx_rcvr_det,
      PIPETXRESET => pcie_block_i_n_140,
      PL2DIRECTEDLSTATE(4 downto 0) => B"00000",
      PL2L0REQ => pcie_block_i_n_141,
      PL2LINKUP => pcie_block_i_n_142,
      PL2RECEIVERERR => pcie_block_i_n_143,
      PL2RECOVERY => pcie_block_i_n_144,
      PL2RXELECIDLE => pcie_block_i_n_145,
      PL2RXPMSTATE(1) => pcie_block_i_n_610,
      PL2RXPMSTATE(0) => pcie_block_i_n_611,
      PL2SUSPENDOK => pcie_block_i_n_146,
      PLDBGMODE(2 downto 0) => B"000",
      PLDBGVEC(11) => pcie_block_i_n_184,
      PLDBGVEC(10) => pcie_block_i_n_185,
      PLDBGVEC(9) => pcie_block_i_n_186,
      PLDBGVEC(8) => pcie_block_i_n_187,
      PLDBGVEC(7) => pcie_block_i_n_188,
      PLDBGVEC(6) => pcie_block_i_n_189,
      PLDBGVEC(5) => pcie_block_i_n_190,
      PLDBGVEC(4) => pcie_block_i_n_191,
      PLDBGVEC(3) => pcie_block_i_n_192,
      PLDBGVEC(2) => pcie_block_i_n_193,
      PLDBGVEC(1) => pcie_block_i_n_194,
      PLDBGVEC(0) => pcie_block_i_n_195,
      PLDIRECTEDCHANGEDONE => pl_directed_change_done,
      PLDIRECTEDLINKAUTON => pl_directed_link_auton,
      PLDIRECTEDLINKCHANGE(1 downto 0) => pl_directed_link_change(1 downto 0),
      PLDIRECTEDLINKSPEED => pl_directed_link_speed,
      PLDIRECTEDLINKWIDTH(1 downto 0) => pl_directed_link_width(1 downto 0),
      PLDIRECTEDLTSSMNEW(5 downto 0) => B"000000",
      PLDIRECTEDLTSSMNEWVLD => '0',
      PLDIRECTEDLTSSMSTALL => '0',
      PLDOWNSTREAMDEEMPHSOURCE => pl_downstream_deemph_source,
      PLINITIALLINKWIDTH(2 downto 0) => pl_initial_link_width(2 downto 0),
      PLLANEREVERSALMODE(1 downto 0) => pl_lane_reversal_mode(1 downto 0),
      PLLINKGEN2CAP => pl_link_gen2_cap,
      PLLINKPARTNERGEN2SUPPORTED => pl_link_partner_gen2_supported,
      PLLINKUPCFGCAP => pl_link_upcfg_cap,
      PLLTSSMSTATE(5 downto 0) => pl_ltssm_state(5 downto 0),
      PLPHYLNKUPN => pl_phy_lnk_up_n,
      PLRECEIVEDHOTRST => pl_received_hot_rst,
      PLRSTN => '1',
      PLRXPMSTATE(1 downto 0) => pl_rx_pm_state(1 downto 0),
      PLSELLNKRATE => pl_sel_lnk_rate,
      PLSELLNKWIDTH(1 downto 0) => pl_sel_lnk_width(1 downto 0),
      PLTRANSMITHOTRST => pl_transmit_hot_rst,
      PLTXPMSTATE(2 downto 0) => pl_tx_pm_state(2 downto 0),
      PLUPSTREAMPREFERDEEMPH => pl_upstream_prefer_deemph,
      RECEIVEDFUNCLVLRSTN => received_func_lvl_rst_n,
      SYSRSTN => sys_rst_n,
      TL2ASPMSUSPENDCREDITCHECK => '0',
      TL2ASPMSUSPENDCREDITCHECKOK => pcie_block_i_n_155,
      TL2ASPMSUSPENDREQ => pcie_block_i_n_156,
      TL2ERRFCPE => pcie_block_i_n_157,
      TL2ERRHDR(63) => pcie_block_i_n_832,
      TL2ERRHDR(62) => pcie_block_i_n_833,
      TL2ERRHDR(61) => pcie_block_i_n_834,
      TL2ERRHDR(60) => pcie_block_i_n_835,
      TL2ERRHDR(59) => pcie_block_i_n_836,
      TL2ERRHDR(58) => pcie_block_i_n_837,
      TL2ERRHDR(57) => pcie_block_i_n_838,
      TL2ERRHDR(56) => pcie_block_i_n_839,
      TL2ERRHDR(55) => pcie_block_i_n_840,
      TL2ERRHDR(54) => pcie_block_i_n_841,
      TL2ERRHDR(53) => pcie_block_i_n_842,
      TL2ERRHDR(52) => pcie_block_i_n_843,
      TL2ERRHDR(51) => pcie_block_i_n_844,
      TL2ERRHDR(50) => pcie_block_i_n_845,
      TL2ERRHDR(49) => pcie_block_i_n_846,
      TL2ERRHDR(48) => pcie_block_i_n_847,
      TL2ERRHDR(47) => pcie_block_i_n_848,
      TL2ERRHDR(46) => pcie_block_i_n_849,
      TL2ERRHDR(45) => pcie_block_i_n_850,
      TL2ERRHDR(44) => pcie_block_i_n_851,
      TL2ERRHDR(43) => pcie_block_i_n_852,
      TL2ERRHDR(42) => pcie_block_i_n_853,
      TL2ERRHDR(41) => pcie_block_i_n_854,
      TL2ERRHDR(40) => pcie_block_i_n_855,
      TL2ERRHDR(39) => pcie_block_i_n_856,
      TL2ERRHDR(38) => pcie_block_i_n_857,
      TL2ERRHDR(37) => pcie_block_i_n_858,
      TL2ERRHDR(36) => pcie_block_i_n_859,
      TL2ERRHDR(35) => pcie_block_i_n_860,
      TL2ERRHDR(34) => pcie_block_i_n_861,
      TL2ERRHDR(33) => pcie_block_i_n_862,
      TL2ERRHDR(32) => pcie_block_i_n_863,
      TL2ERRHDR(31) => pcie_block_i_n_864,
      TL2ERRHDR(30) => pcie_block_i_n_865,
      TL2ERRHDR(29) => pcie_block_i_n_866,
      TL2ERRHDR(28) => pcie_block_i_n_867,
      TL2ERRHDR(27) => pcie_block_i_n_868,
      TL2ERRHDR(26) => pcie_block_i_n_869,
      TL2ERRHDR(25) => pcie_block_i_n_870,
      TL2ERRHDR(24) => pcie_block_i_n_871,
      TL2ERRHDR(23) => pcie_block_i_n_872,
      TL2ERRHDR(22) => pcie_block_i_n_873,
      TL2ERRHDR(21) => pcie_block_i_n_874,
      TL2ERRHDR(20) => pcie_block_i_n_875,
      TL2ERRHDR(19) => pcie_block_i_n_876,
      TL2ERRHDR(18) => pcie_block_i_n_877,
      TL2ERRHDR(17) => pcie_block_i_n_878,
      TL2ERRHDR(16) => pcie_block_i_n_879,
      TL2ERRHDR(15) => pcie_block_i_n_880,
      TL2ERRHDR(14) => pcie_block_i_n_881,
      TL2ERRHDR(13) => pcie_block_i_n_882,
      TL2ERRHDR(12) => pcie_block_i_n_883,
      TL2ERRHDR(11) => pcie_block_i_n_884,
      TL2ERRHDR(10) => pcie_block_i_n_885,
      TL2ERRHDR(9) => pcie_block_i_n_886,
      TL2ERRHDR(8) => pcie_block_i_n_887,
      TL2ERRHDR(7) => pcie_block_i_n_888,
      TL2ERRHDR(6) => pcie_block_i_n_889,
      TL2ERRHDR(5) => pcie_block_i_n_890,
      TL2ERRHDR(4) => pcie_block_i_n_891,
      TL2ERRHDR(3) => pcie_block_i_n_892,
      TL2ERRHDR(2) => pcie_block_i_n_893,
      TL2ERRHDR(1) => pcie_block_i_n_894,
      TL2ERRHDR(0) => pcie_block_i_n_895,
      TL2ERRMALFORMED => pcie_block_i_n_158,
      TL2ERRRXOVERFLOW => pcie_block_i_n_159,
      TL2PPMSUSPENDOK => pcie_block_i_n_160,
      TL2PPMSUSPENDREQ => '0',
      TLRSTN => '1',
      TRNFCCPLD(11 downto 0) => fc_cpld(11 downto 0),
      TRNFCCPLH(7 downto 0) => fc_cplh(7 downto 0),
      TRNFCNPD(11 downto 0) => fc_npd(11 downto 0),
      TRNFCNPH(7 downto 0) => fc_nph(7 downto 0),
      TRNFCPD(11 downto 0) => fc_pd(11 downto 0),
      TRNFCPH(7 downto 0) => fc_ph(7 downto 0),
      TRNFCSEL(2 downto 0) => fc_sel(2 downto 0),
      TRNLNKUP => trn_lnk_up,
      TRNRBARHIT(7) => pcie_block_i_n_1143,
      TRNRBARHIT(6 downto 0) => trn_rbar_hit(6 downto 0),
      TRNRD(127 downto 64) => NLW_pcie_block_i_TRNRD_UNCONNECTED(127 downto 64),
      TRNRD(63 downto 0) => trn_rd(63 downto 0),
      TRNRDLLPDATA(63) => pcie_block_i_n_896,
      TRNRDLLPDATA(62) => pcie_block_i_n_897,
      TRNRDLLPDATA(61) => pcie_block_i_n_898,
      TRNRDLLPDATA(60) => pcie_block_i_n_899,
      TRNRDLLPDATA(59) => pcie_block_i_n_900,
      TRNRDLLPDATA(58) => pcie_block_i_n_901,
      TRNRDLLPDATA(57) => pcie_block_i_n_902,
      TRNRDLLPDATA(56) => pcie_block_i_n_903,
      TRNRDLLPDATA(55) => pcie_block_i_n_904,
      TRNRDLLPDATA(54) => pcie_block_i_n_905,
      TRNRDLLPDATA(53) => pcie_block_i_n_906,
      TRNRDLLPDATA(52) => pcie_block_i_n_907,
      TRNRDLLPDATA(51) => pcie_block_i_n_908,
      TRNRDLLPDATA(50) => pcie_block_i_n_909,
      TRNRDLLPDATA(49) => pcie_block_i_n_910,
      TRNRDLLPDATA(48) => pcie_block_i_n_911,
      TRNRDLLPDATA(47) => pcie_block_i_n_912,
      TRNRDLLPDATA(46) => pcie_block_i_n_913,
      TRNRDLLPDATA(45) => pcie_block_i_n_914,
      TRNRDLLPDATA(44) => pcie_block_i_n_915,
      TRNRDLLPDATA(43) => pcie_block_i_n_916,
      TRNRDLLPDATA(42) => pcie_block_i_n_917,
      TRNRDLLPDATA(41) => pcie_block_i_n_918,
      TRNRDLLPDATA(40) => pcie_block_i_n_919,
      TRNRDLLPDATA(39) => pcie_block_i_n_920,
      TRNRDLLPDATA(38) => pcie_block_i_n_921,
      TRNRDLLPDATA(37) => pcie_block_i_n_922,
      TRNRDLLPDATA(36) => pcie_block_i_n_923,
      TRNRDLLPDATA(35) => pcie_block_i_n_924,
      TRNRDLLPDATA(34) => pcie_block_i_n_925,
      TRNRDLLPDATA(33) => pcie_block_i_n_926,
      TRNRDLLPDATA(32) => pcie_block_i_n_927,
      TRNRDLLPDATA(31) => pcie_block_i_n_928,
      TRNRDLLPDATA(30) => pcie_block_i_n_929,
      TRNRDLLPDATA(29) => pcie_block_i_n_930,
      TRNRDLLPDATA(28) => pcie_block_i_n_931,
      TRNRDLLPDATA(27) => pcie_block_i_n_932,
      TRNRDLLPDATA(26) => pcie_block_i_n_933,
      TRNRDLLPDATA(25) => pcie_block_i_n_934,
      TRNRDLLPDATA(24) => pcie_block_i_n_935,
      TRNRDLLPDATA(23) => pcie_block_i_n_936,
      TRNRDLLPDATA(22) => pcie_block_i_n_937,
      TRNRDLLPDATA(21) => pcie_block_i_n_938,
      TRNRDLLPDATA(20) => pcie_block_i_n_939,
      TRNRDLLPDATA(19) => pcie_block_i_n_940,
      TRNRDLLPDATA(18) => pcie_block_i_n_941,
      TRNRDLLPDATA(17) => pcie_block_i_n_942,
      TRNRDLLPDATA(16) => pcie_block_i_n_943,
      TRNRDLLPDATA(15) => pcie_block_i_n_944,
      TRNRDLLPDATA(14) => pcie_block_i_n_945,
      TRNRDLLPDATA(13) => pcie_block_i_n_946,
      TRNRDLLPDATA(12) => pcie_block_i_n_947,
      TRNRDLLPDATA(11) => pcie_block_i_n_948,
      TRNRDLLPDATA(10) => pcie_block_i_n_949,
      TRNRDLLPDATA(9) => pcie_block_i_n_950,
      TRNRDLLPDATA(8) => pcie_block_i_n_951,
      TRNRDLLPDATA(7) => pcie_block_i_n_952,
      TRNRDLLPDATA(6) => pcie_block_i_n_953,
      TRNRDLLPDATA(5) => pcie_block_i_n_954,
      TRNRDLLPDATA(4) => pcie_block_i_n_955,
      TRNRDLLPDATA(3) => pcie_block_i_n_956,
      TRNRDLLPDATA(2) => pcie_block_i_n_957,
      TRNRDLLPDATA(1) => pcie_block_i_n_958,
      TRNRDLLPDATA(0) => pcie_block_i_n_959,
      TRNRDLLPSRCRDY(1) => pcie_block_i_n_618,
      TRNRDLLPSRCRDY(0) => pcie_block_i_n_619,
      TRNRDSTRDY => trn_rdst_rdy,
      TRNRECRCERR => trn_recrc_err,
      TRNREOF => \^trn_reof\,
      TRNRERRFWD => trn_rerrfwd,
      TRNRFCPRET => '1',
      TRNRNPOK => rx_np_ok,
      TRNRNPREQ => rx_np_req,
      TRNRREM(1) => NLW_pcie_block_i_TRNRREM_UNCONNECTED(1),
      TRNRREM(0) => trn_rrem(0),
      TRNRSOF => \^trn_rsof\,
      TRNRSRCDSC => \^trn_rsrc_dsc\,
      TRNRSRCRDY => trn_rsrc_rdy,
      TRNTBUFAV(5 downto 0) => \^trn_tbuf_av\(5 downto 0),
      TRNTCFGGNT => trn_tcfg_gnt,
      TRNTCFGREQ => \^trn_tcfg_req\,
      TRNTD(127 downto 64) => B"0000000000000000000000000000000000000000000000000000000000000000",
      TRNTD(63 downto 0) => trn_td(63 downto 0),
      TRNTDLLPDATA(31 downto 0) => B"00000000000000000000000000000000",
      TRNTDLLPDSTRDY => pcie_block_i_n_169,
      TRNTDLLPSRCRDY => '0',
      TRNTDSTRDY(3 downto 1) => NLW_pcie_block_i_TRNTDSTRDY_UNCONNECTED(3 downto 1),
      TRNTDSTRDY(0) => \^trn_tdst_rdy\,
      TRNTECRCGEN => cfg_aer_ecrc_check_en_0(0),
      TRNTEOF => trn_teof,
      TRNTERRDROP => tx_err_drop,
      TRNTERRFWD => cfg_aer_ecrc_check_en_0(1),
      TRNTREM(1) => '0',
      TRNTREM(0) => trn_trem(0),
      TRNTSOF => trn_tsof,
      TRNTSRCDSC => cfg_aer_ecrc_check_en_0(3),
      TRNTSRCRDY => trn_tsrc_rdy,
      TRNTSTR => cfg_aer_ecrc_check_en_0(2),
      USERCLK => CLK,
      USERCLK2 => CLK,
      USERRSTN => user_rst_n
    );
pcie_block_i_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_atomic_egress_blocked,
      O => cfg_err_atomic_egress_blocked_n
    );
pcie_block_i_i_10: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_malformed,
      O => cfg_err_malformed_n
    );
pcie_block_i_i_11: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_mc_blocked,
      O => cfg_err_mc_blocked_n
    );
pcie_block_i_i_12: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_norecovery,
      O => cfg_err_norecovery_n
    );
pcie_block_i_i_13: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_poisoned,
      O => cfg_err_poisoned_n
    );
pcie_block_i_i_14: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_posted,
      O => cfg_err_posted_n
    );
pcie_block_i_i_15: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_ur,
      O => cfg_err_ur_n
    );
pcie_block_i_i_16: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_interrupt_assert,
      O => cfg_interrupt_assert_n
    );
pcie_block_i_i_17: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_interrupt,
      O => cfg_interrupt_n
    );
pcie_block_i_i_18: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_interrupt_stat,
      O => cfg_interrupt_stat_n
    );
pcie_block_i_i_19: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_mgmt_rd_en,
      O => cfg_mgmt_rd_en_n
    );
pcie_block_i_i_2: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_cor,
      O => cfg_err_cor_n
    );
pcie_block_i_i_20: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_mgmt_wr_en,
      O => cfg_mgmt_wr_en_n
    );
pcie_block_i_i_21: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_mgmt_wr_readonly,
      O => cfg_mgmt_wr_readonly_n
    );
pcie_block_i_i_22: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_mgmt_wr_rw1c_as_rw,
      O => cfg_mgmt_wr_rw1c_as_rw_n
    );
pcie_block_i_i_23: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_pm_force_state_en,
      O => cfg_pm_force_state_en_n
    );
pcie_block_i_i_24: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_pm_halt_aspm_l0s,
      O => cfg_pm_halt_aspm_l0s_n
    );
pcie_block_i_i_25: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_pm_halt_aspm_l1,
      O => cfg_pm_halt_aspm_l1_n
    );
pcie_block_i_i_27: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_pm_wake,
      O => cfg_pm_wake_n
    );
pcie_block_i_i_28: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_trn_pending,
      O => cfg_trn_pending_n
    );
pcie_block_i_i_3: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_cpl_abort,
      O => cfg_err_cpl_abort_n
    );
pcie_block_i_i_4: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_cpl_timeout,
      O => cfg_err_cpl_timeout_n
    );
pcie_block_i_i_5: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_cpl_unexpect,
      O => cfg_err_cpl_unexpect_n
    );
pcie_block_i_i_6: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_ecrc,
      O => cfg_err_ecrc_n
    );
pcie_block_i_i_7: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_internal_cor,
      O => cfg_err_internal_cor_n
    );
pcie_block_i_i_8: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_internal_uncor,
      O => cfg_err_internal_uncor_n
    );
pcie_block_i_i_9: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_err_locked,
      O => cfg_err_locked_n
    );
pcie_bram_top: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_bram_top_7x
     port map (
      CLK => CLK,
      MIMRXRADDR(10 downto 0) => mim_rx_raddr(10 downto 0),
      MIMRXWADDR(10 downto 0) => mim_rx_waddr(10 downto 0),
      MIMTXRADDR(10 downto 0) => mim_tx_raddr(10 downto 0),
      MIMTXWADDR(10 downto 0) => mim_tx_waddr(10 downto 0),
      mim_rx_ren => mim_rx_ren,
      mim_rx_wen => mim_rx_wen,
      mim_tx_ren => mim_tx_ren,
      mim_tx_wen => mim_tx_wen,
      \ramb_bl.ramb36_dp_bl.ram36_bl\(67 downto 0) => mim_rx_rdata_int(67 downto 0),
      \ramb_bl.ramb36_dp_bl.ram36_bl_0\(67 downto 0) => mim_rx_wdata(67 downto 0),
      rdata(68 downto 0) => mim_tx_rdata_int(68 downto 0),
      wdata(68 downto 0) => mim_tx_wdata(68 downto 0)
    );
pl_phy_lnk_up_cdc_i_1: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => pl_phy_lnk_up_n,
      O => src_in
    );
ppm_L1_thrtl_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"FFFEAAAA"
    )
        port map (
      I0 => ppm_L1_trig,
      I1 => \^cfg_pcie_link_state\(0),
      I2 => \^cfg_pcie_link_state\(2),
      I3 => \^cfg_pcie_link_state\(1),
      I4 => ppm_L1_thrtl,
      O => ppm_L1_thrtl_reg
    );
tbuf_av_min_thrtl_i_1: unisim.vcomponents.LUT5
    generic map(
      INIT => X"00000001"
    )
        port map (
      I0 => \^trn_tbuf_av\(1),
      I1 => \^trn_tbuf_av\(3),
      I2 => \^trn_tbuf_av\(2),
      I3 => \^trn_tbuf_av\(5),
      I4 => \^trn_tbuf_av\(4),
      O => tbuf_av_min_trig
    );
tready_thrtl_xhdl1_i_10: unisim.vcomponents.LUT2
    generic map(
      INIT => X"8"
    )
        port map (
      I0 => \^trn_tcfg_req\,
      I1 => reg_tcfg_gnt,
      O => tcfg_req_trig
    );
tready_thrtl_xhdl1_i_11: unisim.vcomponents.LUT6
    generic map(
      INIT => X"0000000100000003"
    )
        port map (
      I0 => \^trn_tbuf_av\(1),
      I1 => \^trn_tbuf_av\(4),
      I2 => \^trn_tbuf_av\(5),
      I3 => \^trn_tbuf_av\(2),
      I4 => \^trn_tbuf_av\(3),
      I5 => \^trn_tbuf_av\(0),
      O => gt_rxelecidle_q_reg
    );
trn_in_packet_i_1: unisim.vcomponents.LUT6
    generic map(
      INIT => X"08000000AEAA2AAA"
    )
        port map (
      I0 => trn_in_packet,
      I1 => trn_rdst_rdy,
      I2 => \^trn_reof\,
      I3 => trn_rsrc_rdy,
      I4 => \^trn_rsof\,
      I5 => \^trn_rsrc_dsc\,
      O => trn_in_packet_reg
    );
trn_rsrc_dsc_prev_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^trn_rsrc_dsc\,
      I1 => reg_dsc_detect,
      O => trn_rsrc_dsc_prev0
    );
trn_rsrc_rdy_prev_i_1: unisim.vcomponents.LUT4
    generic map(
      INIT => X"AA08"
    )
        port map (
      I0 => trn_rsrc_rdy,
      I1 => \^trn_rsof\,
      I2 => \^trn_rsrc_dsc\,
      I3 => trn_in_packet,
      O => rsrc_rdy_filtered6_out
    );
user_reset_int_i_1: unisim.vcomponents.LUT3
    generic map(
      INIT => X"2A"
    )
        port map (
      I0 => bridge_reset_int,
      I1 => pl_phy_lnk_up,
      I2 => user_rst_n,
      O => user_reset_int_reg
    );
\xhdl12.xhdl14.xhdl15.reg_to_turnoff_i_1\: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => \^cfg_to_turnoff\,
      I1 => reg_to_turnoff,
      O => \xhdl12.xhdl14.xhdl15.reg_to_turnoff_reg\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_top is
  port (
    m_axis_rx_tvalid_xhdl2_reg : out STD_LOGIC;
    m_axis_rx_tlast : out STD_LOGIC;
    trn_tcfg_req : out STD_LOGIC;
    tready_thrtl_xhdl1_reg : out STD_LOGIC;
    user_reset_int_reg : out STD_LOGIC;
    src_in : out STD_LOGIC;
    cfg_mgmt_rd_wr_done : out STD_LOGIC;
    cfg_err_aer_headerlog_set : out STD_LOGIC;
    cfg_err_cpl_rdy : out STD_LOGIC;
    cfg_interrupt_rdy : out STD_LOGIC;
    cfg_msg_received : out STD_LOGIC;
    cfg_received_func_lvl_rst : out STD_LOGIC;
    cfg_pcie_link_state : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_to_turnoff : out STD_LOGIC;
    m_axis_rx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_rx_tkeep : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axis_rx_tuser : out STD_LOGIC_VECTOR ( 12 downto 0 );
    trn_tbuf_av : out STD_LOGIC_VECTOR ( 5 downto 0 );
    cfg_bus_number : out STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_msg_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_device_number : out STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_function_number : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_aer_ecrc_check_en : out STD_LOGIC;
    cfg_aer_ecrc_gen_en : out STD_LOGIC;
    cfg_aer_rooterr_corr_err_received : out STD_LOGIC;
    cfg_aer_rooterr_corr_err_reporting_en : out STD_LOGIC;
    cfg_aer_rooterr_fatal_err_received : out STD_LOGIC;
    cfg_aer_rooterr_fatal_err_reporting_en : out STD_LOGIC;
    cfg_aer_rooterr_non_fatal_err_received : out STD_LOGIC;
    cfg_aer_rooterr_non_fatal_err_reporting_en : out STD_LOGIC;
    cfg_bridge_serr_en : out STD_LOGIC;
    cfg_command : out STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_dcommand2 : out STD_LOGIC_VECTOR ( 11 downto 0 );
    cfg_dcommand : out STD_LOGIC_VECTOR ( 14 downto 0 );
    cfg_dstatus : out STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_interrupt_msienable : out STD_LOGIC;
    cfg_interrupt_msixenable : out STD_LOGIC;
    cfg_interrupt_msixfm : out STD_LOGIC;
    cfg_lcommand : out STD_LOGIC_VECTOR ( 10 downto 0 );
    cfg_lstatus : out STD_LOGIC_VECTOR ( 9 downto 0 );
    cfg_msg_received_assert_int_a : out STD_LOGIC;
    cfg_msg_received_assert_int_b : out STD_LOGIC;
    cfg_msg_received_assert_int_c : out STD_LOGIC;
    cfg_msg_received_assert_int_d : out STD_LOGIC;
    cfg_msg_received_deassert_int_a : out STD_LOGIC;
    cfg_msg_received_deassert_int_b : out STD_LOGIC;
    cfg_msg_received_deassert_int_c : out STD_LOGIC;
    cfg_msg_received_deassert_int_d : out STD_LOGIC;
    cfg_msg_received_err_cor : out STD_LOGIC;
    cfg_msg_received_err_fatal : out STD_LOGIC;
    cfg_msg_received_err_non_fatal : out STD_LOGIC;
    cfg_msg_received_pm_as_nak : out STD_LOGIC;
    cfg_msg_received_pme_to_ack : out STD_LOGIC;
    cfg_msg_received_pm_pme : out STD_LOGIC;
    cfg_msg_received_setslotpowerlimit : out STD_LOGIC;
    cfg_pmcsr_pme_en : out STD_LOGIC;
    cfg_pmcsr_pme_status : out STD_LOGIC;
    cfg_root_control_pme_int_en : out STD_LOGIC;
    cfg_root_control_syserr_corr_err_en : out STD_LOGIC;
    cfg_root_control_syserr_fatal_err_en : out STD_LOGIC;
    cfg_root_control_syserr_non_fatal_err_en : out STD_LOGIC;
    cfg_slot_control_electromech_il_ctl_pulse : out STD_LOGIC;
    pcie_drp_rdy : out STD_LOGIC;
    pipe_rx0_polarity : out STD_LOGIC;
    pipe_rx1_polarity : out STD_LOGIC;
    pipe_tx0_compliance : out STD_LOGIC;
    pipe_tx0_elec_idle : out STD_LOGIC;
    pipe_tx1_compliance : out STD_LOGIC;
    pipe_tx1_elec_idle : out STD_LOGIC;
    pipe_tx_deemph : out STD_LOGIC;
    pipe_tx_rate : out STD_LOGIC;
    pipe_tx_rcvr_det : out STD_LOGIC;
    pl_directed_change_done : out STD_LOGIC;
    pl_link_gen2_cap : out STD_LOGIC;
    pl_link_partner_gen2_supported : out STD_LOGIC;
    pl_link_upcfg_cap : out STD_LOGIC;
    pl_received_hot_rst : out STD_LOGIC;
    pl_sel_lnk_rate : out STD_LOGIC;
    trn_lnk_up : out STD_LOGIC;
    tx_err_drop : out STD_LOGIC;
    fc_cpld : out STD_LOGIC_VECTOR ( 11 downto 0 );
    fc_npd : out STD_LOGIC_VECTOR ( 11 downto 0 );
    fc_pd : out STD_LOGIC_VECTOR ( 11 downto 0 );
    pcie_drp_do : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_tx0_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_tx1_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_pmcsr_powerstate : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx0_char_is_k : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx0_powerdown : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx1_char_is_k : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_tx1_powerdown : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_lane_reversal_mode : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_rx_pm_state : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_sel_lnk_width : out STD_LOGIC_VECTOR ( 1 downto 0 );
    cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_tx_margin : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pl_initial_link_width : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pl_tx_pm_state : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_mgmt_do : out STD_LOGIC_VECTOR ( 31 downto 0 );
    pl_ltssm_state : out STD_LOGIC_VECTOR ( 5 downto 0 );
    cfg_vc_tcvc_map : out STD_LOGIC_VECTOR ( 6 downto 0 );
    cfg_interrupt_do : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_cplh : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_nph : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_ph : out STD_LOGIC_VECTOR ( 7 downto 0 );
    \tbuf_gap_cnt_reg[0]\ : in STD_LOGIC;
    CLK : in STD_LOGIC;
    s_axis_tx_tlast : in STD_LOGIC;
    s_axis_tx_tvalid : in STD_LOGIC;
    s_axis_tx_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
    tx_cfg_gnt : in STD_LOGIC;
    cfg_turnoff_ok : in STD_LOGIC;
    bridge_reset_int : in STD_LOGIC;
    pl_phy_lnk_up : in STD_LOGIC;
    m_axis_rx_tready : in STD_LOGIC;
    cfg_trn_pending : in STD_LOGIC;
    cfg_mgmt_wr_rw1c_as_rw : in STD_LOGIC;
    cfg_mgmt_wr_readonly : in STD_LOGIC;
    cfg_mgmt_wr_en : in STD_LOGIC;
    cfg_mgmt_rd_en : in STD_LOGIC;
    cfg_err_malformed : in STD_LOGIC;
    cfg_err_cor : in STD_LOGIC;
    cfg_err_ur : in STD_LOGIC;
    cfg_err_ecrc : in STD_LOGIC;
    cfg_err_cpl_timeout : in STD_LOGIC;
    cfg_err_cpl_abort : in STD_LOGIC;
    cfg_err_cpl_unexpect : in STD_LOGIC;
    cfg_err_poisoned : in STD_LOGIC;
    cfg_err_atomic_egress_blocked : in STD_LOGIC;
    cfg_err_mc_blocked : in STD_LOGIC;
    cfg_err_internal_uncor : in STD_LOGIC;
    cfg_err_internal_cor : in STD_LOGIC;
    cfg_err_posted : in STD_LOGIC;
    cfg_err_locked : in STD_LOGIC;
    cfg_err_norecovery : in STD_LOGIC;
    cfg_interrupt : in STD_LOGIC;
    cfg_interrupt_assert : in STD_LOGIC;
    cfg_interrupt_stat : in STD_LOGIC;
    cfg_pm_halt_aspm_l0s : in STD_LOGIC;
    cfg_pm_halt_aspm_l1 : in STD_LOGIC;
    cfg_pm_force_state_en : in STD_LOGIC;
    cfg_pm_wake : in STD_LOGIC;
    \out\ : in STD_LOGIC;
    s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axis_tx_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
    pcie_drp_clk : in STD_LOGIC;
    pcie_drp_en : in STD_LOGIC;
    pcie_drp_we : in STD_LOGIC;
    pipe_clk : in STD_LOGIC;
    pipe_rx0_chanisaligned : in STD_LOGIC;
    pipe_rx0_elec_idle : in STD_LOGIC;
    pipe_rx0_phy_status : in STD_LOGIC;
    pipe_rx0_valid : in STD_LOGIC;
    pipe_rx1_chanisaligned : in STD_LOGIC;
    pipe_rx1_elec_idle : in STD_LOGIC;
    pipe_rx1_phy_status : in STD_LOGIC;
    pipe_rx1_valid : in STD_LOGIC;
    pl_directed_link_auton : in STD_LOGIC;
    pl_directed_link_speed : in STD_LOGIC;
    pl_downstream_deemph_source : in STD_LOGIC;
    pl_transmit_hot_rst : in STD_LOGIC;
    pl_upstream_prefer_deemph : in STD_LOGIC;
    sys_rst_n : in STD_LOGIC;
    rx_np_ok : in STD_LOGIC;
    rx_np_req : in STD_LOGIC;
    cfg_err_aer_headerlog : in STD_LOGIC_VECTOR ( 127 downto 0 );
    pcie_drp_di : in STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_rx0_data : in STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_rx1_data : in STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_pm_force_state : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rx0_char_is_k : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rx1_char_is_k : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_directed_link_change : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_directed_link_width : in STD_LOGIC_VECTOR ( 1 downto 0 );
    cfg_ds_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_rx0_status : in STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_rx1_status : in STD_LOGIC_VECTOR ( 2 downto 0 );
    fc_sel : in STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_mgmt_di : in STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_mgmt_byte_en_n : in STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_err_tlp_cpl_header : in STD_LOGIC_VECTOR ( 47 downto 0 );
    cfg_aer_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_ds_device_number : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_pciecap_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 );
    cfg_ds_bus_number : in STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_interrupt_di : in STD_LOGIC_VECTOR ( 7 downto 0 );
    pcie_drp_addr : in STD_LOGIC_VECTOR ( 8 downto 0 );
    cfg_mgmt_dwaddr : in STD_LOGIC_VECTOR ( 9 downto 0 )
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_top : entity is "spec7_pcie_7x_0_pcie_top";
end spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_top;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_top is
  signal \^cfg_msg_data\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \^cfg_pcie_link_state\ : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal cfg_pm_turnoff_ok_n : STD_LOGIC;
  signal pcie_7x_i_n_13 : STD_LOGIC;
  signal pcie_7x_i_n_17 : STD_LOGIC;
  signal pcie_7x_i_n_24 : STD_LOGIC;
  signal pcie_7x_i_n_32 : STD_LOGIC;
  signal pcie_7x_i_n_6 : STD_LOGIC;
  signal pcie_7x_i_n_9 : STD_LOGIC;
  signal \rx_inst/rx_pipeline_inst/dsc_detect\ : STD_LOGIC;
  signal \rx_inst/rx_pipeline_inst/reg_dsc_detect\ : STD_LOGIC;
  signal \rx_inst/rx_pipeline_inst/rsrc_rdy_filtered6_out\ : STD_LOGIC;
  signal \rx_inst/rx_pipeline_inst/trn_in_packet\ : STD_LOGIC;
  signal \rx_inst/rx_pipeline_inst/trn_rsrc_dsc_d\ : STD_LOGIC;
  signal \rx_inst/rx_pipeline_inst/trn_rsrc_dsc_prev0\ : STD_LOGIC;
  signal trn_rbar_hit : STD_LOGIC_VECTOR ( 6 downto 0 );
  signal trn_rd : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal trn_rdst_rdy : STD_LOGIC;
  signal trn_recrc_err : STD_LOGIC;
  signal trn_reof : STD_LOGIC;
  signal trn_rerrfwd : STD_LOGIC;
  signal trn_rrem : STD_LOGIC;
  signal trn_rsof : STD_LOGIC;
  signal trn_rsrc_dsc : STD_LOGIC;
  signal \^trn_tbuf_av\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal trn_tcfg_gnt : STD_LOGIC;
  signal \^trn_tcfg_req\ : STD_LOGIC;
  signal trn_td : STD_LOGIC_VECTOR ( 63 downto 0 );
  signal trn_tdst_rdy : STD_LOGIC;
  signal trn_tecrc_gen : STD_LOGIC;
  signal trn_teof : STD_LOGIC;
  signal trn_terrfwd : STD_LOGIC;
  signal trn_trem : STD_LOGIC;
  signal trn_tsof : STD_LOGIC;
  signal trn_tsrc_dsc : STD_LOGIC;
  signal trn_tsrc_rdy : STD_LOGIC;
  signal trn_tstr : STD_LOGIC;
  signal \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_thrtl\ : STD_LOGIC;
  signal \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\ : STD_LOGIC;
  signal \tx_inst/xhdl12.tx_thrl_ctl_inst/ppm_L1_thrtl\ : STD_LOGIC;
  signal \tx_inst/xhdl12.tx_thrl_ctl_inst/ppm_L1_trig\ : STD_LOGIC;
  signal \tx_inst/xhdl12.tx_thrl_ctl_inst/reg_tcfg_gnt\ : STD_LOGIC;
  signal \tx_inst/xhdl12.tx_thrl_ctl_inst/reg_to_turnoff\ : STD_LOGIC;
  signal \tx_inst/xhdl12.tx_thrl_ctl_inst/tbuf_av_min_trig\ : STD_LOGIC;
  signal \tx_inst/xhdl12.tx_thrl_ctl_inst/tcfg_req_trig\ : STD_LOGIC;
begin
  cfg_msg_data(15 downto 0) <= \^cfg_msg_data\(15 downto 0);
  cfg_pcie_link_state(2 downto 0) <= \^cfg_pcie_link_state\(2 downto 0);
  trn_tbuf_av(5 downto 0) <= \^trn_tbuf_av\(5 downto 0);
  trn_tcfg_req <= \^trn_tcfg_req\;
axi_basic_top_i: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_axi_basic_top
     port map (
      CLK => CLK,
      E(0) => trn_rdst_rdy,
      Q(63 downto 32) => trn_td(31 downto 0),
      Q(31 downto 0) => trn_td(63 downto 32),
      cfg_pcie_link_state(2 downto 0) => \^cfg_pcie_link_state\(2 downto 0),
      cfg_pm_turnoff_ok_n => cfg_pm_turnoff_ok_n,
      cfg_turnoff_ok => cfg_turnoff_ok,
      dsc_detect => \rx_inst/rx_pipeline_inst/dsc_detect\,
      lnk_up_thrtl => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_thrtl\,
      lnk_up_thrtl_reg => pcie_7x_i_n_32,
      m_axis_rx_tdata(63 downto 0) => m_axis_rx_tdata(63 downto 0),
      m_axis_rx_tkeep(1 downto 0) => m_axis_rx_tkeep(1 downto 0),
      m_axis_rx_tlast => m_axis_rx_tlast,
      m_axis_rx_tready => m_axis_rx_tready,
      m_axis_rx_tuser(12 downto 0) => m_axis_rx_tuser(12 downto 0),
      m_axis_rx_tvalid_xhdl2_reg => m_axis_rx_tvalid_xhdl2_reg,
      \out\ => \out\,
      ppm_L1_thrtl => \tx_inst/xhdl12.tx_thrl_ctl_inst/ppm_L1_thrtl\,
      ppm_L1_thrtl_reg => pcie_7x_i_n_13,
      ppm_L1_trig => \tx_inst/xhdl12.tx_thrl_ctl_inst/ppm_L1_trig\,
      reg_dsc_detect => \rx_inst/rx_pipeline_inst/reg_dsc_detect\,
      reg_tcfg_gnt => \tx_inst/xhdl12.tx_thrl_ctl_inst/reg_tcfg_gnt\,
      reg_to_turnoff => \tx_inst/xhdl12.tx_thrl_ctl_inst/reg_to_turnoff\,
      rsrc_rdy_filtered6_out => \rx_inst/rx_pipeline_inst/rsrc_rdy_filtered6_out\,
      s_axis_tx_tdata(63 downto 0) => s_axis_tx_tdata(63 downto 0),
      s_axis_tx_tkeep(0) => s_axis_tx_tkeep(0),
      s_axis_tx_tlast => s_axis_tx_tlast,
      s_axis_tx_tuser(3 downto 0) => s_axis_tx_tuser(3 downto 0),
      s_axis_tx_tvalid => s_axis_tx_tvalid,
      tbuf_av_min_trig => \tx_inst/xhdl12.tx_thrl_ctl_inst/tbuf_av_min_trig\,
      \tbuf_gap_cnt_reg[0]\ => \tbuf_gap_cnt_reg[0]\,
      tcfg_req_trig => \tx_inst/xhdl12.tx_thrl_ctl_inst/tcfg_req_trig\,
      tready_thrtl_xhdl1_i_4 => pcie_7x_i_n_24,
      tready_thrtl_xhdl1_reg => tready_thrtl_xhdl1_reg,
      trn_in_packet => \rx_inst/rx_pipeline_inst/trn_in_packet\,
      trn_in_packet_reg => pcie_7x_i_n_9,
      trn_rbar_hit(6 downto 0) => trn_rbar_hit(6 downto 0),
      trn_rd(63 downto 0) => trn_rd(63 downto 0),
      trn_recrc_err => trn_recrc_err,
      trn_reof => trn_reof,
      trn_rerrfwd => trn_rerrfwd,
      trn_rrem(0) => trn_rrem,
      trn_rsof => trn_rsof,
      trn_rsrc_dsc => trn_rsrc_dsc,
      trn_rsrc_dsc_d => \rx_inst/rx_pipeline_inst/trn_rsrc_dsc_d\,
      trn_rsrc_dsc_prev0 => \rx_inst/rx_pipeline_inst/trn_rsrc_dsc_prev0\,
      trn_tbuf_av(5 downto 0) => \^trn_tbuf_av\(5 downto 0),
      trn_tcfg_gnt => trn_tcfg_gnt,
      trn_tcfg_req => \^trn_tcfg_req\,
      trn_tdst_rdy => trn_tdst_rdy,
      trn_teof => trn_teof,
      trn_trem(0) => trn_trem,
      trn_tsof => trn_tsof,
      trn_tsrc_rdy => trn_tsrc_rdy,
      tx_cfg_gnt => tx_cfg_gnt,
      \xhdl12.reg_tuser_reg[3]\(3) => trn_tsrc_dsc,
      \xhdl12.reg_tuser_reg[3]\(2) => trn_tstr,
      \xhdl12.reg_tuser_reg[3]\(1) => trn_terrfwd,
      \xhdl12.reg_tuser_reg[3]\(0) => trn_tecrc_gen,
      \xhdl12.xhdl14.xhdl15.reg_to_turnoff_reg\ => pcie_7x_i_n_17
    );
\cfg_bus_number_d[7]_i_1\: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => \out\,
      O => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_bus_number_d_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_6,
      D => \^cfg_msg_data\(8),
      Q => cfg_bus_number(0),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_bus_number_d_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_6,
      D => \^cfg_msg_data\(9),
      Q => cfg_bus_number(1),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_bus_number_d_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_6,
      D => \^cfg_msg_data\(10),
      Q => cfg_bus_number(2),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_bus_number_d_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_6,
      D => \^cfg_msg_data\(11),
      Q => cfg_bus_number(3),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_bus_number_d_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_6,
      D => \^cfg_msg_data\(12),
      Q => cfg_bus_number(4),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_bus_number_d_reg[5]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_6,
      D => \^cfg_msg_data\(13),
      Q => cfg_bus_number(5),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_bus_number_d_reg[6]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_6,
      D => \^cfg_msg_data\(14),
      Q => cfg_bus_number(6),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_bus_number_d_reg[7]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_6,
      D => \^cfg_msg_data\(15),
      Q => cfg_bus_number(7),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_device_number_d_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_6,
      D => \^cfg_msg_data\(3),
      Q => cfg_device_number(0),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_device_number_d_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_6,
      D => \^cfg_msg_data\(4),
      Q => cfg_device_number(1),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_device_number_d_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_6,
      D => \^cfg_msg_data\(5),
      Q => cfg_device_number(2),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_device_number_d_reg[3]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_6,
      D => \^cfg_msg_data\(6),
      Q => cfg_device_number(3),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_device_number_d_reg[4]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_6,
      D => \^cfg_msg_data\(7),
      Q => cfg_device_number(4),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_function_number_d_reg[0]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_6,
      D => \^cfg_msg_data\(0),
      Q => cfg_function_number(0),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_function_number_d_reg[1]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_6,
      D => \^cfg_msg_data\(1),
      Q => cfg_function_number(1),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
\cfg_function_number_d_reg[2]\: unisim.vcomponents.FDRE
     port map (
      C => CLK,
      CE => pcie_7x_i_n_6,
      D => \^cfg_msg_data\(2),
      Q => cfg_function_number(2),
      R => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_trig\
    );
pcie_7x_i: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_7x
     port map (
      CLK => CLK,
      E(0) => pcie_7x_i_n_6,
      bridge_reset_int => bridge_reset_int,
      cfg_aer_ecrc_check_en => cfg_aer_ecrc_check_en,
      cfg_aer_ecrc_check_en_0(3) => trn_tsrc_dsc,
      cfg_aer_ecrc_check_en_0(2) => trn_tstr,
      cfg_aer_ecrc_check_en_0(1) => trn_terrfwd,
      cfg_aer_ecrc_check_en_0(0) => trn_tecrc_gen,
      cfg_aer_ecrc_gen_en => cfg_aer_ecrc_gen_en,
      cfg_aer_interrupt_msgnum(4 downto 0) => cfg_aer_interrupt_msgnum(4 downto 0),
      cfg_aer_rooterr_corr_err_received => cfg_aer_rooterr_corr_err_received,
      cfg_aer_rooterr_corr_err_reporting_en => cfg_aer_rooterr_corr_err_reporting_en,
      cfg_aer_rooterr_fatal_err_received => cfg_aer_rooterr_fatal_err_received,
      cfg_aer_rooterr_fatal_err_reporting_en => cfg_aer_rooterr_fatal_err_reporting_en,
      cfg_aer_rooterr_non_fatal_err_received => cfg_aer_rooterr_non_fatal_err_received,
      cfg_aer_rooterr_non_fatal_err_reporting_en => cfg_aer_rooterr_non_fatal_err_reporting_en,
      cfg_bridge_serr_en => cfg_bridge_serr_en,
      cfg_command(4 downto 0) => cfg_command(4 downto 0),
      cfg_dcommand(14 downto 0) => cfg_dcommand(14 downto 0),
      cfg_dcommand2(11 downto 0) => cfg_dcommand2(11 downto 0),
      cfg_ds_bus_number(7 downto 0) => cfg_ds_bus_number(7 downto 0),
      cfg_ds_device_number(4 downto 0) => cfg_ds_device_number(4 downto 0),
      cfg_ds_function_number(2 downto 0) => cfg_ds_function_number(2 downto 0),
      cfg_dsn(63 downto 0) => cfg_dsn(63 downto 0),
      cfg_dstatus(3 downto 0) => cfg_dstatus(3 downto 0),
      cfg_err_aer_headerlog(127 downto 0) => cfg_err_aer_headerlog(127 downto 0),
      cfg_err_aer_headerlog_set => cfg_err_aer_headerlog_set,
      cfg_err_atomic_egress_blocked => cfg_err_atomic_egress_blocked,
      cfg_err_cor => cfg_err_cor,
      cfg_err_cpl_abort => cfg_err_cpl_abort,
      cfg_err_cpl_rdy => cfg_err_cpl_rdy,
      cfg_err_cpl_timeout => cfg_err_cpl_timeout,
      cfg_err_cpl_unexpect => cfg_err_cpl_unexpect,
      cfg_err_ecrc => cfg_err_ecrc,
      cfg_err_internal_cor => cfg_err_internal_cor,
      cfg_err_internal_uncor => cfg_err_internal_uncor,
      cfg_err_locked => cfg_err_locked,
      cfg_err_malformed => cfg_err_malformed,
      cfg_err_mc_blocked => cfg_err_mc_blocked,
      cfg_err_norecovery => cfg_err_norecovery,
      cfg_err_poisoned => cfg_err_poisoned,
      cfg_err_posted => cfg_err_posted,
      cfg_err_tlp_cpl_header(47 downto 0) => cfg_err_tlp_cpl_header(47 downto 0),
      cfg_err_ur => cfg_err_ur,
      cfg_interrupt => cfg_interrupt,
      cfg_interrupt_assert => cfg_interrupt_assert,
      cfg_interrupt_di(7 downto 0) => cfg_interrupt_di(7 downto 0),
      cfg_interrupt_do(7 downto 0) => cfg_interrupt_do(7 downto 0),
      cfg_interrupt_mmenable(2 downto 0) => cfg_interrupt_mmenable(2 downto 0),
      cfg_interrupt_msienable => cfg_interrupt_msienable,
      cfg_interrupt_msixenable => cfg_interrupt_msixenable,
      cfg_interrupt_msixfm => cfg_interrupt_msixfm,
      cfg_interrupt_rdy => cfg_interrupt_rdy,
      cfg_interrupt_stat => cfg_interrupt_stat,
      cfg_lcommand(10 downto 0) => cfg_lcommand(10 downto 0),
      cfg_lstatus(9 downto 0) => cfg_lstatus(9 downto 0),
      cfg_mgmt_byte_en_n(3 downto 0) => cfg_mgmt_byte_en_n(3 downto 0),
      cfg_mgmt_di(31 downto 0) => cfg_mgmt_di(31 downto 0),
      cfg_mgmt_do(31 downto 0) => cfg_mgmt_do(31 downto 0),
      cfg_mgmt_dwaddr(9 downto 0) => cfg_mgmt_dwaddr(9 downto 0),
      cfg_mgmt_rd_en => cfg_mgmt_rd_en,
      cfg_mgmt_rd_wr_done => cfg_mgmt_rd_wr_done,
      cfg_mgmt_wr_en => cfg_mgmt_wr_en,
      cfg_mgmt_wr_readonly => cfg_mgmt_wr_readonly,
      cfg_mgmt_wr_rw1c_as_rw => cfg_mgmt_wr_rw1c_as_rw,
      cfg_msg_data(15 downto 0) => \^cfg_msg_data\(15 downto 0),
      cfg_msg_received => cfg_msg_received,
      cfg_msg_received_assert_int_a => cfg_msg_received_assert_int_a,
      cfg_msg_received_assert_int_b => cfg_msg_received_assert_int_b,
      cfg_msg_received_assert_int_c => cfg_msg_received_assert_int_c,
      cfg_msg_received_assert_int_d => cfg_msg_received_assert_int_d,
      cfg_msg_received_deassert_int_a => cfg_msg_received_deassert_int_a,
      cfg_msg_received_deassert_int_b => cfg_msg_received_deassert_int_b,
      cfg_msg_received_deassert_int_c => cfg_msg_received_deassert_int_c,
      cfg_msg_received_deassert_int_d => cfg_msg_received_deassert_int_d,
      cfg_msg_received_err_cor => cfg_msg_received_err_cor,
      cfg_msg_received_err_fatal => cfg_msg_received_err_fatal,
      cfg_msg_received_err_non_fatal => cfg_msg_received_err_non_fatal,
      cfg_msg_received_pm_as_nak => cfg_msg_received_pm_as_nak,
      cfg_msg_received_pm_pme => cfg_msg_received_pm_pme,
      cfg_msg_received_pme_to_ack => cfg_msg_received_pme_to_ack,
      cfg_msg_received_setslotpowerlimit => cfg_msg_received_setslotpowerlimit,
      cfg_pcie_link_state(2 downto 0) => \^cfg_pcie_link_state\(2 downto 0),
      cfg_pciecap_interrupt_msgnum(4 downto 0) => cfg_pciecap_interrupt_msgnum(4 downto 0),
      cfg_pm_force_state(1 downto 0) => cfg_pm_force_state(1 downto 0),
      cfg_pm_force_state_en => cfg_pm_force_state_en,
      cfg_pm_halt_aspm_l0s => cfg_pm_halt_aspm_l0s,
      cfg_pm_halt_aspm_l1 => cfg_pm_halt_aspm_l1,
      cfg_pm_turnoff_ok_n => cfg_pm_turnoff_ok_n,
      cfg_pm_wake => cfg_pm_wake,
      cfg_pmcsr_pme_en => cfg_pmcsr_pme_en,
      cfg_pmcsr_pme_status => cfg_pmcsr_pme_status,
      cfg_pmcsr_powerstate(1 downto 0) => cfg_pmcsr_powerstate(1 downto 0),
      cfg_received_func_lvl_rst => cfg_received_func_lvl_rst,
      cfg_root_control_pme_int_en => cfg_root_control_pme_int_en,
      cfg_root_control_syserr_corr_err_en => cfg_root_control_syserr_corr_err_en,
      cfg_root_control_syserr_fatal_err_en => cfg_root_control_syserr_fatal_err_en,
      cfg_root_control_syserr_non_fatal_err_en => cfg_root_control_syserr_non_fatal_err_en,
      cfg_slot_control_electromech_il_ctl_pulse => cfg_slot_control_electromech_il_ctl_pulse,
      cfg_to_turnoff => cfg_to_turnoff,
      cfg_trn_pending => cfg_trn_pending,
      cfg_vc_tcvc_map(6 downto 0) => cfg_vc_tcvc_map(6 downto 0),
      dsc_detect => \rx_inst/rx_pipeline_inst/dsc_detect\,
      fc_cpld(11 downto 0) => fc_cpld(11 downto 0),
      fc_cplh(7 downto 0) => fc_cplh(7 downto 0),
      fc_npd(11 downto 0) => fc_npd(11 downto 0),
      fc_nph(7 downto 0) => fc_nph(7 downto 0),
      fc_pd(11 downto 0) => fc_pd(11 downto 0),
      fc_ph(7 downto 0) => fc_ph(7 downto 0),
      fc_sel(2 downto 0) => fc_sel(2 downto 0),
      gt_rxelecidle_q_reg => pcie_7x_i_n_24,
      lnk_up_thrtl => \tx_inst/xhdl12.tx_thrl_ctl_inst/lnk_up_thrtl\,
      lnk_up_thrtl_reg => pcie_7x_i_n_32,
      \out\ => \out\,
      pcie_drp_addr(8 downto 0) => pcie_drp_addr(8 downto 0),
      pcie_drp_clk => pcie_drp_clk,
      pcie_drp_di(15 downto 0) => pcie_drp_di(15 downto 0),
      pcie_drp_do(15 downto 0) => pcie_drp_do(15 downto 0),
      pcie_drp_en => pcie_drp_en,
      pcie_drp_rdy => pcie_drp_rdy,
      pcie_drp_we => pcie_drp_we,
      pipe_clk => pipe_clk,
      pipe_rx0_chanisaligned => pipe_rx0_chanisaligned,
      pipe_rx0_char_is_k(1 downto 0) => pipe_rx0_char_is_k(1 downto 0),
      pipe_rx0_data(15 downto 0) => pipe_rx0_data(15 downto 0),
      pipe_rx0_elec_idle => pipe_rx0_elec_idle,
      pipe_rx0_phy_status => pipe_rx0_phy_status,
      pipe_rx0_polarity => pipe_rx0_polarity,
      pipe_rx0_status(2 downto 0) => pipe_rx0_status(2 downto 0),
      pipe_rx0_valid => pipe_rx0_valid,
      pipe_rx1_chanisaligned => pipe_rx1_chanisaligned,
      pipe_rx1_char_is_k(1 downto 0) => pipe_rx1_char_is_k(1 downto 0),
      pipe_rx1_data(15 downto 0) => pipe_rx1_data(15 downto 0),
      pipe_rx1_elec_idle => pipe_rx1_elec_idle,
      pipe_rx1_phy_status => pipe_rx1_phy_status,
      pipe_rx1_polarity => pipe_rx1_polarity,
      pipe_rx1_status(2 downto 0) => pipe_rx1_status(2 downto 0),
      pipe_rx1_valid => pipe_rx1_valid,
      pipe_tx0_char_is_k(1 downto 0) => pipe_tx0_char_is_k(1 downto 0),
      pipe_tx0_compliance => pipe_tx0_compliance,
      pipe_tx0_data(15 downto 0) => pipe_tx0_data(15 downto 0),
      pipe_tx0_elec_idle => pipe_tx0_elec_idle,
      pipe_tx0_powerdown(1 downto 0) => pipe_tx0_powerdown(1 downto 0),
      pipe_tx1_char_is_k(1 downto 0) => pipe_tx1_char_is_k(1 downto 0),
      pipe_tx1_compliance => pipe_tx1_compliance,
      pipe_tx1_data(15 downto 0) => pipe_tx1_data(15 downto 0),
      pipe_tx1_elec_idle => pipe_tx1_elec_idle,
      pipe_tx1_powerdown(1 downto 0) => pipe_tx1_powerdown(1 downto 0),
      pipe_tx_deemph => pipe_tx_deemph,
      pipe_tx_margin(2 downto 0) => pipe_tx_margin(2 downto 0),
      pipe_tx_rate => pipe_tx_rate,
      pipe_tx_rcvr_det => pipe_tx_rcvr_det,
      pl_directed_change_done => pl_directed_change_done,
      pl_directed_link_auton => pl_directed_link_auton,
      pl_directed_link_change(1 downto 0) => pl_directed_link_change(1 downto 0),
      pl_directed_link_speed => pl_directed_link_speed,
      pl_directed_link_width(1 downto 0) => pl_directed_link_width(1 downto 0),
      pl_downstream_deemph_source => pl_downstream_deemph_source,
      pl_initial_link_width(2 downto 0) => pl_initial_link_width(2 downto 0),
      pl_lane_reversal_mode(1 downto 0) => pl_lane_reversal_mode(1 downto 0),
      pl_link_gen2_cap => pl_link_gen2_cap,
      pl_link_partner_gen2_supported => pl_link_partner_gen2_supported,
      pl_link_upcfg_cap => pl_link_upcfg_cap,
      pl_ltssm_state(5 downto 0) => pl_ltssm_state(5 downto 0),
      pl_phy_lnk_up => pl_phy_lnk_up,
      pl_received_hot_rst => pl_received_hot_rst,
      pl_rx_pm_state(1 downto 0) => pl_rx_pm_state(1 downto 0),
      pl_sel_lnk_rate => pl_sel_lnk_rate,
      pl_sel_lnk_width(1 downto 0) => pl_sel_lnk_width(1 downto 0),
      pl_transmit_hot_rst => pl_transmit_hot_rst,
      pl_tx_pm_state(2 downto 0) => pl_tx_pm_state(2 downto 0),
      pl_upstream_prefer_deemph => pl_upstream_prefer_deemph,
      ppm_L1_thrtl => \tx_inst/xhdl12.tx_thrl_ctl_inst/ppm_L1_thrtl\,
      ppm_L1_thrtl_reg => pcie_7x_i_n_13,
      ppm_L1_trig => \tx_inst/xhdl12.tx_thrl_ctl_inst/ppm_L1_trig\,
      reg_dsc_detect => \rx_inst/rx_pipeline_inst/reg_dsc_detect\,
      reg_tcfg_gnt => \tx_inst/xhdl12.tx_thrl_ctl_inst/reg_tcfg_gnt\,
      reg_to_turnoff => \tx_inst/xhdl12.tx_thrl_ctl_inst/reg_to_turnoff\,
      rsrc_rdy_filtered6_out => \rx_inst/rx_pipeline_inst/rsrc_rdy_filtered6_out\,
      rx_np_ok => rx_np_ok,
      rx_np_req => rx_np_req,
      src_in => src_in,
      sys_rst_n => sys_rst_n,
      tbuf_av_min_trig => \tx_inst/xhdl12.tx_thrl_ctl_inst/tbuf_av_min_trig\,
      tcfg_req_trig => \tx_inst/xhdl12.tx_thrl_ctl_inst/tcfg_req_trig\,
      trn_in_packet => \rx_inst/rx_pipeline_inst/trn_in_packet\,
      trn_in_packet_reg => pcie_7x_i_n_9,
      trn_lnk_up => trn_lnk_up,
      trn_rbar_hit(6 downto 0) => trn_rbar_hit(6 downto 0),
      trn_rd(63 downto 0) => trn_rd(63 downto 0),
      trn_rdst_rdy => trn_rdst_rdy,
      trn_recrc_err => trn_recrc_err,
      trn_reof => trn_reof,
      trn_rerrfwd => trn_rerrfwd,
      trn_rrem(0) => trn_rrem,
      trn_rsof => trn_rsof,
      trn_rsrc_dsc => trn_rsrc_dsc,
      trn_rsrc_dsc_d => \rx_inst/rx_pipeline_inst/trn_rsrc_dsc_d\,
      trn_rsrc_dsc_prev0 => \rx_inst/rx_pipeline_inst/trn_rsrc_dsc_prev0\,
      trn_tbuf_av(5 downto 0) => \^trn_tbuf_av\(5 downto 0),
      trn_tcfg_gnt => trn_tcfg_gnt,
      trn_tcfg_req => \^trn_tcfg_req\,
      trn_td(63 downto 0) => trn_td(63 downto 0),
      trn_tdst_rdy => trn_tdst_rdy,
      trn_teof => trn_teof,
      trn_trem(0) => trn_trem,
      trn_tsof => trn_tsof,
      trn_tsrc_rdy => trn_tsrc_rdy,
      tx_err_drop => tx_err_drop,
      user_reset_int_reg => user_reset_int_reg,
      \xhdl12.xhdl14.xhdl15.reg_to_turnoff_reg\ => pcie_7x_i_n_17
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_core_top is
  port (
    pl_ltssm_state : out STD_LOGIC_VECTOR ( 5 downto 0 );
    int_pipe_rxusrclk_out : out STD_LOGIC;
    pl_phy_lnk_up : out STD_LOGIC;
    user_reset_out : out STD_LOGIC;
    m_axis_rx_tvalid : out STD_LOGIC;
    Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pl_received_hot_rst : out STD_LOGIC;
    int_userclk1_out : out STD_LOGIC;
    cfg_aer_ecrc_check_en : out STD_LOGIC;
    cfg_aer_ecrc_gen_en : out STD_LOGIC;
    cfg_aer_rooterr_corr_err_received : out STD_LOGIC;
    cfg_aer_rooterr_corr_err_reporting_en : out STD_LOGIC;
    cfg_aer_rooterr_fatal_err_received : out STD_LOGIC;
    cfg_aer_rooterr_fatal_err_reporting_en : out STD_LOGIC;
    cfg_aer_rooterr_non_fatal_err_received : out STD_LOGIC;
    cfg_aer_rooterr_non_fatal_err_reporting_en : out STD_LOGIC;
    cfg_bridge_serr_en : out STD_LOGIC;
    cfg_command : out STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_dcommand2 : out STD_LOGIC_VECTOR ( 11 downto 0 );
    cfg_dcommand : out STD_LOGIC_VECTOR ( 14 downto 0 );
    cfg_dstatus : out STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_interrupt_msienable : out STD_LOGIC;
    cfg_interrupt_msixenable : out STD_LOGIC;
    cfg_interrupt_msixfm : out STD_LOGIC;
    cfg_lcommand : out STD_LOGIC_VECTOR ( 10 downto 0 );
    cfg_lstatus : out STD_LOGIC_VECTOR ( 9 downto 0 );
    cfg_msg_received : out STD_LOGIC;
    cfg_msg_received_assert_int_a : out STD_LOGIC;
    cfg_msg_received_assert_int_b : out STD_LOGIC;
    cfg_msg_received_assert_int_c : out STD_LOGIC;
    cfg_msg_received_assert_int_d : out STD_LOGIC;
    cfg_msg_received_deassert_int_a : out STD_LOGIC;
    cfg_msg_received_deassert_int_b : out STD_LOGIC;
    cfg_msg_received_deassert_int_c : out STD_LOGIC;
    cfg_msg_received_deassert_int_d : out STD_LOGIC;
    cfg_msg_received_err_cor : out STD_LOGIC;
    cfg_msg_received_err_fatal : out STD_LOGIC;
    cfg_msg_received_err_non_fatal : out STD_LOGIC;
    cfg_msg_received_pm_as_nak : out STD_LOGIC;
    cfg_to_turnoff : out STD_LOGIC;
    cfg_msg_received_pme_to_ack : out STD_LOGIC;
    cfg_msg_received_pm_pme : out STD_LOGIC;
    cfg_msg_received_setslotpowerlimit : out STD_LOGIC;
    cfg_pmcsr_pme_en : out STD_LOGIC;
    cfg_pmcsr_pme_status : out STD_LOGIC;
    cfg_root_control_pme_int_en : out STD_LOGIC;
    cfg_root_control_syserr_corr_err_en : out STD_LOGIC;
    cfg_root_control_syserr_fatal_err_en : out STD_LOGIC;
    cfg_root_control_syserr_non_fatal_err_en : out STD_LOGIC;
    cfg_slot_control_electromech_il_ctl_pulse : out STD_LOGIC;
    pcie_drp_rdy : out STD_LOGIC;
    pl_directed_change_done : out STD_LOGIC;
    pl_link_gen2_cap : out STD_LOGIC;
    pl_link_partner_gen2_supported : out STD_LOGIC;
    pl_link_upcfg_cap : out STD_LOGIC;
    pl_sel_lnk_rate : out STD_LOGIC;
    tx_cfg_req : out STD_LOGIC;
    tx_err_drop : out STD_LOGIC;
    fc_cpld : out STD_LOGIC_VECTOR ( 11 downto 0 );
    fc_npd : out STD_LOGIC_VECTOR ( 11 downto 0 );
    fc_pd : out STD_LOGIC_VECTOR ( 11 downto 0 );
    cfg_msg_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pcie_drp_do : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_pmcsr_powerstate : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_lane_reversal_mode : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_rx_pm_state : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_sel_lnk_width : out STD_LOGIC_VECTOR ( 1 downto 0 );
    cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_pcie_link_state : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pl_initial_link_width : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pl_tx_pm_state : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_mgmt_do : out STD_LOGIC_VECTOR ( 31 downto 0 );
    tx_buf_av : out STD_LOGIC_VECTOR ( 5 downto 0 );
    cfg_vc_tcvc_map : out STD_LOGIC_VECTOR ( 6 downto 0 );
    cfg_interrupt_do : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_cplh : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_nph : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_ph : out STD_LOGIC_VECTOR ( 7 downto 0 );
    pipe_txoutclk_out : out STD_LOGIC;
    int_dclk_out : out STD_LOGIC;
    int_mmcm_lock_out : out STD_LOGIC;
    \FSM_onehot_fsm_reg[10]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_cpll_lock : out STD_LOGIC_VECTOR ( 1 downto 0 );
    QRST_IDLE : out STD_LOGIC;
    int_qplllock_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_qrst_fsm : out STD_LOGIC_VECTOR ( 3 downto 0 );
    ext_ch_gt_drprdy : out STD_LOGIC_VECTOR ( 1 downto 0 );
    ext_ch_gt_drpdo : out STD_LOGIC_VECTOR ( 31 downto 0 );
    gen3_reg : out STD_LOGIC;
    int_qplloutclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    int_qplloutrefclk_out : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_pclk_sel_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxstatus : out STD_LOGIC_VECTOR ( 5 downto 0 );
    \FSM_onehot_txsync_fsm.fsm_tx_reg[6]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    pipe_sync_fsm_rx : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxphaligndone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_eyescandataerror : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_txn : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_txp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxcommadet : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxdlysresetdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxprbserr : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_txdlysresetdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_txphaligndone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_txphinitdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxbufstatus : out STD_LOGIC_VECTOR ( 5 downto 0 );
    pipe_dmonitorout : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_rxdisperr : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_rxnotintable : out STD_LOGIC_VECTOR ( 15 downto 0 );
    \fsm_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
    \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
    user_lnk_up : out STD_LOGIC;
    m_axis_rx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_rx_tkeep : out STD_LOGIC_VECTOR ( 1 downto 0 );
    m_axis_rx_tlast : out STD_LOGIC;
    m_axis_rx_tuser : out STD_LOGIC_VECTOR ( 12 downto 0 );
    s_axis_tx_tready : out STD_LOGIC;
    cfg_bus_number : out STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_device_number : out STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_function_number : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_rst_fsm : out STD_LOGIC_VECTOR ( 3 downto 0 );
    pipe_rate_fsm : out STD_LOGIC_VECTOR ( 9 downto 0 );
    pipe_rate_idle : out STD_LOGIC;
    gt_ch_drp_rdy : out STD_LOGIC_VECTOR ( 1 downto 0 );
    cfg_mgmt_rd_wr_done : out STD_LOGIC;
    cfg_err_aer_headerlog_set : out STD_LOGIC;
    cfg_err_cpl_rdy : out STD_LOGIC;
    cfg_interrupt_rdy : out STD_LOGIC;
    cfg_received_func_lvl_rst : out STD_LOGIC;
    m_axis_rx_tready : in STD_LOGIC;
    ext_ch_gt_drpaddr : in STD_LOGIC_VECTOR ( 17 downto 0 );
    sys_rst_n : in STD_LOGIC;
    pcie_drp_clk : in STD_LOGIC;
    pcie_drp_en : in STD_LOGIC;
    pcie_drp_we : in STD_LOGIC;
    pl_directed_link_auton : in STD_LOGIC;
    pl_directed_link_speed : in STD_LOGIC;
    pl_downstream_deemph_source : in STD_LOGIC;
    pl_transmit_hot_rst : in STD_LOGIC;
    pl_upstream_prefer_deemph : in STD_LOGIC;
    rx_np_ok : in STD_LOGIC;
    rx_np_req : in STD_LOGIC;
    cfg_err_aer_headerlog : in STD_LOGIC_VECTOR ( 127 downto 0 );
    pcie_drp_di : in STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_pm_force_state : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_directed_link_change : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_directed_link_width : in STD_LOGIC_VECTOR ( 1 downto 0 );
    cfg_ds_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 );
    fc_sel : in STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_mgmt_di : in STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_err_tlp_cpl_header : in STD_LOGIC_VECTOR ( 47 downto 0 );
    cfg_aer_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_ds_device_number : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_pciecap_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 );
    cfg_ds_bus_number : in STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_interrupt_di : in STD_LOGIC_VECTOR ( 7 downto 0 );
    pcie_drp_addr : in STD_LOGIC_VECTOR ( 8 downto 0 );
    cfg_mgmt_dwaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
    sys_clk : in STD_LOGIC;
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_txinhibit : in STD_LOGIC_VECTOR ( 1 downto 0 );
    int_pclk_sel_slave : in STD_LOGIC_VECTOR ( 1 downto 0 );
    s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axis_tx_tlast : in STD_LOGIC;
    s_axis_tx_tvalid : in STD_LOGIC;
    s_axis_tx_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
    s_axis_tx_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
    tx_cfg_gnt : in STD_LOGIC;
    cfg_turnoff_ok : in STD_LOGIC;
    cfg_mgmt_byte_en : in STD_LOGIC_VECTOR ( 3 downto 0 );
    ext_ch_gt_drpen : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ext_ch_gt_drpwe : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ext_ch_gt_drpdi : in STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_trn_pending : in STD_LOGIC;
    cfg_mgmt_wr_rw1c_as_rw : in STD_LOGIC;
    cfg_mgmt_wr_readonly : in STD_LOGIC;
    cfg_mgmt_wr_en : in STD_LOGIC;
    cfg_mgmt_rd_en : in STD_LOGIC;
    cfg_err_malformed : in STD_LOGIC;
    cfg_err_cor : in STD_LOGIC;
    cfg_err_ur : in STD_LOGIC;
    cfg_err_ecrc : in STD_LOGIC;
    cfg_err_cpl_timeout : in STD_LOGIC;
    cfg_err_cpl_abort : in STD_LOGIC;
    cfg_err_cpl_unexpect : in STD_LOGIC;
    cfg_err_poisoned : in STD_LOGIC;
    cfg_err_atomic_egress_blocked : in STD_LOGIC;
    cfg_err_mc_blocked : in STD_LOGIC;
    cfg_err_internal_uncor : in STD_LOGIC;
    cfg_err_internal_cor : in STD_LOGIC;
    cfg_err_posted : in STD_LOGIC;
    cfg_err_locked : in STD_LOGIC;
    cfg_err_norecovery : in STD_LOGIC;
    cfg_interrupt : in STD_LOGIC;
    cfg_interrupt_assert : in STD_LOGIC;
    cfg_interrupt_stat : in STD_LOGIC;
    cfg_pm_halt_aspm_l0s : in STD_LOGIC;
    cfg_pm_halt_aspm_l1 : in STD_LOGIC;
    cfg_pm_force_state_en : in STD_LOGIC;
    cfg_pm_wake : in STD_LOGIC;
    pipe_mmcm_rst_n : in STD_LOGIC
  );
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_core_top : entity is "spec7_pcie_7x_0_core_top";
end spec7_pcie_7x_0_spec7_pcie_7x_0_core_top;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_core_top is
  signal bridge_reset_int : STD_LOGIC;
  signal cfg_mgmt_byte_en_n : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal gt_top_i_n_146 : STD_LOGIC;
  signal \^int_pipe_rxusrclk_out\ : STD_LOGIC;
  signal \^int_userclk1_out\ : STD_LOGIC;
  signal \ltssm_reg1_reg[0]_srl2_n_0\ : STD_LOGIC;
  signal \ltssm_reg1_reg[1]_srl2_n_0\ : STD_LOGIC;
  signal \ltssm_reg1_reg[2]_srl2_n_0\ : STD_LOGIC;
  signal \ltssm_reg1_reg[3]_srl2_n_0\ : STD_LOGIC;
  signal \ltssm_reg1_reg[4]_srl2_n_0\ : STD_LOGIC;
  signal \ltssm_reg1_reg[5]_srl2_n_0\ : STD_LOGIC;
  signal ltssm_reg2 : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal pcie_top_i_n_4 : STD_LOGIC;
  signal pipe_rx0_chanisaligned_gt : STD_LOGIC;
  signal pipe_rx0_char_is_k_gt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_rx0_data_gt : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_rx0_elec_idle_gt : STD_LOGIC;
  signal pipe_rx0_phy_status_gt : STD_LOGIC;
  signal pipe_rx0_polarity_gt : STD_LOGIC;
  signal pipe_rx0_status_gt : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal pipe_rx0_valid_gt : STD_LOGIC;
  signal pipe_rx1_chanisaligned_gt : STD_LOGIC;
  signal pipe_rx1_char_is_k_gt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_rx1_data_gt : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_rx1_elec_idle_gt : STD_LOGIC;
  signal pipe_rx1_phy_status_gt : STD_LOGIC;
  signal pipe_rx1_polarity_gt : STD_LOGIC;
  signal pipe_rx1_status_gt : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal pipe_rx1_valid_gt : STD_LOGIC;
  signal pipe_tx0_char_is_k_gt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx0_compliance_gt : STD_LOGIC;
  signal pipe_tx0_data_gt : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx0_elec_idle_gt : STD_LOGIC;
  signal pipe_tx0_powerdown_gt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx1_char_is_k_gt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx1_compliance_gt : STD_LOGIC;
  signal pipe_tx1_data_gt : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal pipe_tx1_elec_idle_gt : STD_LOGIC;
  signal pipe_tx1_powerdown_gt : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal pipe_tx_deemph_gt : STD_LOGIC;
  signal pipe_tx_margin_gt : STD_LOGIC_VECTOR ( 2 downto 0 );
  signal pipe_tx_rate_gt : STD_LOGIC;
  signal pipe_tx_rcvr_det_gt : STD_LOGIC;
  signal \^pl_ltssm_state\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \^pl_phy_lnk_up\ : STD_LOGIC;
  signal pl_phy_lnk_up_int : STD_LOGIC;
  signal pl_phy_lnk_up_sync : STD_LOGIC;
  signal \^pl_received_hot_rst\ : STD_LOGIC;
  signal pl_received_hot_rst_int : STD_LOGIC;
  signal pl_received_hot_rst_sync : STD_LOGIC;
  signal store_ltssm : STD_LOGIC;
  attribute DONT_TOUCH : boolean;
  attribute DONT_TOUCH of store_ltssm : signal is std.standard.true;
  signal store_ltssm_inferred_i_2_n_0 : STD_LOGIC;
  signal store_ltssm_inferred_i_3_n_0 : STD_LOGIC;
  signal sys_rst_n_0 : STD_LOGIC;
  signal trn_lnk_up : STD_LOGIC;
  attribute RTL_KEEP : string;
  attribute RTL_KEEP of trn_lnk_up : signal is "true";
  attribute async_reg : string;
  attribute async_reg of trn_lnk_up : signal is "true";
  signal user_lnk_up_d : STD_LOGIC;
  attribute RTL_KEEP of user_lnk_up_d : signal is "true";
  attribute async_reg of user_lnk_up_d : signal is "true";
  attribute equivalent_register_removal : string;
  attribute equivalent_register_removal of user_lnk_up_d : signal is "no";
  signal user_lnk_up_int : STD_LOGIC;
  attribute RTL_KEEP of user_lnk_up_int : signal is "true";
  attribute async_reg of user_lnk_up_int : signal is "true";
  attribute equivalent_register_removal of user_lnk_up_int : signal is "no";
  signal \^user_reset_out\ : STD_LOGIC;
  signal user_reset_out_i_1_n_0 : STD_LOGIC;
  attribute srl_bus_name : string;
  attribute srl_bus_name of \ltssm_reg1_reg[0]_srl2\ : label is "U0/\inst/ltssm_reg1_reg ";
  attribute srl_name : string;
  attribute srl_name of \ltssm_reg1_reg[0]_srl2\ : label is "U0/\inst/ltssm_reg1_reg[0]_srl2 ";
  attribute srl_bus_name of \ltssm_reg1_reg[1]_srl2\ : label is "U0/\inst/ltssm_reg1_reg ";
  attribute srl_name of \ltssm_reg1_reg[1]_srl2\ : label is "U0/\inst/ltssm_reg1_reg[1]_srl2 ";
  attribute srl_bus_name of \ltssm_reg1_reg[2]_srl2\ : label is "U0/\inst/ltssm_reg1_reg ";
  attribute srl_name of \ltssm_reg1_reg[2]_srl2\ : label is "U0/\inst/ltssm_reg1_reg[2]_srl2 ";
  attribute srl_bus_name of \ltssm_reg1_reg[3]_srl2\ : label is "U0/\inst/ltssm_reg1_reg ";
  attribute srl_name of \ltssm_reg1_reg[3]_srl2\ : label is "U0/\inst/ltssm_reg1_reg[3]_srl2 ";
  attribute srl_bus_name of \ltssm_reg1_reg[4]_srl2\ : label is "U0/\inst/ltssm_reg1_reg ";
  attribute srl_name of \ltssm_reg1_reg[4]_srl2\ : label is "U0/\inst/ltssm_reg1_reg[4]_srl2 ";
  attribute srl_bus_name of \ltssm_reg1_reg[5]_srl2\ : label is "U0/\inst/ltssm_reg1_reg ";
  attribute srl_name of \ltssm_reg1_reg[5]_srl2\ : label is "U0/\inst/ltssm_reg1_reg[5]_srl2 ";
  attribute DEST_SYNC_FF : integer;
  attribute DEST_SYNC_FF of pl_phy_lnk_up_cdc : label is 2;
  attribute INIT_SYNC_FF : integer;
  attribute INIT_SYNC_FF of pl_phy_lnk_up_cdc : label is 0;
  attribute SIM_ASSERT_CHK : integer;
  attribute SIM_ASSERT_CHK of pl_phy_lnk_up_cdc : label is 0;
  attribute SRC_INPUT_REG : integer;
  attribute SRC_INPUT_REG of pl_phy_lnk_up_cdc : label is 0;
  attribute VERSION : integer;
  attribute VERSION of pl_phy_lnk_up_cdc : label is 0;
  attribute XPM_CDC : string;
  attribute XPM_CDC of pl_phy_lnk_up_cdc : label is "SINGLE";
  attribute XPM_MODULE : string;
  attribute XPM_MODULE of pl_phy_lnk_up_cdc : label is "TRUE";
  attribute DEST_SYNC_FF of pl_received_hot_rst_cdc : label is 2;
  attribute INIT_SYNC_FF of pl_received_hot_rst_cdc : label is 0;
  attribute SIM_ASSERT_CHK of pl_received_hot_rst_cdc : label is 0;
  attribute SRC_INPUT_REG of pl_received_hot_rst_cdc : label is 0;
  attribute VERSION of pl_received_hot_rst_cdc : label is 0;
  attribute XPM_CDC of pl_received_hot_rst_cdc : label is "SINGLE";
  attribute XPM_MODULE of pl_received_hot_rst_cdc : label is "TRUE";
  attribute ASYNC_REG_boolean : boolean;
  attribute ASYNC_REG_boolean of user_lnk_up_d_reg : label is std.standard.true;
  attribute KEEP : string;
  attribute KEEP of user_lnk_up_d_reg : label is "yes";
  attribute equivalent_register_removal of user_lnk_up_d_reg : label is "no";
  attribute ASYNC_REG_boolean of user_lnk_up_int_reg : label is std.standard.true;
  attribute KEEP of user_lnk_up_int_reg : label is "yes";
  attribute equivalent_register_removal of user_lnk_up_int_reg : label is "no";
begin
  int_pipe_rxusrclk_out <= \^int_pipe_rxusrclk_out\;
  int_userclk1_out <= \^int_userclk1_out\;
  pl_ltssm_state(5 downto 0) <= \^pl_ltssm_state\(5 downto 0);
  pl_phy_lnk_up <= \^pl_phy_lnk_up\;
  pl_received_hot_rst <= \^pl_received_hot_rst\;
  user_lnk_up <= user_lnk_up_int;
  user_reset_out <= \^user_reset_out\;
gt_top_i: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_gt_top
     port map (
      CLK => int_dclk_out,
      D(1 downto 0) => pipe_cpll_lock(1 downto 0),
      \FSM_onehot_fsm_reg[10]\(1 downto 0) => \FSM_onehot_fsm_reg[10]\(1 downto 0),
      \FSM_onehot_txsync_fsm.fsm_tx_reg[6]\(5 downto 0) => \FSM_onehot_txsync_fsm.fsm_tx_reg[6]\(5 downto 0),
      \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\(5 downto 0) => \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\(5 downto 0),
      Q(0) => QRST_IDLE,
      QPLL_QPLLLOCK => int_qplllock_out(0),
      SYNC_GEN3 => gen3_reg,
      SYNC_MMCM_LOCK => int_mmcm_lock_out,
      ext_ch_gt_drpaddr(17 downto 0) => ext_ch_gt_drpaddr(17 downto 0),
      ext_ch_gt_drpdi(31 downto 0) => ext_ch_gt_drpdi(31 downto 0),
      ext_ch_gt_drpdo(31 downto 0) => ext_ch_gt_drpdo(31 downto 0),
      ext_ch_gt_drpen(1 downto 0) => ext_ch_gt_drpen(1 downto 0),
      ext_ch_gt_drprdy(1 downto 0) => ext_ch_gt_drprdy(1 downto 0),
      ext_ch_gt_drpwe(1 downto 0) => ext_ch_gt_drpwe(1 downto 0),
      \fsm_reg[2]\(2 downto 0) => Q(2 downto 0),
      \fsm_reg[2]_0\(2 downto 0) => \fsm_reg[2]\(2 downto 0),
      gt_ch_drp_rdy(1 downto 0) => gt_ch_drp_rdy(1 downto 0),
      \gt_rx_status_q_reg[2]\(2 downto 0) => pipe_rx0_status_gt(2 downto 0),
      \gt_rx_status_q_reg[2]_0\(2 downto 0) => pipe_rx1_status_gt(2 downto 0),
      \gt_rxdata_q_reg[15]\(15 downto 0) => pipe_rx0_data_gt(15 downto 0),
      \gt_rxdata_q_reg[15]_0\(15 downto 0) => pipe_rx1_data_gt(15 downto 0),
      int_pclk_sel_slave(1 downto 0) => int_pclk_sel_slave(1 downto 0),
      int_qplloutclk_out(0) => int_qplloutclk_out(0),
      int_qplloutrefclk_out(0) => int_qplloutrefclk_out(0),
      mmcm_i => \^int_userclk1_out\,
      pci_exp_rxn(1 downto 0) => pci_exp_rxn(1 downto 0),
      pci_exp_rxp(1 downto 0) => pci_exp_rxp(1 downto 0),
      pci_exp_txn(1 downto 0) => pci_exp_txn(1 downto 0),
      pci_exp_txp(1 downto 0) => pci_exp_txp(1 downto 0),
      pclk_sel_reg => \^int_pipe_rxusrclk_out\,
      pclk_sel_reg_0(1 downto 0) => pipe_pclk_sel_out(1 downto 0),
      pipe_dmonitorout(15 downto 0) => pipe_dmonitorout(15 downto 0),
      pipe_eyescandataerror(1 downto 0) => pipe_eyescandataerror(1 downto 0),
      pipe_mmcm_rst_n => pipe_mmcm_rst_n,
      pipe_qrst_fsm(3 downto 0) => pipe_qrst_fsm(3 downto 0),
      pipe_rate_fsm(9 downto 0) => pipe_rate_fsm(9 downto 0),
      pipe_rate_idle => pipe_rate_idle,
      pipe_rst_fsm(3 downto 0) => pipe_rst_fsm(3 downto 0),
      pipe_rx0_chanisaligned => pipe_rx0_chanisaligned_gt,
      pipe_rx0_char_is_k(1 downto 0) => pipe_rx0_char_is_k_gt(1 downto 0),
      pipe_rx0_elec_idle => pipe_rx0_elec_idle_gt,
      pipe_rx0_phy_status => pipe_rx0_phy_status_gt,
      pipe_rx0_polarity => pipe_rx0_polarity_gt,
      pipe_rx0_valid_gt => pipe_rx0_valid_gt,
      pipe_rx1_chanisaligned => pipe_rx1_chanisaligned_gt,
      pipe_rx1_char_is_k(1 downto 0) => pipe_rx1_char_is_k_gt(1 downto 0),
      pipe_rx1_elec_idle => pipe_rx1_elec_idle_gt,
      pipe_rx1_phy_status => pipe_rx1_phy_status_gt,
      pipe_rx1_polarity => pipe_rx1_polarity_gt,
      pipe_rx1_valid_gt => pipe_rx1_valid_gt,
      pipe_rxbufstatus(5 downto 0) => pipe_rxbufstatus(5 downto 0),
      pipe_rxcommadet(1 downto 0) => pipe_rxcommadet(1 downto 0),
      pipe_rxdisperr(15 downto 0) => pipe_rxdisperr(15 downto 0),
      pipe_rxdlysresetdone(1 downto 0) => pipe_rxdlysresetdone(1 downto 0),
      pipe_rxnotintable(15 downto 0) => pipe_rxnotintable(15 downto 0),
      pipe_rxoutclk_out(1 downto 0) => pipe_rxoutclk_out(1 downto 0),
      pipe_rxphaligndone(1 downto 0) => pipe_rxphaligndone(1 downto 0),
      pipe_rxprbserr(1 downto 0) => pipe_rxprbserr(1 downto 0),
      pipe_rxstatus(5 downto 0) => pipe_rxstatus(5 downto 0),
      pipe_sync_fsm_rx(1 downto 0) => pipe_sync_fsm_rx(1 downto 0),
      pipe_tx0_char_is_k(1 downto 0) => pipe_tx0_char_is_k_gt(1 downto 0),
      pipe_tx0_compliance => pipe_tx0_compliance_gt,
      pipe_tx0_data(15 downto 0) => pipe_tx0_data_gt(15 downto 0),
      pipe_tx0_elec_idle => pipe_tx0_elec_idle_gt,
      pipe_tx0_powerdown(1 downto 0) => pipe_tx0_powerdown_gt(1 downto 0),
      pipe_tx1_char_is_k(1 downto 0) => pipe_tx1_char_is_k_gt(1 downto 0),
      pipe_tx1_compliance => pipe_tx1_compliance_gt,
      pipe_tx1_data(15 downto 0) => pipe_tx1_data_gt(15 downto 0),
      pipe_tx1_elec_idle => pipe_tx1_elec_idle_gt,
      pipe_tx1_powerdown(1 downto 0) => pipe_tx1_powerdown_gt(1 downto 0),
      pipe_tx_deemph => pipe_tx_deemph_gt,
      pipe_tx_margin(2 downto 0) => pipe_tx_margin_gt(2 downto 0),
      pipe_tx_rate => pipe_tx_rate_gt,
      pipe_tx_rcvr_det => pipe_tx_rcvr_det_gt,
      pipe_txdlysresetdone(1 downto 0) => pipe_txdlysresetdone(1 downto 0),
      pipe_txinhibit(1 downto 0) => pipe_txinhibit(1 downto 0),
      pipe_txoutclk_out => pipe_txoutclk_out,
      pipe_txphaligndone(1 downto 0) => pipe_txphaligndone(1 downto 0),
      pipe_txphinitdone(1 downto 0) => pipe_txphinitdone(1 downto 0),
      pl_ltssm_state(5 downto 0) => \^pl_ltssm_state\(5 downto 0),
      reset_n_reg2_reg => sys_rst_n,
      sys_clk => sys_clk,
      sys_rst_n => sys_rst_n_0,
      sys_rst_n_0 => gt_top_i_n_146
    );
\ltssm_reg1_reg[0]_srl2\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => \^int_pipe_rxusrclk_out\,
      D => \^pl_ltssm_state\(0),
      Q => \ltssm_reg1_reg[0]_srl2_n_0\
    );
\ltssm_reg1_reg[1]_srl2\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => \^int_pipe_rxusrclk_out\,
      D => \^pl_ltssm_state\(1),
      Q => \ltssm_reg1_reg[1]_srl2_n_0\
    );
\ltssm_reg1_reg[2]_srl2\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => \^int_pipe_rxusrclk_out\,
      D => \^pl_ltssm_state\(2),
      Q => \ltssm_reg1_reg[2]_srl2_n_0\
    );
\ltssm_reg1_reg[3]_srl2\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => \^int_pipe_rxusrclk_out\,
      D => \^pl_ltssm_state\(3),
      Q => \ltssm_reg1_reg[3]_srl2_n_0\
    );
\ltssm_reg1_reg[4]_srl2\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => \^int_pipe_rxusrclk_out\,
      D => \^pl_ltssm_state\(4),
      Q => \ltssm_reg1_reg[4]_srl2_n_0\
    );
\ltssm_reg1_reg[5]_srl2\: unisim.vcomponents.SRL16E
    generic map(
      INIT => X"0000"
    )
        port map (
      A0 => '1',
      A1 => '0',
      A2 => '0',
      A3 => '0',
      CE => '1',
      CLK => \^int_pipe_rxusrclk_out\,
      D => \^pl_ltssm_state\(5),
      Q => \ltssm_reg1_reg[5]_srl2_n_0\
    );
\ltssm_reg2_reg[0]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^int_pipe_rxusrclk_out\,
      CE => '1',
      D => \ltssm_reg1_reg[0]_srl2_n_0\,
      Q => ltssm_reg2(0),
      R => '0'
    );
\ltssm_reg2_reg[1]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^int_pipe_rxusrclk_out\,
      CE => '1',
      D => \ltssm_reg1_reg[1]_srl2_n_0\,
      Q => ltssm_reg2(1),
      R => '0'
    );
\ltssm_reg2_reg[2]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^int_pipe_rxusrclk_out\,
      CE => '1',
      D => \ltssm_reg1_reg[2]_srl2_n_0\,
      Q => ltssm_reg2(2),
      R => '0'
    );
\ltssm_reg2_reg[3]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^int_pipe_rxusrclk_out\,
      CE => '1',
      D => \ltssm_reg1_reg[3]_srl2_n_0\,
      Q => ltssm_reg2(3),
      R => '0'
    );
\ltssm_reg2_reg[4]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^int_pipe_rxusrclk_out\,
      CE => '1',
      D => \ltssm_reg1_reg[4]_srl2_n_0\,
      Q => ltssm_reg2(4),
      R => '0'
    );
\ltssm_reg2_reg[5]\: unisim.vcomponents.FDRE
    generic map(
      INIT => '0'
    )
        port map (
      C => \^int_pipe_rxusrclk_out\,
      CE => '1',
      D => \ltssm_reg1_reg[5]_srl2_n_0\,
      Q => ltssm_reg2(5),
      R => '0'
    );
pcie_block_i_i_36: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_mgmt_byte_en(3),
      O => cfg_mgmt_byte_en_n(3)
    );
pcie_block_i_i_37: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_mgmt_byte_en(2),
      O => cfg_mgmt_byte_en_n(2)
    );
pcie_block_i_i_38: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_mgmt_byte_en(1),
      O => cfg_mgmt_byte_en_n(1)
    );
pcie_block_i_i_39: unisim.vcomponents.LUT1
    generic map(
      INIT => X"1"
    )
        port map (
      I0 => cfg_mgmt_byte_en(0),
      O => cfg_mgmt_byte_en_n(0)
    );
pcie_top_i: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_pcie_top
     port map (
      CLK => \^int_userclk1_out\,
      bridge_reset_int => bridge_reset_int,
      cfg_aer_ecrc_check_en => cfg_aer_ecrc_check_en,
      cfg_aer_ecrc_gen_en => cfg_aer_ecrc_gen_en,
      cfg_aer_interrupt_msgnum(4 downto 0) => cfg_aer_interrupt_msgnum(4 downto 0),
      cfg_aer_rooterr_corr_err_received => cfg_aer_rooterr_corr_err_received,
      cfg_aer_rooterr_corr_err_reporting_en => cfg_aer_rooterr_corr_err_reporting_en,
      cfg_aer_rooterr_fatal_err_received => cfg_aer_rooterr_fatal_err_received,
      cfg_aer_rooterr_fatal_err_reporting_en => cfg_aer_rooterr_fatal_err_reporting_en,
      cfg_aer_rooterr_non_fatal_err_received => cfg_aer_rooterr_non_fatal_err_received,
      cfg_aer_rooterr_non_fatal_err_reporting_en => cfg_aer_rooterr_non_fatal_err_reporting_en,
      cfg_bridge_serr_en => cfg_bridge_serr_en,
      cfg_bus_number(7 downto 0) => cfg_bus_number(7 downto 0),
      cfg_command(4 downto 0) => cfg_command(4 downto 0),
      cfg_dcommand(14 downto 0) => cfg_dcommand(14 downto 0),
      cfg_dcommand2(11 downto 0) => cfg_dcommand2(11 downto 0),
      cfg_device_number(4 downto 0) => cfg_device_number(4 downto 0),
      cfg_ds_bus_number(7 downto 0) => cfg_ds_bus_number(7 downto 0),
      cfg_ds_device_number(4 downto 0) => cfg_ds_device_number(4 downto 0),
      cfg_ds_function_number(2 downto 0) => cfg_ds_function_number(2 downto 0),
      cfg_dsn(63 downto 0) => cfg_dsn(63 downto 0),
      cfg_dstatus(3 downto 0) => cfg_dstatus(3 downto 0),
      cfg_err_aer_headerlog(127 downto 0) => cfg_err_aer_headerlog(127 downto 0),
      cfg_err_aer_headerlog_set => cfg_err_aer_headerlog_set,
      cfg_err_atomic_egress_blocked => cfg_err_atomic_egress_blocked,
      cfg_err_cor => cfg_err_cor,
      cfg_err_cpl_abort => cfg_err_cpl_abort,
      cfg_err_cpl_rdy => cfg_err_cpl_rdy,
      cfg_err_cpl_timeout => cfg_err_cpl_timeout,
      cfg_err_cpl_unexpect => cfg_err_cpl_unexpect,
      cfg_err_ecrc => cfg_err_ecrc,
      cfg_err_internal_cor => cfg_err_internal_cor,
      cfg_err_internal_uncor => cfg_err_internal_uncor,
      cfg_err_locked => cfg_err_locked,
      cfg_err_malformed => cfg_err_malformed,
      cfg_err_mc_blocked => cfg_err_mc_blocked,
      cfg_err_norecovery => cfg_err_norecovery,
      cfg_err_poisoned => cfg_err_poisoned,
      cfg_err_posted => cfg_err_posted,
      cfg_err_tlp_cpl_header(47 downto 0) => cfg_err_tlp_cpl_header(47 downto 0),
      cfg_err_ur => cfg_err_ur,
      cfg_function_number(2 downto 0) => cfg_function_number(2 downto 0),
      cfg_interrupt => cfg_interrupt,
      cfg_interrupt_assert => cfg_interrupt_assert,
      cfg_interrupt_di(7 downto 0) => cfg_interrupt_di(7 downto 0),
      cfg_interrupt_do(7 downto 0) => cfg_interrupt_do(7 downto 0),
      cfg_interrupt_mmenable(2 downto 0) => cfg_interrupt_mmenable(2 downto 0),
      cfg_interrupt_msienable => cfg_interrupt_msienable,
      cfg_interrupt_msixenable => cfg_interrupt_msixenable,
      cfg_interrupt_msixfm => cfg_interrupt_msixfm,
      cfg_interrupt_rdy => cfg_interrupt_rdy,
      cfg_interrupt_stat => cfg_interrupt_stat,
      cfg_lcommand(10 downto 0) => cfg_lcommand(10 downto 0),
      cfg_lstatus(9 downto 0) => cfg_lstatus(9 downto 0),
      cfg_mgmt_byte_en_n(3 downto 0) => cfg_mgmt_byte_en_n(3 downto 0),
      cfg_mgmt_di(31 downto 0) => cfg_mgmt_di(31 downto 0),
      cfg_mgmt_do(31 downto 0) => cfg_mgmt_do(31 downto 0),
      cfg_mgmt_dwaddr(9 downto 0) => cfg_mgmt_dwaddr(9 downto 0),
      cfg_mgmt_rd_en => cfg_mgmt_rd_en,
      cfg_mgmt_rd_wr_done => cfg_mgmt_rd_wr_done,
      cfg_mgmt_wr_en => cfg_mgmt_wr_en,
      cfg_mgmt_wr_readonly => cfg_mgmt_wr_readonly,
      cfg_mgmt_wr_rw1c_as_rw => cfg_mgmt_wr_rw1c_as_rw,
      cfg_msg_data(15 downto 0) => cfg_msg_data(15 downto 0),
      cfg_msg_received => cfg_msg_received,
      cfg_msg_received_assert_int_a => cfg_msg_received_assert_int_a,
      cfg_msg_received_assert_int_b => cfg_msg_received_assert_int_b,
      cfg_msg_received_assert_int_c => cfg_msg_received_assert_int_c,
      cfg_msg_received_assert_int_d => cfg_msg_received_assert_int_d,
      cfg_msg_received_deassert_int_a => cfg_msg_received_deassert_int_a,
      cfg_msg_received_deassert_int_b => cfg_msg_received_deassert_int_b,
      cfg_msg_received_deassert_int_c => cfg_msg_received_deassert_int_c,
      cfg_msg_received_deassert_int_d => cfg_msg_received_deassert_int_d,
      cfg_msg_received_err_cor => cfg_msg_received_err_cor,
      cfg_msg_received_err_fatal => cfg_msg_received_err_fatal,
      cfg_msg_received_err_non_fatal => cfg_msg_received_err_non_fatal,
      cfg_msg_received_pm_as_nak => cfg_msg_received_pm_as_nak,
      cfg_msg_received_pm_pme => cfg_msg_received_pm_pme,
      cfg_msg_received_pme_to_ack => cfg_msg_received_pme_to_ack,
      cfg_msg_received_setslotpowerlimit => cfg_msg_received_setslotpowerlimit,
      cfg_pcie_link_state(2 downto 0) => cfg_pcie_link_state(2 downto 0),
      cfg_pciecap_interrupt_msgnum(4 downto 0) => cfg_pciecap_interrupt_msgnum(4 downto 0),
      cfg_pm_force_state(1 downto 0) => cfg_pm_force_state(1 downto 0),
      cfg_pm_force_state_en => cfg_pm_force_state_en,
      cfg_pm_halt_aspm_l0s => cfg_pm_halt_aspm_l0s,
      cfg_pm_halt_aspm_l1 => cfg_pm_halt_aspm_l1,
      cfg_pm_wake => cfg_pm_wake,
      cfg_pmcsr_pme_en => cfg_pmcsr_pme_en,
      cfg_pmcsr_pme_status => cfg_pmcsr_pme_status,
      cfg_pmcsr_powerstate(1 downto 0) => cfg_pmcsr_powerstate(1 downto 0),
      cfg_received_func_lvl_rst => cfg_received_func_lvl_rst,
      cfg_root_control_pme_int_en => cfg_root_control_pme_int_en,
      cfg_root_control_syserr_corr_err_en => cfg_root_control_syserr_corr_err_en,
      cfg_root_control_syserr_fatal_err_en => cfg_root_control_syserr_fatal_err_en,
      cfg_root_control_syserr_non_fatal_err_en => cfg_root_control_syserr_non_fatal_err_en,
      cfg_slot_control_electromech_il_ctl_pulse => cfg_slot_control_electromech_il_ctl_pulse,
      cfg_to_turnoff => cfg_to_turnoff,
      cfg_trn_pending => cfg_trn_pending,
      cfg_turnoff_ok => cfg_turnoff_ok,
      cfg_vc_tcvc_map(6 downto 0) => cfg_vc_tcvc_map(6 downto 0),
      fc_cpld(11 downto 0) => fc_cpld(11 downto 0),
      fc_cplh(7 downto 0) => fc_cplh(7 downto 0),
      fc_npd(11 downto 0) => fc_npd(11 downto 0),
      fc_nph(7 downto 0) => fc_nph(7 downto 0),
      fc_pd(11 downto 0) => fc_pd(11 downto 0),
      fc_ph(7 downto 0) => fc_ph(7 downto 0),
      fc_sel(2 downto 0) => fc_sel(2 downto 0),
      m_axis_rx_tdata(63 downto 0) => m_axis_rx_tdata(63 downto 0),
      m_axis_rx_tkeep(1 downto 0) => m_axis_rx_tkeep(1 downto 0),
      m_axis_rx_tlast => m_axis_rx_tlast,
      m_axis_rx_tready => m_axis_rx_tready,
      m_axis_rx_tuser(12 downto 0) => m_axis_rx_tuser(12 downto 0),
      m_axis_rx_tvalid_xhdl2_reg => m_axis_rx_tvalid,
      \out\ => user_lnk_up_int,
      pcie_drp_addr(8 downto 0) => pcie_drp_addr(8 downto 0),
      pcie_drp_clk => pcie_drp_clk,
      pcie_drp_di(15 downto 0) => pcie_drp_di(15 downto 0),
      pcie_drp_do(15 downto 0) => pcie_drp_do(15 downto 0),
      pcie_drp_en => pcie_drp_en,
      pcie_drp_rdy => pcie_drp_rdy,
      pcie_drp_we => pcie_drp_we,
      pipe_clk => \^int_pipe_rxusrclk_out\,
      pipe_rx0_chanisaligned => pipe_rx0_chanisaligned_gt,
      pipe_rx0_char_is_k(1 downto 0) => pipe_rx0_char_is_k_gt(1 downto 0),
      pipe_rx0_data(15 downto 0) => pipe_rx0_data_gt(15 downto 0),
      pipe_rx0_elec_idle => pipe_rx0_elec_idle_gt,
      pipe_rx0_phy_status => pipe_rx0_phy_status_gt,
      pipe_rx0_polarity => pipe_rx0_polarity_gt,
      pipe_rx0_status(2 downto 0) => pipe_rx0_status_gt(2 downto 0),
      pipe_rx0_valid => pipe_rx0_valid_gt,
      pipe_rx1_chanisaligned => pipe_rx1_chanisaligned_gt,
      pipe_rx1_char_is_k(1 downto 0) => pipe_rx1_char_is_k_gt(1 downto 0),
      pipe_rx1_data(15 downto 0) => pipe_rx1_data_gt(15 downto 0),
      pipe_rx1_elec_idle => pipe_rx1_elec_idle_gt,
      pipe_rx1_phy_status => pipe_rx1_phy_status_gt,
      pipe_rx1_polarity => pipe_rx1_polarity_gt,
      pipe_rx1_status(2 downto 0) => pipe_rx1_status_gt(2 downto 0),
      pipe_rx1_valid => pipe_rx1_valid_gt,
      pipe_tx0_char_is_k(1 downto 0) => pipe_tx0_char_is_k_gt(1 downto 0),
      pipe_tx0_compliance => pipe_tx0_compliance_gt,
      pipe_tx0_data(15 downto 0) => pipe_tx0_data_gt(15 downto 0),
      pipe_tx0_elec_idle => pipe_tx0_elec_idle_gt,
      pipe_tx0_powerdown(1 downto 0) => pipe_tx0_powerdown_gt(1 downto 0),
      pipe_tx1_char_is_k(1 downto 0) => pipe_tx1_char_is_k_gt(1 downto 0),
      pipe_tx1_compliance => pipe_tx1_compliance_gt,
      pipe_tx1_data(15 downto 0) => pipe_tx1_data_gt(15 downto 0),
      pipe_tx1_elec_idle => pipe_tx1_elec_idle_gt,
      pipe_tx1_powerdown(1 downto 0) => pipe_tx1_powerdown_gt(1 downto 0),
      pipe_tx_deemph => pipe_tx_deemph_gt,
      pipe_tx_margin(2 downto 0) => pipe_tx_margin_gt(2 downto 0),
      pipe_tx_rate => pipe_tx_rate_gt,
      pipe_tx_rcvr_det => pipe_tx_rcvr_det_gt,
      pl_directed_change_done => pl_directed_change_done,
      pl_directed_link_auton => pl_directed_link_auton,
      pl_directed_link_change(1 downto 0) => pl_directed_link_change(1 downto 0),
      pl_directed_link_speed => pl_directed_link_speed,
      pl_directed_link_width(1 downto 0) => pl_directed_link_width(1 downto 0),
      pl_downstream_deemph_source => pl_downstream_deemph_source,
      pl_initial_link_width(2 downto 0) => pl_initial_link_width(2 downto 0),
      pl_lane_reversal_mode(1 downto 0) => pl_lane_reversal_mode(1 downto 0),
      pl_link_gen2_cap => pl_link_gen2_cap,
      pl_link_partner_gen2_supported => pl_link_partner_gen2_supported,
      pl_link_upcfg_cap => pl_link_upcfg_cap,
      pl_ltssm_state(5 downto 0) => \^pl_ltssm_state\(5 downto 0),
      pl_phy_lnk_up => \^pl_phy_lnk_up\,
      pl_received_hot_rst => pl_received_hot_rst_int,
      pl_rx_pm_state(1 downto 0) => pl_rx_pm_state(1 downto 0),
      pl_sel_lnk_rate => pl_sel_lnk_rate,
      pl_sel_lnk_width(1 downto 0) => pl_sel_lnk_width(1 downto 0),
      pl_transmit_hot_rst => pl_transmit_hot_rst,
      pl_tx_pm_state(2 downto 0) => pl_tx_pm_state(2 downto 0),
      pl_upstream_prefer_deemph => pl_upstream_prefer_deemph,
      rx_np_ok => rx_np_ok,
      rx_np_req => rx_np_req,
      s_axis_tx_tdata(63 downto 0) => s_axis_tx_tdata(63 downto 0),
      s_axis_tx_tkeep(0) => s_axis_tx_tkeep(0),
      s_axis_tx_tlast => s_axis_tx_tlast,
      s_axis_tx_tuser(3 downto 0) => s_axis_tx_tuser(3 downto 0),
      s_axis_tx_tvalid => s_axis_tx_tvalid,
      src_in => pl_phy_lnk_up_int,
      sys_rst_n => sys_rst_n_0,
      \tbuf_gap_cnt_reg[0]\ => \^user_reset_out\,
      tready_thrtl_xhdl1_reg => s_axis_tx_tready,
      trn_lnk_up => trn_lnk_up,
      trn_tbuf_av(5 downto 0) => tx_buf_av(5 downto 0),
      trn_tcfg_req => tx_cfg_req,
      tx_cfg_gnt => tx_cfg_gnt,
      tx_err_drop => tx_err_drop,
      user_reset_int_reg => pcie_top_i_n_4
    );
pl_phy_lnk_up_cdc: entity work.\spec7_pcie_7x_0_xpm_cdc_single__2\
     port map (
      dest_clk => \^int_userclk1_out\,
      dest_out => pl_phy_lnk_up_sync,
      src_clk => \^int_pipe_rxusrclk_out\,
      src_in => pl_phy_lnk_up_int
    );
pl_phy_lnk_up_q_reg: unisim.vcomponents.FDRE
     port map (
      C => \^int_userclk1_out\,
      CE => '1',
      D => pl_phy_lnk_up_sync,
      Q => \^pl_phy_lnk_up\,
      R => gt_top_i_n_146
    );
pl_received_hot_rst_cdc: entity work.spec7_pcie_7x_0_xpm_cdc_single
     port map (
      dest_clk => \^int_userclk1_out\,
      dest_out => pl_received_hot_rst_sync,
      src_clk => \^int_pipe_rxusrclk_out\,
      src_in => pl_received_hot_rst_int
    );
pl_received_hot_rst_q_reg: unisim.vcomponents.FDRE
     port map (
      C => \^int_userclk1_out\,
      CE => '1',
      D => pl_received_hot_rst_sync,
      Q => \^pl_received_hot_rst\,
      R => gt_top_i_n_146
    );
store_ltssm_inferred_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"E"
    )
        port map (
      I0 => store_ltssm_inferred_i_2_n_0,
      I1 => store_ltssm_inferred_i_3_n_0,
      O => store_ltssm
    );
store_ltssm_inferred_i_2: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => \^pl_ltssm_state\(0),
      I1 => ltssm_reg2(0),
      I2 => ltssm_reg2(2),
      I3 => \^pl_ltssm_state\(2),
      I4 => ltssm_reg2(1),
      I5 => \^pl_ltssm_state\(1),
      O => store_ltssm_inferred_i_2_n_0
    );
store_ltssm_inferred_i_3: unisim.vcomponents.LUT6
    generic map(
      INIT => X"6FF6FFFFFFFF6FF6"
    )
        port map (
      I0 => \^pl_ltssm_state\(3),
      I1 => ltssm_reg2(3),
      I2 => ltssm_reg2(5),
      I3 => \^pl_ltssm_state\(5),
      I4 => ltssm_reg2(4),
      I5 => \^pl_ltssm_state\(4),
      O => store_ltssm_inferred_i_3_n_0
    );
user_lnk_up_d_reg: unisim.vcomponents.FDRE
     port map (
      C => \^int_userclk1_out\,
      CE => '1',
      D => trn_lnk_up,
      Q => user_lnk_up_d,
      R => gt_top_i_n_146
    );
user_lnk_up_int_reg: unisim.vcomponents.FDRE
     port map (
      C => \^int_userclk1_out\,
      CE => '1',
      D => user_lnk_up_d,
      Q => user_lnk_up_int,
      R => gt_top_i_n_146
    );
user_reset_int_reg: unisim.vcomponents.FDPE
     port map (
      C => \^int_userclk1_out\,
      CE => '1',
      D => pcie_top_i_n_4,
      PRE => user_reset_out_i_1_n_0,
      Q => bridge_reset_int
    );
user_reset_out_i_1: unisim.vcomponents.LUT2
    generic map(
      INIT => X"B"
    )
        port map (
      I0 => \^pl_received_hot_rst\,
      I1 => sys_rst_n,
      O => user_reset_out_i_1_n_0
    );
user_reset_out_reg: unisim.vcomponents.FDPE
     port map (
      C => \^int_userclk1_out\,
      CE => '1',
      D => bridge_reset_int,
      PRE => user_reset_out_i_1_n_0,
      Q => \^user_reset_out\
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top is
  port (
    pci_exp_txp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_txn : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 1 downto 0 );
    int_pclk_out_slave : out STD_LOGIC;
    int_pipe_rxusrclk_out : out STD_LOGIC;
    int_rxoutclk_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    int_dclk_out : out STD_LOGIC;
    int_userclk1_out : out STD_LOGIC;
    int_userclk2_out : out STD_LOGIC;
    int_oobclk_out : out STD_LOGIC;
    int_mmcm_lock_out : out STD_LOGIC;
    int_qplllock_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    int_qplloutclk_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    int_qplloutrefclk_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    int_pclk_sel_slave : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_pclk_in : in STD_LOGIC;
    pipe_rxusrclk_in : in STD_LOGIC;
    pipe_rxoutclk_in : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_dclk_in : in STD_LOGIC;
    pipe_userclk1_in : in STD_LOGIC;
    pipe_userclk2_in : in STD_LOGIC;
    pipe_oobclk_in : in STD_LOGIC;
    pipe_mmcm_lock_in : in STD_LOGIC;
    pipe_txoutclk_out : out STD_LOGIC;
    pipe_rxoutclk_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_pclk_sel_out : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_gen3_out : out STD_LOGIC;
    user_clk_out : out STD_LOGIC;
    user_reset_out : out STD_LOGIC;
    user_lnk_up : out STD_LOGIC;
    user_app_rdy : out STD_LOGIC;
    tx_buf_av : out STD_LOGIC_VECTOR ( 5 downto 0 );
    tx_cfg_req : out STD_LOGIC;
    tx_err_drop : out STD_LOGIC;
    s_axis_tx_tready : out STD_LOGIC;
    s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axis_tx_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axis_tx_tlast : in STD_LOGIC;
    s_axis_tx_tvalid : in STD_LOGIC;
    s_axis_tx_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
    tx_cfg_gnt : in STD_LOGIC;
    m_axis_rx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_rx_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axis_rx_tlast : out STD_LOGIC;
    m_axis_rx_tvalid : out STD_LOGIC;
    m_axis_rx_tready : in STD_LOGIC;
    m_axis_rx_tuser : out STD_LOGIC_VECTOR ( 21 downto 0 );
    rx_np_ok : in STD_LOGIC;
    rx_np_req : in STD_LOGIC;
    fc_cpld : out STD_LOGIC_VECTOR ( 11 downto 0 );
    fc_cplh : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_npd : out STD_LOGIC_VECTOR ( 11 downto 0 );
    fc_nph : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_pd : out STD_LOGIC_VECTOR ( 11 downto 0 );
    fc_ph : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_sel : in STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_mgmt_do : out STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_mgmt_rd_wr_done : out STD_LOGIC;
    cfg_status : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_command : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_dstatus : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_dcommand : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_lstatus : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_lcommand : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_dcommand2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_pcie_link_state : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_pmcsr_pme_en : out STD_LOGIC;
    cfg_pmcsr_powerstate : out STD_LOGIC_VECTOR ( 1 downto 0 );
    cfg_pmcsr_pme_status : out STD_LOGIC;
    cfg_received_func_lvl_rst : out STD_LOGIC;
    cfg_mgmt_di : in STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_mgmt_byte_en : in STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_mgmt_dwaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
    cfg_mgmt_wr_en : in STD_LOGIC;
    cfg_mgmt_rd_en : in STD_LOGIC;
    cfg_mgmt_wr_readonly : in STD_LOGIC;
    cfg_err_ecrc : in STD_LOGIC;
    cfg_err_ur : in STD_LOGIC;
    cfg_err_cpl_timeout : in STD_LOGIC;
    cfg_err_cpl_unexpect : in STD_LOGIC;
    cfg_err_cpl_abort : in STD_LOGIC;
    cfg_err_posted : in STD_LOGIC;
    cfg_err_cor : in STD_LOGIC;
    cfg_err_atomic_egress_blocked : in STD_LOGIC;
    cfg_err_internal_cor : in STD_LOGIC;
    cfg_err_malformed : in STD_LOGIC;
    cfg_err_mc_blocked : in STD_LOGIC;
    cfg_err_poisoned : in STD_LOGIC;
    cfg_err_norecovery : in STD_LOGIC;
    cfg_err_tlp_cpl_header : in STD_LOGIC_VECTOR ( 47 downto 0 );
    cfg_err_cpl_rdy : out STD_LOGIC;
    cfg_err_locked : in STD_LOGIC;
    cfg_err_acs : in STD_LOGIC;
    cfg_err_internal_uncor : in STD_LOGIC;
    cfg_trn_pending : in STD_LOGIC;
    cfg_pm_halt_aspm_l0s : in STD_LOGIC;
    cfg_pm_halt_aspm_l1 : in STD_LOGIC;
    cfg_pm_force_state_en : in STD_LOGIC;
    cfg_pm_force_state : in STD_LOGIC_VECTOR ( 1 downto 0 );
    cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 );
    cfg_interrupt : in STD_LOGIC;
    cfg_interrupt_rdy : out STD_LOGIC;
    cfg_interrupt_assert : in STD_LOGIC;
    cfg_interrupt_di : in STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_interrupt_do : out STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_interrupt_msienable : out STD_LOGIC;
    cfg_interrupt_msixenable : out STD_LOGIC;
    cfg_interrupt_msixfm : out STD_LOGIC;
    cfg_interrupt_stat : in STD_LOGIC;
    cfg_pciecap_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_to_turnoff : out STD_LOGIC;
    cfg_turnoff_ok : in STD_LOGIC;
    cfg_bus_number : out STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_device_number : out STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_function_number : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_pm_wake : in STD_LOGIC;
    cfg_pm_send_pme_to : in STD_LOGIC;
    cfg_ds_bus_number : in STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_ds_device_number : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_ds_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_mgmt_wr_rw1c_as_rw : in STD_LOGIC;
    cfg_msg_received : out STD_LOGIC;
    cfg_msg_data : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_bridge_serr_en : out STD_LOGIC;
    cfg_slot_control_electromech_il_ctl_pulse : out STD_LOGIC;
    cfg_root_control_syserr_corr_err_en : out STD_LOGIC;
    cfg_root_control_syserr_non_fatal_err_en : out STD_LOGIC;
    cfg_root_control_syserr_fatal_err_en : out STD_LOGIC;
    cfg_root_control_pme_int_en : out STD_LOGIC;
    cfg_aer_rooterr_corr_err_reporting_en : out STD_LOGIC;
    cfg_aer_rooterr_non_fatal_err_reporting_en : out STD_LOGIC;
    cfg_aer_rooterr_fatal_err_reporting_en : out STD_LOGIC;
    cfg_aer_rooterr_corr_err_received : out STD_LOGIC;
    cfg_aer_rooterr_non_fatal_err_received : out STD_LOGIC;
    cfg_aer_rooterr_fatal_err_received : out STD_LOGIC;
    cfg_msg_received_err_cor : out STD_LOGIC;
    cfg_msg_received_err_non_fatal : out STD_LOGIC;
    cfg_msg_received_err_fatal : out STD_LOGIC;
    cfg_msg_received_pm_as_nak : out STD_LOGIC;
    cfg_msg_received_pm_pme : out STD_LOGIC;
    cfg_msg_received_pme_to_ack : out STD_LOGIC;
    cfg_msg_received_assert_int_a : out STD_LOGIC;
    cfg_msg_received_assert_int_b : out STD_LOGIC;
    cfg_msg_received_assert_int_c : out STD_LOGIC;
    cfg_msg_received_assert_int_d : out STD_LOGIC;
    cfg_msg_received_deassert_int_a : out STD_LOGIC;
    cfg_msg_received_deassert_int_b : out STD_LOGIC;
    cfg_msg_received_deassert_int_c : out STD_LOGIC;
    cfg_msg_received_deassert_int_d : out STD_LOGIC;
    cfg_msg_received_setslotpowerlimit : out STD_LOGIC;
    pl_directed_link_change : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_directed_link_width : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_directed_link_speed : in STD_LOGIC;
    pl_directed_link_auton : in STD_LOGIC;
    pl_upstream_prefer_deemph : in STD_LOGIC;
    pl_sel_lnk_rate : out STD_LOGIC;
    pl_sel_lnk_width : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_ltssm_state : out STD_LOGIC_VECTOR ( 5 downto 0 );
    pl_lane_reversal_mode : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_phy_lnk_up : out STD_LOGIC;
    pl_tx_pm_state : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pl_rx_pm_state : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_link_upcfg_cap : out STD_LOGIC;
    pl_link_gen2_cap : out STD_LOGIC;
    pl_link_partner_gen2_supported : out STD_LOGIC;
    pl_initial_link_width : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pl_directed_change_done : out STD_LOGIC;
    pl_received_hot_rst : out STD_LOGIC;
    pl_transmit_hot_rst : in STD_LOGIC;
    pl_downstream_deemph_source : in STD_LOGIC;
    cfg_err_aer_headerlog : in STD_LOGIC_VECTOR ( 127 downto 0 );
    cfg_aer_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_err_aer_headerlog_set : out STD_LOGIC;
    cfg_aer_ecrc_check_en : out STD_LOGIC;
    cfg_aer_ecrc_gen_en : out STD_LOGIC;
    cfg_vc_tcvc_map : out STD_LOGIC_VECTOR ( 6 downto 0 );
    sys_clk : in STD_LOGIC;
    sys_rst_n : in STD_LOGIC;
    pipe_mmcm_rst_n : in STD_LOGIC;
    common_commands_in : in STD_LOGIC_VECTOR ( 11 downto 0 );
    pipe_rx_0_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_rx_1_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_rx_2_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_rx_3_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_rx_4_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_rx_5_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_rx_6_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_rx_7_sigs : in STD_LOGIC_VECTOR ( 24 downto 0 );
    common_commands_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
    pipe_tx_0_sigs : out STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_tx_1_sigs : out STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_tx_2_sigs : out STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_tx_3_sigs : out STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_tx_4_sigs : out STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_tx_5_sigs : out STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_tx_6_sigs : out STD_LOGIC_VECTOR ( 24 downto 0 );
    pipe_tx_7_sigs : out STD_LOGIC_VECTOR ( 24 downto 0 );
    startup_eos_in : in STD_LOGIC;
    startup_cfgclk : out STD_LOGIC;
    startup_cfgmclk : out STD_LOGIC;
    startup_eos : out STD_LOGIC;
    startup_preq : out STD_LOGIC;
    startup_clk : in STD_LOGIC;
    startup_gsr : in STD_LOGIC;
    startup_gts : in STD_LOGIC;
    startup_keyclearb : in STD_LOGIC;
    startup_pack : in STD_LOGIC;
    startup_usrcclko : in STD_LOGIC;
    startup_usrcclkts : in STD_LOGIC;
    startup_usrdoneo : in STD_LOGIC;
    startup_usrdonets : in STD_LOGIC;
    icap_clk : in STD_LOGIC;
    icap_csib : in STD_LOGIC;
    icap_rdwrb : in STD_LOGIC;
    icap_i : in STD_LOGIC_VECTOR ( 31 downto 0 );
    icap_o : out STD_LOGIC_VECTOR ( 31 downto 0 );
    qpll_drp_crscode : in STD_LOGIC_VECTOR ( 11 downto 0 );
    qpll_drp_fsm : in STD_LOGIC_VECTOR ( 17 downto 0 );
    qpll_drp_done : in STD_LOGIC_VECTOR ( 1 downto 0 );
    qpll_drp_reset : in STD_LOGIC_VECTOR ( 1 downto 0 );
    qpll_qplllock : in STD_LOGIC_VECTOR ( 1 downto 0 );
    qpll_qplloutclk : in STD_LOGIC_VECTOR ( 1 downto 0 );
    qpll_qplloutrefclk : in STD_LOGIC_VECTOR ( 1 downto 0 );
    qpll_qplld : out STD_LOGIC;
    qpll_qpllreset : out STD_LOGIC_VECTOR ( 1 downto 0 );
    qpll_drp_clk : out STD_LOGIC;
    qpll_drp_rst_n : out STD_LOGIC;
    qpll_drp_ovrd : out STD_LOGIC;
    qpll_drp_gen3 : out STD_LOGIC;
    qpll_drp_start : out STD_LOGIC;
    pipe_txprbssel : in STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_rxprbssel : in STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_txprbsforceerr : in STD_LOGIC;
    pipe_rxprbscntreset : in STD_LOGIC;
    pipe_loopback : in STD_LOGIC_VECTOR ( 2 downto 0 );
    pipe_rxprbserr : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_txinhibit : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rst_fsm : out STD_LOGIC_VECTOR ( 4 downto 0 );
    pipe_qrst_fsm : out STD_LOGIC_VECTOR ( 11 downto 0 );
    pipe_rate_fsm : out STD_LOGIC_VECTOR ( 9 downto 0 );
    pipe_sync_fsm_tx : out STD_LOGIC_VECTOR ( 11 downto 0 );
    pipe_sync_fsm_rx : out STD_LOGIC_VECTOR ( 13 downto 0 );
    pipe_drp_fsm : out STD_LOGIC_VECTOR ( 13 downto 0 );
    pipe_rst_idle : out STD_LOGIC;
    pipe_qrst_idle : out STD_LOGIC;
    pipe_rate_idle : out STD_LOGIC;
    pipe_eyescandataerror : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxstatus : out STD_LOGIC_VECTOR ( 5 downto 0 );
    pipe_dmonitorout : out STD_LOGIC_VECTOR ( 29 downto 0 );
    pipe_cpll_lock : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_qpll_lock : out STD_LOGIC_VECTOR ( 0 to 0 );
    pipe_rxpmaresetdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxbufstatus : out STD_LOGIC_VECTOR ( 5 downto 0 );
    pipe_txphaligndone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_txphinitdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_txdlysresetdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxphaligndone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxdlysresetdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxsyncdone : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_rxdisperr : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_rxnotintable : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pipe_rxcommadet : out STD_LOGIC_VECTOR ( 1 downto 0 );
    gt_ch_drp_rdy : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug_0 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug_1 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug_2 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug_3 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug_4 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug_5 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug_6 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug_7 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug_8 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug_9 : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pipe_debug : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ext_ch_gt_drpclk : out STD_LOGIC;
    ext_ch_gt_drpaddr : in STD_LOGIC_VECTOR ( 17 downto 0 );
    ext_ch_gt_drpen : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ext_ch_gt_drpdi : in STD_LOGIC_VECTOR ( 31 downto 0 );
    ext_ch_gt_drpwe : in STD_LOGIC_VECTOR ( 1 downto 0 );
    ext_ch_gt_drpdo : out STD_LOGIC_VECTOR ( 31 downto 0 );
    ext_ch_gt_drprdy : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pcie_drp_clk : in STD_LOGIC;
    pcie_drp_en : in STD_LOGIC;
    pcie_drp_we : in STD_LOGIC;
    pcie_drp_addr : in STD_LOGIC_VECTOR ( 8 downto 0 );
    pcie_drp_di : in STD_LOGIC_VECTOR ( 15 downto 0 );
    pcie_drp_do : out STD_LOGIC_VECTOR ( 15 downto 0 );
    pcie_drp_rdy : out STD_LOGIC
  );
  attribute CFG_CTL_IF : string;
  attribute CFG_CTL_IF of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "TRUE";
  attribute CFG_FC_IF : string;
  attribute CFG_FC_IF of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "TRUE";
  attribute CFG_MGMT_IF : string;
  attribute CFG_MGMT_IF of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "TRUE";
  attribute CFG_STATUS_IF : string;
  attribute CFG_STATUS_IF of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "TRUE";
  attribute C_DATA_WIDTH : integer;
  attribute C_DATA_WIDTH of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is 64;
  attribute ENABLE_JTAG_DBG : string;
  attribute ENABLE_JTAG_DBG of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute ERR_REPORTING_IF : string;
  attribute ERR_REPORTING_IF of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "TRUE";
  attribute EXT_CH_GT_DRP : string;
  attribute EXT_CH_GT_DRP of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute EXT_PIPE_INTERFACE : string;
  attribute EXT_PIPE_INTERFACE of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute EXT_STARTUP_PRIMITIVE : string;
  attribute EXT_STARTUP_PRIMITIVE of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute KEEP_WIDTH : integer;
  attribute KEEP_WIDTH of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is 8;
  attribute LINK_CAP_MAX_LINK_WIDTH : integer;
  attribute LINK_CAP_MAX_LINK_WIDTH of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is 2;
  attribute ORIG_REF_NAME : string;
  attribute ORIG_REF_NAME of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "spec7_pcie_7x_0_pcie2_top";
  attribute PCIE_ASYNC_EN : string;
  attribute PCIE_ASYNC_EN of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute PCIE_EXT_CLK : string;
  attribute PCIE_EXT_CLK of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute PCIE_EXT_GT_COMMON : string;
  attribute PCIE_EXT_GT_COMMON of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute PIPE_SIM : string;
  attribute PIPE_SIM of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute PL_INTERFACE : string;
  attribute PL_INTERFACE of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "TRUE";
  attribute RCV_MSG_IF : string;
  attribute RCV_MSG_IF of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute SHARED_LOGIC_IN_CORE : string;
  attribute SHARED_LOGIC_IN_CORE of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute TRANSCEIVER_CTRL_STATUS_PORTS : string;
  attribute TRANSCEIVER_CTRL_STATUS_PORTS of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute bar_0 : string;
  attribute bar_0 of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FFFF0000";
  attribute bar_1 : string;
  attribute bar_1 of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00000000";
  attribute bar_2 : string;
  attribute bar_2 of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00000000";
  attribute bar_3 : string;
  attribute bar_3 of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00000000";
  attribute bar_4 : string;
  attribute bar_4 of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00000000";
  attribute bar_5 : string;
  attribute bar_5 of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00000000";
  attribute bram_lat : string;
  attribute bram_lat of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute c_aer_base_ptr : string;
  attribute c_aer_base_ptr of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "000";
  attribute c_aer_cap_ecrc_check_capable : string;
  attribute c_aer_cap_ecrc_check_capable of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_aer_cap_ecrc_gen_capable : string;
  attribute c_aer_cap_ecrc_gen_capable of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_aer_cap_multiheader : string;
  attribute c_aer_cap_multiheader of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_aer_cap_nextptr : string;
  attribute c_aer_cap_nextptr of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "000";
  attribute c_aer_cap_on : string;
  attribute c_aer_cap_on of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_aer_cap_optional_err_support : string;
  attribute c_aer_cap_optional_err_support of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "000000";
  attribute c_aer_cap_permit_rooterr_update : string;
  attribute c_aer_cap_permit_rooterr_update of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_buf_opt_bma : string;
  attribute c_buf_opt_bma of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "TRUE";
  attribute c_component_name : string;
  attribute c_component_name of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "spec7_pcie_7x_0";
  attribute c_cpl_inf : string;
  attribute c_cpl_inf of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "TRUE";
  attribute c_cpl_infinite : string;
  attribute c_cpl_infinite of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "TRUE";
  attribute c_cpl_timeout_disable_sup : string;
  attribute c_cpl_timeout_disable_sup of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_cpl_timeout_range : string;
  attribute c_cpl_timeout_range of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0010";
  attribute c_cpl_timeout_ranges_sup : string;
  attribute c_cpl_timeout_ranges_sup of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "2";
  attribute c_d1_support : string;
  attribute c_d1_support of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_d2_support : string;
  attribute c_d2_support of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_de_emph : string;
  attribute c_de_emph of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_dev_cap2_ari_forwarding_supported : string;
  attribute c_dev_cap2_ari_forwarding_supported of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_dev_cap2_atomicop32_completer_supported : string;
  attribute c_dev_cap2_atomicop32_completer_supported of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_dev_cap2_atomicop64_completer_supported : string;
  attribute c_dev_cap2_atomicop64_completer_supported of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_dev_cap2_atomicop_routing_supported : string;
  attribute c_dev_cap2_atomicop_routing_supported of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_dev_cap2_cas128_completer_supported : string;
  attribute c_dev_cap2_cas128_completer_supported of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_dev_cap2_tph_completer_supported : string;
  attribute c_dev_cap2_tph_completer_supported of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00";
  attribute c_dev_control_ext_tag_default : string;
  attribute c_dev_control_ext_tag_default of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_dev_port_type : string;
  attribute c_dev_port_type of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute c_dis_lane_reverse : string;
  attribute c_dis_lane_reverse of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "TRUE";
  attribute c_disable_rx_poisoned_resp : string;
  attribute c_disable_rx_poisoned_resp of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_disable_scrambling : string;
  attribute c_disable_scrambling of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_disable_tx_aspm_l0s : string;
  attribute c_disable_tx_aspm_l0s of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_dll_lnk_actv_cap : string;
  attribute c_dll_lnk_actv_cap of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_dsi_bool : string;
  attribute c_dsi_bool of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_dsn_base_ptr : string;
  attribute c_dsn_base_ptr of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "100";
  attribute c_dsn_cap_enabled : string;
  attribute c_dsn_cap_enabled of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "TRUE";
  attribute c_dsn_next_ptr : string;
  attribute c_dsn_next_ptr of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "000";
  attribute c_enable_msg_route : string;
  attribute c_enable_msg_route of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00000000000";
  attribute c_ep_l0s_accpt_lat : string;
  attribute c_ep_l0s_accpt_lat of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute c_ep_l1_accpt_lat : string;
  attribute c_ep_l1_accpt_lat of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "7";
  attribute c_ext_pci_cfg_space_addr : string;
  attribute c_ext_pci_cfg_space_addr of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "3FF";
  attribute c_external_clocking : string;
  attribute c_external_clocking of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "TRUE";
  attribute c_fc_cpld : string;
  attribute c_fc_cpld of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "461";
  attribute c_fc_cplh : string;
  attribute c_fc_cplh of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "36";
  attribute c_fc_npd : string;
  attribute c_fc_npd of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "24";
  attribute c_fc_nph : string;
  attribute c_fc_nph of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "12";
  attribute c_fc_pd : string;
  attribute c_fc_pd of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "437";
  attribute c_fc_ph : string;
  attribute c_fc_ph of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "32";
  attribute c_gen1 : string;
  attribute c_gen1 of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_header_type : string;
  attribute c_header_type of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00";
  attribute c_hw_auton_spd_disable : string;
  attribute c_hw_auton_spd_disable of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_int_width : integer;
  attribute c_int_width of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is 64;
  attribute c_last_cfg_dw : string;
  attribute c_last_cfg_dw of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "10C";
  attribute c_link_cap_aspm_optionality : string;
  attribute c_link_cap_aspm_optionality of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_ll_ack_timeout : string;
  attribute c_ll_ack_timeout of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0000";
  attribute c_ll_ack_timeout_enable : string;
  attribute c_ll_ack_timeout_enable of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_ll_ack_timeout_function : string;
  attribute c_ll_ack_timeout_function of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute c_ll_replay_timeout : string;
  attribute c_ll_replay_timeout of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0000";
  attribute c_ll_replay_timeout_enable : string;
  attribute c_ll_replay_timeout_enable of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_ll_replay_timeout_func : string;
  attribute c_ll_replay_timeout_func of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "1";
  attribute c_lnk_bndwdt_notif : string;
  attribute c_lnk_bndwdt_notif of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_msi : string;
  attribute c_msi of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute c_msi_64b_addr : string;
  attribute c_msi_64b_addr of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "TRUE";
  attribute c_msi_cap_on : string;
  attribute c_msi_cap_on of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "TRUE";
  attribute c_msi_mult_msg_extn : string;
  attribute c_msi_mult_msg_extn of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute c_msi_per_vctr_mask_cap : string;
  attribute c_msi_per_vctr_mask_cap of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_msix_cap_on : string;
  attribute c_msix_cap_on of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_msix_next_ptr : string;
  attribute c_msix_next_ptr of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00";
  attribute c_msix_pba_bir : string;
  attribute c_msix_pba_bir of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute c_msix_pba_offset : string;
  attribute c_msix_pba_offset of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute c_msix_table_bir : string;
  attribute c_msix_table_bir of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute c_msix_table_offset : string;
  attribute c_msix_table_offset of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute c_msix_table_size : string;
  attribute c_msix_table_size of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "000";
  attribute c_pci_cfg_space_addr : string;
  attribute c_pci_cfg_space_addr of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "3F";
  attribute c_pcie_blk_locn : string;
  attribute c_pcie_blk_locn of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute c_pcie_cap_next_ptr : string;
  attribute c_pcie_cap_next_ptr of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00";
  attribute c_pcie_cap_slot_implemented : string;
  attribute c_pcie_cap_slot_implemented of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_pcie_dbg_ports : string;
  attribute c_pcie_dbg_ports of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_pcie_fast_config : integer;
  attribute c_pcie_fast_config of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is 0;
  attribute c_perf_level_high : string;
  attribute c_perf_level_high of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "TRUE";
  attribute c_phantom_functions : string;
  attribute c_phantom_functions of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute c_pm_cap_next_ptr : string;
  attribute c_pm_cap_next_ptr of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "48";
  attribute c_pme_support : string;
  attribute c_pme_support of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0F";
  attribute c_rbar_base_ptr : string;
  attribute c_rbar_base_ptr of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "000";
  attribute c_rbar_cap_control_encodedbar0 : string;
  attribute c_rbar_cap_control_encodedbar0 of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00";
  attribute c_rbar_cap_control_encodedbar1 : string;
  attribute c_rbar_cap_control_encodedbar1 of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00";
  attribute c_rbar_cap_control_encodedbar2 : string;
  attribute c_rbar_cap_control_encodedbar2 of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00";
  attribute c_rbar_cap_control_encodedbar3 : string;
  attribute c_rbar_cap_control_encodedbar3 of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00";
  attribute c_rbar_cap_control_encodedbar4 : string;
  attribute c_rbar_cap_control_encodedbar4 of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00";
  attribute c_rbar_cap_control_encodedbar5 : string;
  attribute c_rbar_cap_control_encodedbar5 of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00";
  attribute c_rbar_cap_index0 : string;
  attribute c_rbar_cap_index0 of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute c_rbar_cap_index1 : string;
  attribute c_rbar_cap_index1 of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute c_rbar_cap_index2 : string;
  attribute c_rbar_cap_index2 of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute c_rbar_cap_index3 : string;
  attribute c_rbar_cap_index3 of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute c_rbar_cap_index4 : string;
  attribute c_rbar_cap_index4 of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute c_rbar_cap_index5 : string;
  attribute c_rbar_cap_index5 of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute c_rbar_cap_nextptr : string;
  attribute c_rbar_cap_nextptr of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "000";
  attribute c_rbar_cap_on : string;
  attribute c_rbar_cap_on of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_rbar_cap_sup0 : string;
  attribute c_rbar_cap_sup0 of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00001";
  attribute c_rbar_cap_sup1 : string;
  attribute c_rbar_cap_sup1 of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00001";
  attribute c_rbar_cap_sup2 : string;
  attribute c_rbar_cap_sup2 of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00001";
  attribute c_rbar_cap_sup3 : string;
  attribute c_rbar_cap_sup3 of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00001";
  attribute c_rbar_cap_sup4 : string;
  attribute c_rbar_cap_sup4 of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00001";
  attribute c_rbar_cap_sup5 : string;
  attribute c_rbar_cap_sup5 of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00001";
  attribute c_rbar_num : string;
  attribute c_rbar_num of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute c_rcb : string;
  attribute c_rcb of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute c_recrc_check : string;
  attribute c_recrc_check of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute c_recrc_check_trim : string;
  attribute c_recrc_check_trim of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_rev_gt_order : string;
  attribute c_rev_gt_order of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_root_cap_crs : string;
  attribute c_root_cap_crs of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_rx_raddr_lat : string;
  attribute c_rx_raddr_lat of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute c_rx_ram_limit : string;
  attribute c_rx_ram_limit of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "7FF";
  attribute c_rx_rdata_lat : string;
  attribute c_rx_rdata_lat of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "2";
  attribute c_rx_write_lat : string;
  attribute c_rx_write_lat of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute c_silicon_rev : string;
  attribute c_silicon_rev of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "2";
  attribute c_slot_cap_attn_butn : string;
  attribute c_slot_cap_attn_butn of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_slot_cap_attn_ind : string;
  attribute c_slot_cap_attn_ind of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_slot_cap_elec_interlock : string;
  attribute c_slot_cap_elec_interlock of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_slot_cap_hotplug_cap : string;
  attribute c_slot_cap_hotplug_cap of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_slot_cap_hotplug_surprise : string;
  attribute c_slot_cap_hotplug_surprise of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_slot_cap_mrl : string;
  attribute c_slot_cap_mrl of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_slot_cap_no_cmd_comp_sup : string;
  attribute c_slot_cap_no_cmd_comp_sup of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_slot_cap_physical_slot_num : string;
  attribute c_slot_cap_physical_slot_num of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute c_slot_cap_pwr_ctrl : string;
  attribute c_slot_cap_pwr_ctrl of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_slot_cap_pwr_ind : string;
  attribute c_slot_cap_pwr_ind of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_slot_cap_pwr_limit_scale : string;
  attribute c_slot_cap_pwr_limit_scale of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute c_slot_cap_pwr_limit_value : string;
  attribute c_slot_cap_pwr_limit_value of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute c_surprise_dn_err_cap : string;
  attribute c_surprise_dn_err_cap of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_trgt_lnk_spd : string;
  attribute c_trgt_lnk_spd of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute c_trn_np_fc : string;
  attribute c_trn_np_fc of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "TRUE";
  attribute c_tx_last_tlp : string;
  attribute c_tx_last_tlp of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "29";
  attribute c_tx_raddr_lat : string;
  attribute c_tx_raddr_lat of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute c_tx_rdata_lat : string;
  attribute c_tx_rdata_lat of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "2";
  attribute c_tx_write_lat : string;
  attribute c_tx_write_lat of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute c_upconfig_capable : string;
  attribute c_upconfig_capable of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "TRUE";
  attribute c_upstream_facing : string;
  attribute c_upstream_facing of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "TRUE";
  attribute c_ur_atomic : string;
  attribute c_ur_atomic of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_ur_inv_req : string;
  attribute c_ur_inv_req of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "TRUE";
  attribute c_ur_prs_response : string;
  attribute c_ur_prs_response of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "TRUE";
  attribute c_vc_base_ptr : string;
  attribute c_vc_base_ptr of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "000";
  attribute c_vc_cap_enabled : string;
  attribute c_vc_cap_enabled of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_vc_cap_reject_snoop : string;
  attribute c_vc_cap_reject_snoop of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_vc_next_ptr : string;
  attribute c_vc_next_ptr of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "000";
  attribute c_vsec_base_ptr : string;
  attribute c_vsec_base_ptr of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "000";
  attribute c_vsec_cap_enabled : string;
  attribute c_vsec_cap_enabled of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute c_vsec_next_ptr : string;
  attribute c_vsec_next_ptr of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "000";
  attribute c_xlnx_ref_board : string;
  attribute c_xlnx_ref_board of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "NONE";
  attribute cap_ver : string;
  attribute cap_ver of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "2";
  attribute cardbus_cis_ptr : string;
  attribute cardbus_cis_ptr of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00000000";
  attribute class_code : string;
  attribute class_code of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "058000";
  attribute cmps : string;
  attribute cmps of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "2";
  attribute con_scl_fctr_d0_state : string;
  attribute con_scl_fctr_d0_state of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute con_scl_fctr_d1_state : string;
  attribute con_scl_fctr_d1_state of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute con_scl_fctr_d2_state : string;
  attribute con_scl_fctr_d2_state of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute con_scl_fctr_d3_state : string;
  attribute con_scl_fctr_d3_state of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute cost_table : integer;
  attribute cost_table of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is 1;
  attribute d1_sup : string;
  attribute d1_sup of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute d2_sup : string;
  attribute d2_sup of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute dev_id : string;
  attribute dev_id of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "7012";
  attribute dev_port_type : string;
  attribute dev_port_type of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0000";
  attribute dis_scl_fctr_d0_state : string;
  attribute dis_scl_fctr_d0_state of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute dis_scl_fctr_d1_state : string;
  attribute dis_scl_fctr_d1_state of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute dis_scl_fctr_d2_state : string;
  attribute dis_scl_fctr_d2_state of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute dis_scl_fctr_d3_state : string;
  attribute dis_scl_fctr_d3_state of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "yes";
  attribute dsi : string;
  attribute dsi of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute ep_l0s_accpt_lat : string;
  attribute ep_l0s_accpt_lat of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "000";
  attribute ep_l1_accpt_lat : string;
  attribute ep_l1_accpt_lat of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "111";
  attribute ext_tag_fld_sup : string;
  attribute ext_tag_fld_sup of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "FALSE";
  attribute int_pin : string;
  attribute int_pin of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "1";
  attribute intx : string;
  attribute intx of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "TRUE";
  attribute max_lnk_spd : string;
  attribute max_lnk_spd of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "1";
  attribute max_lnk_wdt : string;
  attribute max_lnk_wdt of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "000010";
  attribute mps : string;
  attribute mps of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "010";
  attribute no_soft_rst : string;
  attribute no_soft_rst of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "TRUE";
  attribute pci_exp_int_freq : integer;
  attribute pci_exp_int_freq of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is 1;
  attribute pci_exp_ref_freq : string;
  attribute pci_exp_ref_freq of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0";
  attribute phantm_func_sup : string;
  attribute phantm_func_sup of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00";
  attribute pme_sup : string;
  attribute pme_sup of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0F";
  attribute pwr_con_d0_state : string;
  attribute pwr_con_d0_state of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00";
  attribute pwr_con_d1_state : string;
  attribute pwr_con_d1_state of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00";
  attribute pwr_con_d2_state : string;
  attribute pwr_con_d2_state of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00";
  attribute pwr_con_d3_state : string;
  attribute pwr_con_d3_state of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00";
  attribute pwr_dis_d0_state : string;
  attribute pwr_dis_d0_state of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00";
  attribute pwr_dis_d1_state : string;
  attribute pwr_dis_d1_state of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00";
  attribute pwr_dis_d2_state : string;
  attribute pwr_dis_d2_state of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00";
  attribute pwr_dis_d3_state : string;
  attribute pwr_dis_d3_state of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00";
  attribute rev_id : string;
  attribute rev_id of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00";
  attribute slot_clk : string;
  attribute slot_clk of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "TRUE";
  attribute subsys_id : string;
  attribute subsys_id of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "0007";
  attribute subsys_ven_id : string;
  attribute subsys_ven_id of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "10EE";
  attribute ven_id : string;
  attribute ven_id of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "10EE";
  attribute xrom_bar : string;
  attribute xrom_bar of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top : entity is "00000000";
end spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top;

architecture STRUCTURE of spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top is
  signal \<const0>\ : STD_LOGIC;
  signal \<const1>\ : STD_LOGIC;
  signal \^cfg_command\ : STD_LOGIC_VECTOR ( 10 downto 0 );
  signal \^cfg_dcommand\ : STD_LOGIC_VECTOR ( 14 downto 0 );
  signal \^cfg_dcommand2\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \^cfg_dstatus\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^cfg_lcommand\ : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal \^cfg_lstatus\ : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal \^cfg_trn_pending\ : STD_LOGIC;
  signal \^int_dclk_out\ : STD_LOGIC;
  signal \^int_pipe_rxusrclk_out\ : STD_LOGIC;
  signal \^int_qplllock_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^int_qplloutclk_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^int_qplloutrefclk_out\ : STD_LOGIC_VECTOR ( 0 to 0 );
  signal \^m_axis_rx_tkeep\ : STD_LOGIC_VECTOR ( 6 downto 2 );
  signal \^m_axis_rx_tuser\ : STD_LOGIC_VECTOR ( 21 downto 0 );
  signal \^pipe_dmonitorout\ : STD_LOGIC_VECTOR ( 22 downto 0 );
  signal \^pipe_drp_fsm\ : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal \^pipe_qrst_fsm\ : STD_LOGIC_VECTOR ( 3 downto 0 );
  signal \^pipe_sync_fsm_rx\ : STD_LOGIC_VECTOR ( 7 downto 0 );
  signal \^user_clk_out\ : STD_LOGIC;
begin
  \^cfg_trn_pending\ <= cfg_trn_pending;
  cfg_command(15) <= \<const0>\;
  cfg_command(14) <= \<const0>\;
  cfg_command(13) <= \<const0>\;
  cfg_command(12) <= \<const0>\;
  cfg_command(11) <= \<const0>\;
  cfg_command(10) <= \^cfg_command\(10);
  cfg_command(9) <= \<const0>\;
  cfg_command(8) <= \^cfg_command\(8);
  cfg_command(7) <= \<const0>\;
  cfg_command(6) <= \<const0>\;
  cfg_command(5) <= \<const0>\;
  cfg_command(4) <= \<const0>\;
  cfg_command(3) <= \<const0>\;
  cfg_command(2 downto 0) <= \^cfg_command\(2 downto 0);
  cfg_dcommand(15) <= \<const0>\;
  cfg_dcommand(14 downto 0) <= \^cfg_dcommand\(14 downto 0);
  cfg_dcommand2(15) <= \<const0>\;
  cfg_dcommand2(14) <= \<const0>\;
  cfg_dcommand2(13) <= \<const0>\;
  cfg_dcommand2(12) <= \<const0>\;
  cfg_dcommand2(11 downto 0) <= \^cfg_dcommand2\(11 downto 0);
  cfg_dstatus(15) <= \<const0>\;
  cfg_dstatus(14) <= \<const0>\;
  cfg_dstatus(13) <= \<const0>\;
  cfg_dstatus(12) <= \<const0>\;
  cfg_dstatus(11) <= \<const0>\;
  cfg_dstatus(10) <= \<const0>\;
  cfg_dstatus(9) <= \<const0>\;
  cfg_dstatus(8) <= \<const0>\;
  cfg_dstatus(7) <= \<const0>\;
  cfg_dstatus(6) <= \<const0>\;
  cfg_dstatus(5) <= \^cfg_trn_pending\;
  cfg_dstatus(4) <= \<const0>\;
  cfg_dstatus(3 downto 0) <= \^cfg_dstatus\(3 downto 0);
  cfg_lcommand(15) <= \<const0>\;
  cfg_lcommand(14) <= \<const0>\;
  cfg_lcommand(13) <= \<const0>\;
  cfg_lcommand(12) <= \<const0>\;
  cfg_lcommand(11 downto 3) <= \^cfg_lcommand\(11 downto 3);
  cfg_lcommand(2) <= \<const0>\;
  cfg_lcommand(1 downto 0) <= \^cfg_lcommand\(1 downto 0);
  cfg_lstatus(15 downto 13) <= \^cfg_lstatus\(15 downto 13);
  cfg_lstatus(12) <= \<const1>\;
  cfg_lstatus(11) <= \^cfg_lstatus\(11);
  cfg_lstatus(10) <= \<const0>\;
  cfg_lstatus(9) <= \<const0>\;
  cfg_lstatus(8) <= \<const0>\;
  cfg_lstatus(7 downto 4) <= \^cfg_lstatus\(7 downto 4);
  cfg_lstatus(3) <= \<const0>\;
  cfg_lstatus(2) <= \<const0>\;
  cfg_lstatus(1 downto 0) <= \^cfg_lstatus\(1 downto 0);
  cfg_status(15) <= \<const0>\;
  cfg_status(14) <= \<const0>\;
  cfg_status(13) <= \<const0>\;
  cfg_status(12) <= \<const0>\;
  cfg_status(11) <= \<const0>\;
  cfg_status(10) <= \<const0>\;
  cfg_status(9) <= \<const0>\;
  cfg_status(8) <= \<const0>\;
  cfg_status(7) <= \<const0>\;
  cfg_status(6) <= \<const0>\;
  cfg_status(5) <= \<const0>\;
  cfg_status(4) <= \<const0>\;
  cfg_status(3) <= \<const0>\;
  cfg_status(2) <= \<const0>\;
  cfg_status(1) <= \<const0>\;
  cfg_status(0) <= \<const0>\;
  common_commands_out(11) <= \<const0>\;
  common_commands_out(10) <= \<const0>\;
  common_commands_out(9) <= \<const0>\;
  common_commands_out(8) <= \<const0>\;
  common_commands_out(7) <= \<const0>\;
  common_commands_out(6) <= \<const0>\;
  common_commands_out(5) <= \<const0>\;
  common_commands_out(4) <= \<const0>\;
  common_commands_out(3) <= \<const0>\;
  common_commands_out(2) <= \<const0>\;
  common_commands_out(1) <= \<const0>\;
  common_commands_out(0) <= \<const0>\;
  ext_ch_gt_drpclk <= \^int_dclk_out\;
  icap_o(31) <= \<const0>\;
  icap_o(30) <= \<const0>\;
  icap_o(29) <= \<const0>\;
  icap_o(28) <= \<const0>\;
  icap_o(27) <= \<const0>\;
  icap_o(26) <= \<const0>\;
  icap_o(25) <= \<const0>\;
  icap_o(24) <= \<const0>\;
  icap_o(23) <= \<const0>\;
  icap_o(22) <= \<const0>\;
  icap_o(21) <= \<const0>\;
  icap_o(20) <= \<const0>\;
  icap_o(19) <= \<const0>\;
  icap_o(18) <= \<const0>\;
  icap_o(17) <= \<const0>\;
  icap_o(16) <= \<const0>\;
  icap_o(15) <= \<const0>\;
  icap_o(14) <= \<const0>\;
  icap_o(13) <= \<const0>\;
  icap_o(12) <= \<const0>\;
  icap_o(11) <= \<const0>\;
  icap_o(10) <= \<const0>\;
  icap_o(9) <= \<const0>\;
  icap_o(8) <= \<const0>\;
  icap_o(7) <= \<const0>\;
  icap_o(6) <= \<const0>\;
  icap_o(5) <= \<const0>\;
  icap_o(4) <= \<const0>\;
  icap_o(3) <= \<const0>\;
  icap_o(2) <= \<const0>\;
  icap_o(1) <= \<const0>\;
  icap_o(0) <= \<const0>\;
  int_dclk_out <= \^int_dclk_out\;
  int_oobclk_out <= \^int_pipe_rxusrclk_out\;
  int_pclk_out_slave <= \<const0>\;
  int_pipe_rxusrclk_out <= \^int_pipe_rxusrclk_out\;
  int_qplllock_out(1) <= \<const0>\;
  int_qplllock_out(0) <= \^int_qplllock_out\(0);
  int_qplloutclk_out(1) <= \<const0>\;
  int_qplloutclk_out(0) <= \^int_qplloutclk_out\(0);
  int_qplloutrefclk_out(1) <= \<const0>\;
  int_qplloutrefclk_out(0) <= \^int_qplloutrefclk_out\(0);
  int_rxoutclk_out(1) <= \<const0>\;
  int_rxoutclk_out(0) <= \<const0>\;
  int_userclk1_out <= \^user_clk_out\;
  int_userclk2_out <= \^user_clk_out\;
  m_axis_rx_tkeep(7) <= \^m_axis_rx_tkeep\(6);
  m_axis_rx_tkeep(6) <= \^m_axis_rx_tkeep\(6);
  m_axis_rx_tkeep(5) <= \^m_axis_rx_tkeep\(6);
  m_axis_rx_tkeep(4) <= \^m_axis_rx_tkeep\(6);
  m_axis_rx_tkeep(3) <= \^m_axis_rx_tkeep\(2);
  m_axis_rx_tkeep(2) <= \^m_axis_rx_tkeep\(2);
  m_axis_rx_tkeep(1) <= \^m_axis_rx_tkeep\(2);
  m_axis_rx_tkeep(0) <= \^m_axis_rx_tkeep\(2);
  m_axis_rx_tuser(21) <= \^m_axis_rx_tuser\(21);
  m_axis_rx_tuser(20) <= \<const0>\;
  m_axis_rx_tuser(19) <= \^m_axis_rx_tuser\(19);
  m_axis_rx_tuser(18) <= \^m_axis_rx_tuser\(17);
  m_axis_rx_tuser(17) <= \^m_axis_rx_tuser\(17);
  m_axis_rx_tuser(16) <= \<const0>\;
  m_axis_rx_tuser(15) <= \<const0>\;
  m_axis_rx_tuser(14) <= \^m_axis_rx_tuser\(14);
  m_axis_rx_tuser(13) <= \<const0>\;
  m_axis_rx_tuser(12) <= \<const0>\;
  m_axis_rx_tuser(11) <= \<const0>\;
  m_axis_rx_tuser(10) <= \<const0>\;
  m_axis_rx_tuser(9) <= \<const0>\;
  m_axis_rx_tuser(8 downto 0) <= \^m_axis_rx_tuser\(8 downto 0);
  pipe_debug(31) <= \<const0>\;
  pipe_debug(30) <= \<const0>\;
  pipe_debug(29) <= \<const0>\;
  pipe_debug(28) <= \<const0>\;
  pipe_debug(27) <= \<const0>\;
  pipe_debug(26) <= \<const0>\;
  pipe_debug(25) <= \<const0>\;
  pipe_debug(24) <= \<const0>\;
  pipe_debug(23) <= \<const0>\;
  pipe_debug(22) <= \<const0>\;
  pipe_debug(21) <= \<const0>\;
  pipe_debug(20) <= \<const0>\;
  pipe_debug(19) <= \<const0>\;
  pipe_debug(18) <= \<const0>\;
  pipe_debug(17) <= \<const0>\;
  pipe_debug(16) <= \<const0>\;
  pipe_debug(15) <= \<const0>\;
  pipe_debug(14) <= \<const0>\;
  pipe_debug(13) <= \<const0>\;
  pipe_debug(12) <= \<const0>\;
  pipe_debug(11) <= \<const0>\;
  pipe_debug(10) <= \<const0>\;
  pipe_debug(9) <= \<const0>\;
  pipe_debug(8) <= \<const0>\;
  pipe_debug(7) <= \<const0>\;
  pipe_debug(6) <= \<const0>\;
  pipe_debug(5) <= \<const0>\;
  pipe_debug(4) <= \<const0>\;
  pipe_debug(3) <= \<const0>\;
  pipe_debug(2) <= \<const0>\;
  pipe_debug(1) <= \<const0>\;
  pipe_debug(0) <= \<const0>\;
  pipe_debug_0(1) <= \<const0>\;
  pipe_debug_0(0) <= \<const0>\;
  pipe_debug_1(1) <= \<const0>\;
  pipe_debug_1(0) <= \<const0>\;
  pipe_debug_2(1) <= \<const0>\;
  pipe_debug_2(0) <= \<const0>\;
  pipe_debug_3(1) <= \<const0>\;
  pipe_debug_3(0) <= \<const0>\;
  pipe_debug_4(1) <= \<const0>\;
  pipe_debug_4(0) <= \<const0>\;
  pipe_debug_5(1) <= \<const0>\;
  pipe_debug_5(0) <= \<const0>\;
  pipe_debug_6(1) <= \<const0>\;
  pipe_debug_6(0) <= \<const0>\;
  pipe_debug_7(1) <= \<const0>\;
  pipe_debug_7(0) <= \<const0>\;
  pipe_debug_8(1) <= \<const0>\;
  pipe_debug_8(0) <= \<const0>\;
  pipe_debug_9(1) <= \<const0>\;
  pipe_debug_9(0) <= \<const0>\;
  pipe_dmonitorout(29) <= \<const0>\;
  pipe_dmonitorout(28) <= \<const0>\;
  pipe_dmonitorout(27) <= \<const0>\;
  pipe_dmonitorout(26) <= \<const0>\;
  pipe_dmonitorout(25) <= \<const0>\;
  pipe_dmonitorout(24) <= \<const0>\;
  pipe_dmonitorout(23) <= \<const0>\;
  pipe_dmonitorout(22 downto 15) <= \^pipe_dmonitorout\(22 downto 15);
  pipe_dmonitorout(14) <= \<const0>\;
  pipe_dmonitorout(13) <= \<const0>\;
  pipe_dmonitorout(12) <= \<const0>\;
  pipe_dmonitorout(11) <= \<const0>\;
  pipe_dmonitorout(10) <= \<const0>\;
  pipe_dmonitorout(9) <= \<const0>\;
  pipe_dmonitorout(8) <= \<const0>\;
  pipe_dmonitorout(7 downto 0) <= \^pipe_dmonitorout\(7 downto 0);
  pipe_drp_fsm(13) <= \<const0>\;
  pipe_drp_fsm(12) <= \<const0>\;
  pipe_drp_fsm(11) <= \<const0>\;
  pipe_drp_fsm(10) <= \<const0>\;
  pipe_drp_fsm(9) <= \<const0>\;
  pipe_drp_fsm(8) <= \<const0>\;
  pipe_drp_fsm(7) <= \<const0>\;
  pipe_drp_fsm(6) <= \<const0>\;
  pipe_drp_fsm(5 downto 0) <= \^pipe_drp_fsm\(5 downto 0);
  pipe_qpll_lock(0) <= \^int_qplllock_out\(0);
  pipe_qrst_fsm(11) <= \<const0>\;
  pipe_qrst_fsm(10) <= \<const0>\;
  pipe_qrst_fsm(9) <= \<const0>\;
  pipe_qrst_fsm(8) <= \<const0>\;
  pipe_qrst_fsm(7) <= \<const0>\;
  pipe_qrst_fsm(6) <= \<const0>\;
  pipe_qrst_fsm(5) <= \<const0>\;
  pipe_qrst_fsm(4) <= \<const0>\;
  pipe_qrst_fsm(3 downto 0) <= \^pipe_qrst_fsm\(3 downto 0);
  pipe_rxpmaresetdone(1) <= \<const0>\;
  pipe_rxpmaresetdone(0) <= \<const0>\;
  pipe_rxsyncdone(1) <= \<const0>\;
  pipe_rxsyncdone(0) <= \<const0>\;
  pipe_sync_fsm_rx(13) <= \<const0>\;
  pipe_sync_fsm_rx(12) <= \<const0>\;
  pipe_sync_fsm_rx(11) <= \<const0>\;
  pipe_sync_fsm_rx(10) <= \<const0>\;
  pipe_sync_fsm_rx(9) <= \<const0>\;
  pipe_sync_fsm_rx(8) <= \<const0>\;
  pipe_sync_fsm_rx(7) <= \^pipe_sync_fsm_rx\(7);
  pipe_sync_fsm_rx(6) <= \<const0>\;
  pipe_sync_fsm_rx(5) <= \<const0>\;
  pipe_sync_fsm_rx(4) <= \<const0>\;
  pipe_sync_fsm_rx(3) <= \<const0>\;
  pipe_sync_fsm_rx(2) <= \<const0>\;
  pipe_sync_fsm_rx(1) <= \<const0>\;
  pipe_sync_fsm_rx(0) <= \^pipe_sync_fsm_rx\(0);
  pipe_tx_0_sigs(24) <= \<const0>\;
  pipe_tx_0_sigs(23) <= \<const0>\;
  pipe_tx_0_sigs(22) <= \<const0>\;
  pipe_tx_0_sigs(21) <= \<const0>\;
  pipe_tx_0_sigs(20) <= \<const0>\;
  pipe_tx_0_sigs(19) <= \<const0>\;
  pipe_tx_0_sigs(18) <= \<const0>\;
  pipe_tx_0_sigs(17) <= \<const0>\;
  pipe_tx_0_sigs(16) <= \<const0>\;
  pipe_tx_0_sigs(15) <= \<const0>\;
  pipe_tx_0_sigs(14) <= \<const0>\;
  pipe_tx_0_sigs(13) <= \<const0>\;
  pipe_tx_0_sigs(12) <= \<const0>\;
  pipe_tx_0_sigs(11) <= \<const0>\;
  pipe_tx_0_sigs(10) <= \<const0>\;
  pipe_tx_0_sigs(9) <= \<const0>\;
  pipe_tx_0_sigs(8) <= \<const0>\;
  pipe_tx_0_sigs(7) <= \<const0>\;
  pipe_tx_0_sigs(6) <= \<const0>\;
  pipe_tx_0_sigs(5) <= \<const0>\;
  pipe_tx_0_sigs(4) <= \<const0>\;
  pipe_tx_0_sigs(3) <= \<const0>\;
  pipe_tx_0_sigs(2) <= \<const0>\;
  pipe_tx_0_sigs(1) <= \<const0>\;
  pipe_tx_0_sigs(0) <= \<const0>\;
  pipe_tx_1_sigs(24) <= \<const0>\;
  pipe_tx_1_sigs(23) <= \<const0>\;
  pipe_tx_1_sigs(22) <= \<const0>\;
  pipe_tx_1_sigs(21) <= \<const0>\;
  pipe_tx_1_sigs(20) <= \<const0>\;
  pipe_tx_1_sigs(19) <= \<const0>\;
  pipe_tx_1_sigs(18) <= \<const0>\;
  pipe_tx_1_sigs(17) <= \<const0>\;
  pipe_tx_1_sigs(16) <= \<const0>\;
  pipe_tx_1_sigs(15) <= \<const0>\;
  pipe_tx_1_sigs(14) <= \<const0>\;
  pipe_tx_1_sigs(13) <= \<const0>\;
  pipe_tx_1_sigs(12) <= \<const0>\;
  pipe_tx_1_sigs(11) <= \<const0>\;
  pipe_tx_1_sigs(10) <= \<const0>\;
  pipe_tx_1_sigs(9) <= \<const0>\;
  pipe_tx_1_sigs(8) <= \<const0>\;
  pipe_tx_1_sigs(7) <= \<const0>\;
  pipe_tx_1_sigs(6) <= \<const0>\;
  pipe_tx_1_sigs(5) <= \<const0>\;
  pipe_tx_1_sigs(4) <= \<const0>\;
  pipe_tx_1_sigs(3) <= \<const0>\;
  pipe_tx_1_sigs(2) <= \<const0>\;
  pipe_tx_1_sigs(1) <= \<const0>\;
  pipe_tx_1_sigs(0) <= \<const0>\;
  pipe_tx_2_sigs(24) <= \<const0>\;
  pipe_tx_2_sigs(23) <= \<const0>\;
  pipe_tx_2_sigs(22) <= \<const0>\;
  pipe_tx_2_sigs(21) <= \<const0>\;
  pipe_tx_2_sigs(20) <= \<const0>\;
  pipe_tx_2_sigs(19) <= \<const0>\;
  pipe_tx_2_sigs(18) <= \<const0>\;
  pipe_tx_2_sigs(17) <= \<const0>\;
  pipe_tx_2_sigs(16) <= \<const0>\;
  pipe_tx_2_sigs(15) <= \<const0>\;
  pipe_tx_2_sigs(14) <= \<const0>\;
  pipe_tx_2_sigs(13) <= \<const0>\;
  pipe_tx_2_sigs(12) <= \<const0>\;
  pipe_tx_2_sigs(11) <= \<const0>\;
  pipe_tx_2_sigs(10) <= \<const0>\;
  pipe_tx_2_sigs(9) <= \<const0>\;
  pipe_tx_2_sigs(8) <= \<const0>\;
  pipe_tx_2_sigs(7) <= \<const0>\;
  pipe_tx_2_sigs(6) <= \<const0>\;
  pipe_tx_2_sigs(5) <= \<const0>\;
  pipe_tx_2_sigs(4) <= \<const0>\;
  pipe_tx_2_sigs(3) <= \<const0>\;
  pipe_tx_2_sigs(2) <= \<const0>\;
  pipe_tx_2_sigs(1) <= \<const0>\;
  pipe_tx_2_sigs(0) <= \<const0>\;
  pipe_tx_3_sigs(24) <= \<const0>\;
  pipe_tx_3_sigs(23) <= \<const0>\;
  pipe_tx_3_sigs(22) <= \<const0>\;
  pipe_tx_3_sigs(21) <= \<const0>\;
  pipe_tx_3_sigs(20) <= \<const0>\;
  pipe_tx_3_sigs(19) <= \<const0>\;
  pipe_tx_3_sigs(18) <= \<const0>\;
  pipe_tx_3_sigs(17) <= \<const0>\;
  pipe_tx_3_sigs(16) <= \<const0>\;
  pipe_tx_3_sigs(15) <= \<const0>\;
  pipe_tx_3_sigs(14) <= \<const0>\;
  pipe_tx_3_sigs(13) <= \<const0>\;
  pipe_tx_3_sigs(12) <= \<const0>\;
  pipe_tx_3_sigs(11) <= \<const0>\;
  pipe_tx_3_sigs(10) <= \<const0>\;
  pipe_tx_3_sigs(9) <= \<const0>\;
  pipe_tx_3_sigs(8) <= \<const0>\;
  pipe_tx_3_sigs(7) <= \<const0>\;
  pipe_tx_3_sigs(6) <= \<const0>\;
  pipe_tx_3_sigs(5) <= \<const0>\;
  pipe_tx_3_sigs(4) <= \<const0>\;
  pipe_tx_3_sigs(3) <= \<const0>\;
  pipe_tx_3_sigs(2) <= \<const0>\;
  pipe_tx_3_sigs(1) <= \<const0>\;
  pipe_tx_3_sigs(0) <= \<const0>\;
  pipe_tx_4_sigs(24) <= \<const0>\;
  pipe_tx_4_sigs(23) <= \<const0>\;
  pipe_tx_4_sigs(22) <= \<const0>\;
  pipe_tx_4_sigs(21) <= \<const0>\;
  pipe_tx_4_sigs(20) <= \<const0>\;
  pipe_tx_4_sigs(19) <= \<const0>\;
  pipe_tx_4_sigs(18) <= \<const0>\;
  pipe_tx_4_sigs(17) <= \<const0>\;
  pipe_tx_4_sigs(16) <= \<const0>\;
  pipe_tx_4_sigs(15) <= \<const0>\;
  pipe_tx_4_sigs(14) <= \<const0>\;
  pipe_tx_4_sigs(13) <= \<const0>\;
  pipe_tx_4_sigs(12) <= \<const0>\;
  pipe_tx_4_sigs(11) <= \<const0>\;
  pipe_tx_4_sigs(10) <= \<const0>\;
  pipe_tx_4_sigs(9) <= \<const0>\;
  pipe_tx_4_sigs(8) <= \<const0>\;
  pipe_tx_4_sigs(7) <= \<const0>\;
  pipe_tx_4_sigs(6) <= \<const0>\;
  pipe_tx_4_sigs(5) <= \<const0>\;
  pipe_tx_4_sigs(4) <= \<const0>\;
  pipe_tx_4_sigs(3) <= \<const0>\;
  pipe_tx_4_sigs(2) <= \<const0>\;
  pipe_tx_4_sigs(1) <= \<const0>\;
  pipe_tx_4_sigs(0) <= \<const0>\;
  pipe_tx_5_sigs(24) <= \<const0>\;
  pipe_tx_5_sigs(23) <= \<const0>\;
  pipe_tx_5_sigs(22) <= \<const0>\;
  pipe_tx_5_sigs(21) <= \<const0>\;
  pipe_tx_5_sigs(20) <= \<const0>\;
  pipe_tx_5_sigs(19) <= \<const0>\;
  pipe_tx_5_sigs(18) <= \<const0>\;
  pipe_tx_5_sigs(17) <= \<const0>\;
  pipe_tx_5_sigs(16) <= \<const0>\;
  pipe_tx_5_sigs(15) <= \<const0>\;
  pipe_tx_5_sigs(14) <= \<const0>\;
  pipe_tx_5_sigs(13) <= \<const0>\;
  pipe_tx_5_sigs(12) <= \<const0>\;
  pipe_tx_5_sigs(11) <= \<const0>\;
  pipe_tx_5_sigs(10) <= \<const0>\;
  pipe_tx_5_sigs(9) <= \<const0>\;
  pipe_tx_5_sigs(8) <= \<const0>\;
  pipe_tx_5_sigs(7) <= \<const0>\;
  pipe_tx_5_sigs(6) <= \<const0>\;
  pipe_tx_5_sigs(5) <= \<const0>\;
  pipe_tx_5_sigs(4) <= \<const0>\;
  pipe_tx_5_sigs(3) <= \<const0>\;
  pipe_tx_5_sigs(2) <= \<const0>\;
  pipe_tx_5_sigs(1) <= \<const0>\;
  pipe_tx_5_sigs(0) <= \<const0>\;
  pipe_tx_6_sigs(24) <= \<const0>\;
  pipe_tx_6_sigs(23) <= \<const0>\;
  pipe_tx_6_sigs(22) <= \<const0>\;
  pipe_tx_6_sigs(21) <= \<const0>\;
  pipe_tx_6_sigs(20) <= \<const0>\;
  pipe_tx_6_sigs(19) <= \<const0>\;
  pipe_tx_6_sigs(18) <= \<const0>\;
  pipe_tx_6_sigs(17) <= \<const0>\;
  pipe_tx_6_sigs(16) <= \<const0>\;
  pipe_tx_6_sigs(15) <= \<const0>\;
  pipe_tx_6_sigs(14) <= \<const0>\;
  pipe_tx_6_sigs(13) <= \<const0>\;
  pipe_tx_6_sigs(12) <= \<const0>\;
  pipe_tx_6_sigs(11) <= \<const0>\;
  pipe_tx_6_sigs(10) <= \<const0>\;
  pipe_tx_6_sigs(9) <= \<const0>\;
  pipe_tx_6_sigs(8) <= \<const0>\;
  pipe_tx_6_sigs(7) <= \<const0>\;
  pipe_tx_6_sigs(6) <= \<const0>\;
  pipe_tx_6_sigs(5) <= \<const0>\;
  pipe_tx_6_sigs(4) <= \<const0>\;
  pipe_tx_6_sigs(3) <= \<const0>\;
  pipe_tx_6_sigs(2) <= \<const0>\;
  pipe_tx_6_sigs(1) <= \<const0>\;
  pipe_tx_6_sigs(0) <= \<const0>\;
  pipe_tx_7_sigs(24) <= \<const0>\;
  pipe_tx_7_sigs(23) <= \<const0>\;
  pipe_tx_7_sigs(22) <= \<const0>\;
  pipe_tx_7_sigs(21) <= \<const0>\;
  pipe_tx_7_sigs(20) <= \<const0>\;
  pipe_tx_7_sigs(19) <= \<const0>\;
  pipe_tx_7_sigs(18) <= \<const0>\;
  pipe_tx_7_sigs(17) <= \<const0>\;
  pipe_tx_7_sigs(16) <= \<const0>\;
  pipe_tx_7_sigs(15) <= \<const0>\;
  pipe_tx_7_sigs(14) <= \<const0>\;
  pipe_tx_7_sigs(13) <= \<const0>\;
  pipe_tx_7_sigs(12) <= \<const0>\;
  pipe_tx_7_sigs(11) <= \<const0>\;
  pipe_tx_7_sigs(10) <= \<const0>\;
  pipe_tx_7_sigs(9) <= \<const0>\;
  pipe_tx_7_sigs(8) <= \<const0>\;
  pipe_tx_7_sigs(7) <= \<const0>\;
  pipe_tx_7_sigs(6) <= \<const0>\;
  pipe_tx_7_sigs(5) <= \<const0>\;
  pipe_tx_7_sigs(4) <= \<const0>\;
  pipe_tx_7_sigs(3) <= \<const0>\;
  pipe_tx_7_sigs(2) <= \<const0>\;
  pipe_tx_7_sigs(1) <= \<const0>\;
  pipe_tx_7_sigs(0) <= \<const0>\;
  qpll_drp_clk <= \<const0>\;
  qpll_drp_gen3 <= \<const0>\;
  qpll_drp_ovrd <= \<const0>\;
  qpll_drp_rst_n <= \<const0>\;
  qpll_drp_start <= \<const0>\;
  qpll_qplld <= \<const0>\;
  qpll_qpllreset(1) <= \<const0>\;
  qpll_qpllreset(0) <= \<const0>\;
  startup_cfgclk <= \<const0>\;
  startup_cfgmclk <= \<const0>\;
  startup_eos <= \<const0>\;
  startup_preq <= \<const0>\;
  user_app_rdy <= \<const1>\;
  user_clk_out <= \^user_clk_out\;
GND: unisim.vcomponents.GND
     port map (
      G => \<const0>\
    );
VCC: unisim.vcomponents.VCC
     port map (
      P => \<const1>\
    );
inst: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_core_top
     port map (
      \FSM_onehot_fsm_reg[10]\(1) => pipe_rst_idle,
      \FSM_onehot_fsm_reg[10]\(0) => pipe_rst_fsm(4),
      \FSM_onehot_txsync_fsm.fsm_tx_reg[6]\(5 downto 0) => pipe_sync_fsm_tx(5 downto 0),
      \FSM_onehot_txsync_fsm.fsm_tx_reg[6]_0\(5 downto 0) => pipe_sync_fsm_tx(11 downto 6),
      Q(2 downto 0) => \^pipe_drp_fsm\(2 downto 0),
      QRST_IDLE => pipe_qrst_idle,
      cfg_aer_ecrc_check_en => cfg_aer_ecrc_check_en,
      cfg_aer_ecrc_gen_en => cfg_aer_ecrc_gen_en,
      cfg_aer_interrupt_msgnum(4 downto 0) => cfg_aer_interrupt_msgnum(4 downto 0),
      cfg_aer_rooterr_corr_err_received => cfg_aer_rooterr_corr_err_received,
      cfg_aer_rooterr_corr_err_reporting_en => cfg_aer_rooterr_corr_err_reporting_en,
      cfg_aer_rooterr_fatal_err_received => cfg_aer_rooterr_fatal_err_received,
      cfg_aer_rooterr_fatal_err_reporting_en => cfg_aer_rooterr_fatal_err_reporting_en,
      cfg_aer_rooterr_non_fatal_err_received => cfg_aer_rooterr_non_fatal_err_received,
      cfg_aer_rooterr_non_fatal_err_reporting_en => cfg_aer_rooterr_non_fatal_err_reporting_en,
      cfg_bridge_serr_en => cfg_bridge_serr_en,
      cfg_bus_number(7 downto 0) => cfg_bus_number(7 downto 0),
      cfg_command(4) => \^cfg_command\(10),
      cfg_command(3) => \^cfg_command\(8),
      cfg_command(2 downto 0) => \^cfg_command\(2 downto 0),
      cfg_dcommand(14 downto 0) => \^cfg_dcommand\(14 downto 0),
      cfg_dcommand2(11 downto 0) => \^cfg_dcommand2\(11 downto 0),
      cfg_device_number(4 downto 0) => cfg_device_number(4 downto 0),
      cfg_ds_bus_number(7 downto 0) => cfg_ds_bus_number(7 downto 0),
      cfg_ds_device_number(4 downto 0) => cfg_ds_device_number(4 downto 0),
      cfg_ds_function_number(2 downto 0) => cfg_ds_function_number(2 downto 0),
      cfg_dsn(63 downto 0) => cfg_dsn(63 downto 0),
      cfg_dstatus(3 downto 0) => \^cfg_dstatus\(3 downto 0),
      cfg_err_aer_headerlog(127 downto 0) => cfg_err_aer_headerlog(127 downto 0),
      cfg_err_aer_headerlog_set => cfg_err_aer_headerlog_set,
      cfg_err_atomic_egress_blocked => cfg_err_atomic_egress_blocked,
      cfg_err_cor => cfg_err_cor,
      cfg_err_cpl_abort => cfg_err_cpl_abort,
      cfg_err_cpl_rdy => cfg_err_cpl_rdy,
      cfg_err_cpl_timeout => cfg_err_cpl_timeout,
      cfg_err_cpl_unexpect => cfg_err_cpl_unexpect,
      cfg_err_ecrc => cfg_err_ecrc,
      cfg_err_internal_cor => cfg_err_internal_cor,
      cfg_err_internal_uncor => cfg_err_internal_uncor,
      cfg_err_locked => cfg_err_locked,
      cfg_err_malformed => cfg_err_malformed,
      cfg_err_mc_blocked => cfg_err_mc_blocked,
      cfg_err_norecovery => cfg_err_norecovery,
      cfg_err_poisoned => cfg_err_poisoned,
      cfg_err_posted => cfg_err_posted,
      cfg_err_tlp_cpl_header(47 downto 0) => cfg_err_tlp_cpl_header(47 downto 0),
      cfg_err_ur => cfg_err_ur,
      cfg_function_number(2 downto 0) => cfg_function_number(2 downto 0),
      cfg_interrupt => cfg_interrupt,
      cfg_interrupt_assert => cfg_interrupt_assert,
      cfg_interrupt_di(7 downto 0) => cfg_interrupt_di(7 downto 0),
      cfg_interrupt_do(7 downto 0) => cfg_interrupt_do(7 downto 0),
      cfg_interrupt_mmenable(2 downto 0) => cfg_interrupt_mmenable(2 downto 0),
      cfg_interrupt_msienable => cfg_interrupt_msienable,
      cfg_interrupt_msixenable => cfg_interrupt_msixenable,
      cfg_interrupt_msixfm => cfg_interrupt_msixfm,
      cfg_interrupt_rdy => cfg_interrupt_rdy,
      cfg_interrupt_stat => cfg_interrupt_stat,
      cfg_lcommand(10 downto 2) => \^cfg_lcommand\(11 downto 3),
      cfg_lcommand(1 downto 0) => \^cfg_lcommand\(1 downto 0),
      cfg_lstatus(9 downto 7) => \^cfg_lstatus\(15 downto 13),
      cfg_lstatus(6) => \^cfg_lstatus\(11),
      cfg_lstatus(5 downto 2) => \^cfg_lstatus\(7 downto 4),
      cfg_lstatus(1 downto 0) => \^cfg_lstatus\(1 downto 0),
      cfg_mgmt_byte_en(3 downto 0) => cfg_mgmt_byte_en(3 downto 0),
      cfg_mgmt_di(31 downto 0) => cfg_mgmt_di(31 downto 0),
      cfg_mgmt_do(31 downto 0) => cfg_mgmt_do(31 downto 0),
      cfg_mgmt_dwaddr(9 downto 0) => cfg_mgmt_dwaddr(9 downto 0),
      cfg_mgmt_rd_en => cfg_mgmt_rd_en,
      cfg_mgmt_rd_wr_done => cfg_mgmt_rd_wr_done,
      cfg_mgmt_wr_en => cfg_mgmt_wr_en,
      cfg_mgmt_wr_readonly => cfg_mgmt_wr_readonly,
      cfg_mgmt_wr_rw1c_as_rw => cfg_mgmt_wr_rw1c_as_rw,
      cfg_msg_data(15 downto 0) => cfg_msg_data(15 downto 0),
      cfg_msg_received => cfg_msg_received,
      cfg_msg_received_assert_int_a => cfg_msg_received_assert_int_a,
      cfg_msg_received_assert_int_b => cfg_msg_received_assert_int_b,
      cfg_msg_received_assert_int_c => cfg_msg_received_assert_int_c,
      cfg_msg_received_assert_int_d => cfg_msg_received_assert_int_d,
      cfg_msg_received_deassert_int_a => cfg_msg_received_deassert_int_a,
      cfg_msg_received_deassert_int_b => cfg_msg_received_deassert_int_b,
      cfg_msg_received_deassert_int_c => cfg_msg_received_deassert_int_c,
      cfg_msg_received_deassert_int_d => cfg_msg_received_deassert_int_d,
      cfg_msg_received_err_cor => cfg_msg_received_err_cor,
      cfg_msg_received_err_fatal => cfg_msg_received_err_fatal,
      cfg_msg_received_err_non_fatal => cfg_msg_received_err_non_fatal,
      cfg_msg_received_pm_as_nak => cfg_msg_received_pm_as_nak,
      cfg_msg_received_pm_pme => cfg_msg_received_pm_pme,
      cfg_msg_received_pme_to_ack => cfg_msg_received_pme_to_ack,
      cfg_msg_received_setslotpowerlimit => cfg_msg_received_setslotpowerlimit,
      cfg_pcie_link_state(2 downto 0) => cfg_pcie_link_state(2 downto 0),
      cfg_pciecap_interrupt_msgnum(4 downto 0) => cfg_pciecap_interrupt_msgnum(4 downto 0),
      cfg_pm_force_state(1 downto 0) => cfg_pm_force_state(1 downto 0),
      cfg_pm_force_state_en => cfg_pm_force_state_en,
      cfg_pm_halt_aspm_l0s => cfg_pm_halt_aspm_l0s,
      cfg_pm_halt_aspm_l1 => cfg_pm_halt_aspm_l1,
      cfg_pm_wake => cfg_pm_wake,
      cfg_pmcsr_pme_en => cfg_pmcsr_pme_en,
      cfg_pmcsr_pme_status => cfg_pmcsr_pme_status,
      cfg_pmcsr_powerstate(1 downto 0) => cfg_pmcsr_powerstate(1 downto 0),
      cfg_received_func_lvl_rst => cfg_received_func_lvl_rst,
      cfg_root_control_pme_int_en => cfg_root_control_pme_int_en,
      cfg_root_control_syserr_corr_err_en => cfg_root_control_syserr_corr_err_en,
      cfg_root_control_syserr_fatal_err_en => cfg_root_control_syserr_fatal_err_en,
      cfg_root_control_syserr_non_fatal_err_en => cfg_root_control_syserr_non_fatal_err_en,
      cfg_slot_control_electromech_il_ctl_pulse => cfg_slot_control_electromech_il_ctl_pulse,
      cfg_to_turnoff => cfg_to_turnoff,
      cfg_trn_pending => \^cfg_trn_pending\,
      cfg_turnoff_ok => cfg_turnoff_ok,
      cfg_vc_tcvc_map(6 downto 0) => cfg_vc_tcvc_map(6 downto 0),
      ext_ch_gt_drpaddr(17 downto 0) => ext_ch_gt_drpaddr(17 downto 0),
      ext_ch_gt_drpdi(31 downto 0) => ext_ch_gt_drpdi(31 downto 0),
      ext_ch_gt_drpdo(31 downto 0) => ext_ch_gt_drpdo(31 downto 0),
      ext_ch_gt_drpen(1 downto 0) => ext_ch_gt_drpen(1 downto 0),
      ext_ch_gt_drprdy(1 downto 0) => ext_ch_gt_drprdy(1 downto 0),
      ext_ch_gt_drpwe(1 downto 0) => ext_ch_gt_drpwe(1 downto 0),
      fc_cpld(11 downto 0) => fc_cpld(11 downto 0),
      fc_cplh(7 downto 0) => fc_cplh(7 downto 0),
      fc_npd(11 downto 0) => fc_npd(11 downto 0),
      fc_nph(7 downto 0) => fc_nph(7 downto 0),
      fc_pd(11 downto 0) => fc_pd(11 downto 0),
      fc_ph(7 downto 0) => fc_ph(7 downto 0),
      fc_sel(2 downto 0) => fc_sel(2 downto 0),
      \fsm_reg[2]\(2 downto 0) => \^pipe_drp_fsm\(5 downto 3),
      gen3_reg => pipe_gen3_out,
      gt_ch_drp_rdy(1 downto 0) => gt_ch_drp_rdy(1 downto 0),
      int_dclk_out => \^int_dclk_out\,
      int_mmcm_lock_out => int_mmcm_lock_out,
      int_pclk_sel_slave(1 downto 0) => int_pclk_sel_slave(1 downto 0),
      int_pipe_rxusrclk_out => \^int_pipe_rxusrclk_out\,
      int_qplllock_out(0) => \^int_qplllock_out\(0),
      int_qplloutclk_out(0) => \^int_qplloutclk_out\(0),
      int_qplloutrefclk_out(0) => \^int_qplloutrefclk_out\(0),
      int_userclk1_out => \^user_clk_out\,
      m_axis_rx_tdata(63 downto 0) => m_axis_rx_tdata(63 downto 0),
      m_axis_rx_tkeep(1) => \^m_axis_rx_tkeep\(6),
      m_axis_rx_tkeep(0) => \^m_axis_rx_tkeep\(2),
      m_axis_rx_tlast => m_axis_rx_tlast,
      m_axis_rx_tready => m_axis_rx_tready,
      m_axis_rx_tuser(12) => \^m_axis_rx_tuser\(21),
      m_axis_rx_tuser(11) => \^m_axis_rx_tuser\(19),
      m_axis_rx_tuser(10) => \^m_axis_rx_tuser\(17),
      m_axis_rx_tuser(9) => \^m_axis_rx_tuser\(14),
      m_axis_rx_tuser(8 downto 0) => \^m_axis_rx_tuser\(8 downto 0),
      m_axis_rx_tvalid => m_axis_rx_tvalid,
      pci_exp_rxn(1 downto 0) => pci_exp_rxn(1 downto 0),
      pci_exp_rxp(1 downto 0) => pci_exp_rxp(1 downto 0),
      pci_exp_txn(1 downto 0) => pci_exp_txn(1 downto 0),
      pci_exp_txp(1 downto 0) => pci_exp_txp(1 downto 0),
      pcie_drp_addr(8 downto 0) => pcie_drp_addr(8 downto 0),
      pcie_drp_clk => pcie_drp_clk,
      pcie_drp_di(15 downto 0) => pcie_drp_di(15 downto 0),
      pcie_drp_do(15 downto 0) => pcie_drp_do(15 downto 0),
      pcie_drp_en => pcie_drp_en,
      pcie_drp_rdy => pcie_drp_rdy,
      pcie_drp_we => pcie_drp_we,
      pipe_cpll_lock(1 downto 0) => pipe_cpll_lock(1 downto 0),
      pipe_dmonitorout(15 downto 8) => \^pipe_dmonitorout\(22 downto 15),
      pipe_dmonitorout(7 downto 0) => \^pipe_dmonitorout\(7 downto 0),
      pipe_eyescandataerror(1 downto 0) => pipe_eyescandataerror(1 downto 0),
      pipe_mmcm_rst_n => pipe_mmcm_rst_n,
      pipe_pclk_sel_out(1 downto 0) => pipe_pclk_sel_out(1 downto 0),
      pipe_qrst_fsm(3 downto 0) => \^pipe_qrst_fsm\(3 downto 0),
      pipe_rate_fsm(9 downto 0) => pipe_rate_fsm(9 downto 0),
      pipe_rate_idle => pipe_rate_idle,
      pipe_rst_fsm(3 downto 0) => pipe_rst_fsm(3 downto 0),
      pipe_rxbufstatus(5 downto 0) => pipe_rxbufstatus(5 downto 0),
      pipe_rxcommadet(1 downto 0) => pipe_rxcommadet(1 downto 0),
      pipe_rxdisperr(15 downto 0) => pipe_rxdisperr(15 downto 0),
      pipe_rxdlysresetdone(1 downto 0) => pipe_rxdlysresetdone(1 downto 0),
      pipe_rxnotintable(15 downto 0) => pipe_rxnotintable(15 downto 0),
      pipe_rxoutclk_out(1 downto 0) => pipe_rxoutclk_out(1 downto 0),
      pipe_rxphaligndone(1 downto 0) => pipe_rxphaligndone(1 downto 0),
      pipe_rxprbserr(1 downto 0) => pipe_rxprbserr(1 downto 0),
      pipe_rxstatus(5 downto 0) => pipe_rxstatus(5 downto 0),
      pipe_sync_fsm_rx(1) => \^pipe_sync_fsm_rx\(7),
      pipe_sync_fsm_rx(0) => \^pipe_sync_fsm_rx\(0),
      pipe_txdlysresetdone(1 downto 0) => pipe_txdlysresetdone(1 downto 0),
      pipe_txinhibit(1 downto 0) => pipe_txinhibit(1 downto 0),
      pipe_txoutclk_out => pipe_txoutclk_out,
      pipe_txphaligndone(1 downto 0) => pipe_txphaligndone(1 downto 0),
      pipe_txphinitdone(1 downto 0) => pipe_txphinitdone(1 downto 0),
      pl_directed_change_done => pl_directed_change_done,
      pl_directed_link_auton => pl_directed_link_auton,
      pl_directed_link_change(1 downto 0) => pl_directed_link_change(1 downto 0),
      pl_directed_link_speed => pl_directed_link_speed,
      pl_directed_link_width(1 downto 0) => pl_directed_link_width(1 downto 0),
      pl_downstream_deemph_source => pl_downstream_deemph_source,
      pl_initial_link_width(2 downto 0) => pl_initial_link_width(2 downto 0),
      pl_lane_reversal_mode(1 downto 0) => pl_lane_reversal_mode(1 downto 0),
      pl_link_gen2_cap => pl_link_gen2_cap,
      pl_link_partner_gen2_supported => pl_link_partner_gen2_supported,
      pl_link_upcfg_cap => pl_link_upcfg_cap,
      pl_ltssm_state(5 downto 0) => pl_ltssm_state(5 downto 0),
      pl_phy_lnk_up => pl_phy_lnk_up,
      pl_received_hot_rst => pl_received_hot_rst,
      pl_rx_pm_state(1 downto 0) => pl_rx_pm_state(1 downto 0),
      pl_sel_lnk_rate => pl_sel_lnk_rate,
      pl_sel_lnk_width(1 downto 0) => pl_sel_lnk_width(1 downto 0),
      pl_transmit_hot_rst => pl_transmit_hot_rst,
      pl_tx_pm_state(2 downto 0) => pl_tx_pm_state(2 downto 0),
      pl_upstream_prefer_deemph => pl_upstream_prefer_deemph,
      rx_np_ok => rx_np_ok,
      rx_np_req => rx_np_req,
      s_axis_tx_tdata(63 downto 0) => s_axis_tx_tdata(63 downto 0),
      s_axis_tx_tkeep(0) => s_axis_tx_tkeep(7),
      s_axis_tx_tlast => s_axis_tx_tlast,
      s_axis_tx_tready => s_axis_tx_tready,
      s_axis_tx_tuser(3 downto 0) => s_axis_tx_tuser(3 downto 0),
      s_axis_tx_tvalid => s_axis_tx_tvalid,
      sys_clk => sys_clk,
      sys_rst_n => sys_rst_n,
      tx_buf_av(5 downto 0) => tx_buf_av(5 downto 0),
      tx_cfg_gnt => tx_cfg_gnt,
      tx_cfg_req => tx_cfg_req,
      tx_err_drop => tx_err_drop,
      user_lnk_up => user_lnk_up,
      user_reset_out => user_reset_out
    );
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_pcie_7x_0 is
  port (
    pci_exp_txp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_txn : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_rxp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pci_exp_rxn : in STD_LOGIC_VECTOR ( 1 downto 0 );
    user_clk_out : out STD_LOGIC;
    user_reset_out : out STD_LOGIC;
    user_lnk_up : out STD_LOGIC;
    user_app_rdy : out STD_LOGIC;
    tx_buf_av : out STD_LOGIC_VECTOR ( 5 downto 0 );
    tx_cfg_req : out STD_LOGIC;
    tx_err_drop : out STD_LOGIC;
    s_axis_tx_tready : out STD_LOGIC;
    s_axis_tx_tdata : in STD_LOGIC_VECTOR ( 63 downto 0 );
    s_axis_tx_tkeep : in STD_LOGIC_VECTOR ( 7 downto 0 );
    s_axis_tx_tlast : in STD_LOGIC;
    s_axis_tx_tvalid : in STD_LOGIC;
    s_axis_tx_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
    tx_cfg_gnt : in STD_LOGIC;
    m_axis_rx_tdata : out STD_LOGIC_VECTOR ( 63 downto 0 );
    m_axis_rx_tkeep : out STD_LOGIC_VECTOR ( 7 downto 0 );
    m_axis_rx_tlast : out STD_LOGIC;
    m_axis_rx_tvalid : out STD_LOGIC;
    m_axis_rx_tready : in STD_LOGIC;
    m_axis_rx_tuser : out STD_LOGIC_VECTOR ( 21 downto 0 );
    rx_np_ok : in STD_LOGIC;
    rx_np_req : in STD_LOGIC;
    fc_cpld : out STD_LOGIC_VECTOR ( 11 downto 0 );
    fc_cplh : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_npd : out STD_LOGIC_VECTOR ( 11 downto 0 );
    fc_nph : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_pd : out STD_LOGIC_VECTOR ( 11 downto 0 );
    fc_ph : out STD_LOGIC_VECTOR ( 7 downto 0 );
    fc_sel : in STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_mgmt_do : out STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_mgmt_rd_wr_done : out STD_LOGIC;
    cfg_status : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_command : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_dstatus : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_dcommand : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_lstatus : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_lcommand : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_dcommand2 : out STD_LOGIC_VECTOR ( 15 downto 0 );
    cfg_pcie_link_state : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_pmcsr_pme_en : out STD_LOGIC;
    cfg_pmcsr_powerstate : out STD_LOGIC_VECTOR ( 1 downto 0 );
    cfg_pmcsr_pme_status : out STD_LOGIC;
    cfg_received_func_lvl_rst : out STD_LOGIC;
    cfg_mgmt_di : in STD_LOGIC_VECTOR ( 31 downto 0 );
    cfg_mgmt_byte_en : in STD_LOGIC_VECTOR ( 3 downto 0 );
    cfg_mgmt_dwaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
    cfg_mgmt_wr_en : in STD_LOGIC;
    cfg_mgmt_rd_en : in STD_LOGIC;
    cfg_mgmt_wr_readonly : in STD_LOGIC;
    cfg_err_ecrc : in STD_LOGIC;
    cfg_err_ur : in STD_LOGIC;
    cfg_err_cpl_timeout : in STD_LOGIC;
    cfg_err_cpl_unexpect : in STD_LOGIC;
    cfg_err_cpl_abort : in STD_LOGIC;
    cfg_err_posted : in STD_LOGIC;
    cfg_err_cor : in STD_LOGIC;
    cfg_err_atomic_egress_blocked : in STD_LOGIC;
    cfg_err_internal_cor : in STD_LOGIC;
    cfg_err_malformed : in STD_LOGIC;
    cfg_err_mc_blocked : in STD_LOGIC;
    cfg_err_poisoned : in STD_LOGIC;
    cfg_err_norecovery : in STD_LOGIC;
    cfg_err_tlp_cpl_header : in STD_LOGIC_VECTOR ( 47 downto 0 );
    cfg_err_cpl_rdy : out STD_LOGIC;
    cfg_err_locked : in STD_LOGIC;
    cfg_err_acs : in STD_LOGIC;
    cfg_err_internal_uncor : in STD_LOGIC;
    cfg_trn_pending : in STD_LOGIC;
    cfg_pm_halt_aspm_l0s : in STD_LOGIC;
    cfg_pm_halt_aspm_l1 : in STD_LOGIC;
    cfg_pm_force_state_en : in STD_LOGIC;
    cfg_pm_force_state : in STD_LOGIC_VECTOR ( 1 downto 0 );
    cfg_dsn : in STD_LOGIC_VECTOR ( 63 downto 0 );
    cfg_interrupt : in STD_LOGIC;
    cfg_interrupt_rdy : out STD_LOGIC;
    cfg_interrupt_assert : in STD_LOGIC;
    cfg_interrupt_di : in STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_interrupt_do : out STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_interrupt_mmenable : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_interrupt_msienable : out STD_LOGIC;
    cfg_interrupt_msixenable : out STD_LOGIC;
    cfg_interrupt_msixfm : out STD_LOGIC;
    cfg_interrupt_stat : in STD_LOGIC;
    cfg_pciecap_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_to_turnoff : out STD_LOGIC;
    cfg_turnoff_ok : in STD_LOGIC;
    cfg_bus_number : out STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_device_number : out STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_function_number : out STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_pm_wake : in STD_LOGIC;
    cfg_pm_send_pme_to : in STD_LOGIC;
    cfg_ds_bus_number : in STD_LOGIC_VECTOR ( 7 downto 0 );
    cfg_ds_device_number : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_ds_function_number : in STD_LOGIC_VECTOR ( 2 downto 0 );
    cfg_mgmt_wr_rw1c_as_rw : in STD_LOGIC;
    cfg_bridge_serr_en : out STD_LOGIC;
    cfg_slot_control_electromech_il_ctl_pulse : out STD_LOGIC;
    cfg_root_control_syserr_corr_err_en : out STD_LOGIC;
    cfg_root_control_syserr_non_fatal_err_en : out STD_LOGIC;
    cfg_root_control_syserr_fatal_err_en : out STD_LOGIC;
    cfg_root_control_pme_int_en : out STD_LOGIC;
    cfg_aer_rooterr_corr_err_reporting_en : out STD_LOGIC;
    cfg_aer_rooterr_non_fatal_err_reporting_en : out STD_LOGIC;
    cfg_aer_rooterr_fatal_err_reporting_en : out STD_LOGIC;
    cfg_aer_rooterr_corr_err_received : out STD_LOGIC;
    cfg_aer_rooterr_non_fatal_err_received : out STD_LOGIC;
    cfg_aer_rooterr_fatal_err_received : out STD_LOGIC;
    pl_directed_link_change : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_directed_link_width : in STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_directed_link_speed : in STD_LOGIC;
    pl_directed_link_auton : in STD_LOGIC;
    pl_upstream_prefer_deemph : in STD_LOGIC;
    pl_sel_lnk_rate : out STD_LOGIC;
    pl_sel_lnk_width : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_ltssm_state : out STD_LOGIC_VECTOR ( 5 downto 0 );
    pl_lane_reversal_mode : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_phy_lnk_up : out STD_LOGIC;
    pl_tx_pm_state : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pl_rx_pm_state : out STD_LOGIC_VECTOR ( 1 downto 0 );
    pl_link_upcfg_cap : out STD_LOGIC;
    pl_link_gen2_cap : out STD_LOGIC;
    pl_link_partner_gen2_supported : out STD_LOGIC;
    pl_initial_link_width : out STD_LOGIC_VECTOR ( 2 downto 0 );
    pl_directed_change_done : out STD_LOGIC;
    pl_received_hot_rst : out STD_LOGIC;
    pl_transmit_hot_rst : in STD_LOGIC;
    pl_downstream_deemph_source : in STD_LOGIC;
    cfg_err_aer_headerlog : in STD_LOGIC_VECTOR ( 127 downto 0 );
    cfg_aer_interrupt_msgnum : in STD_LOGIC_VECTOR ( 4 downto 0 );
    cfg_err_aer_headerlog_set : out STD_LOGIC;
    cfg_aer_ecrc_check_en : out STD_LOGIC;
    cfg_aer_ecrc_gen_en : out STD_LOGIC;
    cfg_vc_tcvc_map : out STD_LOGIC_VECTOR ( 6 downto 0 );
    sys_clk : in STD_LOGIC;
    sys_rst_n : in STD_LOGIC
  );
  attribute NotValidForBitStream : boolean;
  attribute NotValidForBitStream of spec7_pcie_7x_0 : entity is true;
  attribute CHECK_LICENSE_TYPE : string;
  attribute CHECK_LICENSE_TYPE of spec7_pcie_7x_0 : entity is "spec7_pcie_7x_0,spec7_pcie_7x_0_pcie2_top,{}";
  attribute downgradeipidentifiedwarnings : string;
  attribute downgradeipidentifiedwarnings of spec7_pcie_7x_0 : entity is "yes";
  attribute x_core_info : string;
  attribute x_core_info of spec7_pcie_7x_0 : entity is "spec7_pcie_7x_0_pcie2_top,Vivado 2019.2";
end spec7_pcie_7x_0;

architecture STRUCTURE of spec7_pcie_7x_0 is
  signal NLW_U0_cfg_msg_received_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_received_assert_int_a_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_received_assert_int_b_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_received_assert_int_c_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_received_assert_int_d_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_received_deassert_int_a_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_received_deassert_int_b_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_received_deassert_int_c_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_received_deassert_int_d_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_received_err_cor_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_received_err_fatal_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_received_err_non_fatal_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_received_pm_as_nak_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_received_pm_pme_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_received_pme_to_ack_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_received_setslotpowerlimit_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_ext_ch_gt_drpclk_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_int_dclk_out_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_int_mmcm_lock_out_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_int_oobclk_out_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_int_pclk_out_slave_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_int_pipe_rxusrclk_out_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_int_userclk1_out_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_int_userclk2_out_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_pcie_drp_rdy_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_pipe_gen3_out_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_pipe_qrst_idle_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_pipe_rate_idle_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_pipe_rst_idle_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_pipe_txoutclk_out_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_qpll_drp_clk_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_qpll_drp_gen3_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_qpll_drp_ovrd_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_qpll_drp_rst_n_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_qpll_drp_start_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_qpll_qplld_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_startup_cfgclk_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_startup_cfgmclk_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_startup_eos_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_startup_preq_UNCONNECTED : STD_LOGIC;
  signal NLW_U0_cfg_msg_data_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_U0_common_commands_out_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal NLW_U0_ext_ch_gt_drpdo_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_ext_ch_gt_drprdy_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_gt_ch_drp_rdy_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_icap_o_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_int_qplllock_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_int_qplloutclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_int_qplloutrefclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_int_rxoutclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_pcie_drp_do_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_U0_pipe_cpll_lock_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_pipe_debug_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
  signal NLW_U0_pipe_debug_0_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_pipe_debug_1_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_pipe_debug_2_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_pipe_debug_3_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_pipe_debug_4_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_pipe_debug_5_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_pipe_debug_6_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_pipe_debug_7_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_pipe_debug_8_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_pipe_debug_9_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_pipe_dmonitorout_UNCONNECTED : STD_LOGIC_VECTOR ( 29 downto 0 );
  signal NLW_U0_pipe_drp_fsm_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal NLW_U0_pipe_eyescandataerror_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_pipe_pclk_sel_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_pipe_qpll_lock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
  signal NLW_U0_pipe_qrst_fsm_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal NLW_U0_pipe_rate_fsm_UNCONNECTED : STD_LOGIC_VECTOR ( 9 downto 0 );
  signal NLW_U0_pipe_rst_fsm_UNCONNECTED : STD_LOGIC_VECTOR ( 4 downto 0 );
  signal NLW_U0_pipe_rxbufstatus_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_U0_pipe_rxcommadet_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_pipe_rxdisperr_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_U0_pipe_rxdlysresetdone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_pipe_rxnotintable_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
  signal NLW_U0_pipe_rxoutclk_out_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_pipe_rxphaligndone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_pipe_rxpmaresetdone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_pipe_rxprbserr_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_pipe_rxstatus_UNCONNECTED : STD_LOGIC_VECTOR ( 5 downto 0 );
  signal NLW_U0_pipe_rxsyncdone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_pipe_sync_fsm_rx_UNCONNECTED : STD_LOGIC_VECTOR ( 13 downto 0 );
  signal NLW_U0_pipe_sync_fsm_tx_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
  signal NLW_U0_pipe_tx_0_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 24 downto 0 );
  signal NLW_U0_pipe_tx_1_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 24 downto 0 );
  signal NLW_U0_pipe_tx_2_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 24 downto 0 );
  signal NLW_U0_pipe_tx_3_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 24 downto 0 );
  signal NLW_U0_pipe_tx_4_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 24 downto 0 );
  signal NLW_U0_pipe_tx_5_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 24 downto 0 );
  signal NLW_U0_pipe_tx_6_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 24 downto 0 );
  signal NLW_U0_pipe_tx_7_sigs_UNCONNECTED : STD_LOGIC_VECTOR ( 24 downto 0 );
  signal NLW_U0_pipe_txdlysresetdone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_pipe_txphaligndone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_pipe_txphinitdone_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  signal NLW_U0_qpll_qpllreset_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
  attribute CFG_CTL_IF : string;
  attribute CFG_CTL_IF of U0 : label is "TRUE";
  attribute CFG_FC_IF : string;
  attribute CFG_FC_IF of U0 : label is "TRUE";
  attribute CFG_MGMT_IF : string;
  attribute CFG_MGMT_IF of U0 : label is "TRUE";
  attribute CFG_STATUS_IF : string;
  attribute CFG_STATUS_IF of U0 : label is "TRUE";
  attribute CLASS_CODE : string;
  attribute CLASS_CODE of U0 : label is "058000";
  attribute C_DATA_WIDTH : integer;
  attribute C_DATA_WIDTH of U0 : label is 64;
  attribute ENABLE_JTAG_DBG : string;
  attribute ENABLE_JTAG_DBG of U0 : label is "FALSE";
  attribute ERR_REPORTING_IF : string;
  attribute ERR_REPORTING_IF of U0 : label is "TRUE";
  attribute EXT_CH_GT_DRP : string;
  attribute EXT_CH_GT_DRP of U0 : label is "FALSE";
  attribute EXT_PIPE_INTERFACE : string;
  attribute EXT_PIPE_INTERFACE of U0 : label is "FALSE";
  attribute EXT_STARTUP_PRIMITIVE : string;
  attribute EXT_STARTUP_PRIMITIVE of U0 : label is "FALSE";
  attribute KEEP_WIDTH : integer;
  attribute KEEP_WIDTH of U0 : label is 8;
  attribute LINK_CAP_MAX_LINK_WIDTH : integer;
  attribute LINK_CAP_MAX_LINK_WIDTH of U0 : label is 2;
  attribute PCIE_ASYNC_EN : string;
  attribute PCIE_ASYNC_EN of U0 : label is "FALSE";
  attribute PCIE_EXT_CLK : string;
  attribute PCIE_EXT_CLK of U0 : label is "FALSE";
  attribute PCIE_EXT_GT_COMMON : string;
  attribute PCIE_EXT_GT_COMMON of U0 : label is "FALSE";
  attribute PIPE_SIM : string;
  attribute PIPE_SIM of U0 : label is "FALSE";
  attribute PL_INTERFACE : string;
  attribute PL_INTERFACE of U0 : label is "TRUE";
  attribute RCV_MSG_IF : string;
  attribute RCV_MSG_IF of U0 : label is "FALSE";
  attribute SHARED_LOGIC_IN_CORE : string;
  attribute SHARED_LOGIC_IN_CORE of U0 : label is "FALSE";
  attribute TRANSCEIVER_CTRL_STATUS_PORTS : string;
  attribute TRANSCEIVER_CTRL_STATUS_PORTS of U0 : label is "FALSE";
  attribute bar_0 : string;
  attribute bar_0 of U0 : label is "FFFF0000";
  attribute bar_1 : string;
  attribute bar_1 of U0 : label is "00000000";
  attribute bar_2 : string;
  attribute bar_2 of U0 : label is "00000000";
  attribute bar_3 : string;
  attribute bar_3 of U0 : label is "00000000";
  attribute bar_4 : string;
  attribute bar_4 of U0 : label is "00000000";
  attribute bar_5 : string;
  attribute bar_5 of U0 : label is "00000000";
  attribute bram_lat : string;
  attribute bram_lat of U0 : label is "0";
  attribute c_aer_base_ptr : string;
  attribute c_aer_base_ptr of U0 : label is "000";
  attribute c_aer_cap_ecrc_check_capable : string;
  attribute c_aer_cap_ecrc_check_capable of U0 : label is "FALSE";
  attribute c_aer_cap_ecrc_gen_capable : string;
  attribute c_aer_cap_ecrc_gen_capable of U0 : label is "FALSE";
  attribute c_aer_cap_multiheader : string;
  attribute c_aer_cap_multiheader of U0 : label is "FALSE";
  attribute c_aer_cap_nextptr : string;
  attribute c_aer_cap_nextptr of U0 : label is "000";
  attribute c_aer_cap_on : string;
  attribute c_aer_cap_on of U0 : label is "FALSE";
  attribute c_aer_cap_optional_err_support : string;
  attribute c_aer_cap_optional_err_support of U0 : label is "000000";
  attribute c_aer_cap_permit_rooterr_update : string;
  attribute c_aer_cap_permit_rooterr_update of U0 : label is "FALSE";
  attribute c_buf_opt_bma : string;
  attribute c_buf_opt_bma of U0 : label is "TRUE";
  attribute c_component_name : string;
  attribute c_component_name of U0 : label is "spec7_pcie_7x_0";
  attribute c_cpl_inf : string;
  attribute c_cpl_inf of U0 : label is "TRUE";
  attribute c_cpl_infinite : string;
  attribute c_cpl_infinite of U0 : label is "TRUE";
  attribute c_cpl_timeout_disable_sup : string;
  attribute c_cpl_timeout_disable_sup of U0 : label is "FALSE";
  attribute c_cpl_timeout_range : string;
  attribute c_cpl_timeout_range of U0 : label is "0010";
  attribute c_cpl_timeout_ranges_sup : string;
  attribute c_cpl_timeout_ranges_sup of U0 : label is "2";
  attribute c_d1_support : string;
  attribute c_d1_support of U0 : label is "FALSE";
  attribute c_d2_support : string;
  attribute c_d2_support of U0 : label is "FALSE";
  attribute c_de_emph : string;
  attribute c_de_emph of U0 : label is "FALSE";
  attribute c_dev_cap2_ari_forwarding_supported : string;
  attribute c_dev_cap2_ari_forwarding_supported of U0 : label is "FALSE";
  attribute c_dev_cap2_atomicop32_completer_supported : string;
  attribute c_dev_cap2_atomicop32_completer_supported of U0 : label is "FALSE";
  attribute c_dev_cap2_atomicop64_completer_supported : string;
  attribute c_dev_cap2_atomicop64_completer_supported of U0 : label is "FALSE";
  attribute c_dev_cap2_atomicop_routing_supported : string;
  attribute c_dev_cap2_atomicop_routing_supported of U0 : label is "FALSE";
  attribute c_dev_cap2_cas128_completer_supported : string;
  attribute c_dev_cap2_cas128_completer_supported of U0 : label is "FALSE";
  attribute c_dev_cap2_tph_completer_supported : string;
  attribute c_dev_cap2_tph_completer_supported of U0 : label is "00";
  attribute c_dev_control_ext_tag_default : string;
  attribute c_dev_control_ext_tag_default of U0 : label is "FALSE";
  attribute c_dev_port_type : string;
  attribute c_dev_port_type of U0 : label is "0";
  attribute c_dis_lane_reverse : string;
  attribute c_dis_lane_reverse of U0 : label is "TRUE";
  attribute c_disable_rx_poisoned_resp : string;
  attribute c_disable_rx_poisoned_resp of U0 : label is "FALSE";
  attribute c_disable_scrambling : string;
  attribute c_disable_scrambling of U0 : label is "FALSE";
  attribute c_disable_tx_aspm_l0s : string;
  attribute c_disable_tx_aspm_l0s of U0 : label is "FALSE";
  attribute c_dll_lnk_actv_cap : string;
  attribute c_dll_lnk_actv_cap of U0 : label is "FALSE";
  attribute c_dsi_bool : string;
  attribute c_dsi_bool of U0 : label is "FALSE";
  attribute c_dsn_base_ptr : string;
  attribute c_dsn_base_ptr of U0 : label is "100";
  attribute c_dsn_cap_enabled : string;
  attribute c_dsn_cap_enabled of U0 : label is "TRUE";
  attribute c_dsn_next_ptr : string;
  attribute c_dsn_next_ptr of U0 : label is "000";
  attribute c_enable_msg_route : string;
  attribute c_enable_msg_route of U0 : label is "00000000000";
  attribute c_ep_l0s_accpt_lat : string;
  attribute c_ep_l0s_accpt_lat of U0 : label is "0";
  attribute c_ep_l1_accpt_lat : string;
  attribute c_ep_l1_accpt_lat of U0 : label is "7";
  attribute c_ext_pci_cfg_space_addr : string;
  attribute c_ext_pci_cfg_space_addr of U0 : label is "3FF";
  attribute c_external_clocking : string;
  attribute c_external_clocking of U0 : label is "TRUE";
  attribute c_fc_cpld : string;
  attribute c_fc_cpld of U0 : label is "461";
  attribute c_fc_cplh : string;
  attribute c_fc_cplh of U0 : label is "36";
  attribute c_fc_npd : string;
  attribute c_fc_npd of U0 : label is "24";
  attribute c_fc_nph : string;
  attribute c_fc_nph of U0 : label is "12";
  attribute c_fc_pd : string;
  attribute c_fc_pd of U0 : label is "437";
  attribute c_fc_ph : string;
  attribute c_fc_ph of U0 : label is "32";
  attribute c_gen1 : string;
  attribute c_gen1 of U0 : label is "FALSE";
  attribute c_header_type : string;
  attribute c_header_type of U0 : label is "00";
  attribute c_hw_auton_spd_disable : string;
  attribute c_hw_auton_spd_disable of U0 : label is "FALSE";
  attribute c_int_width : integer;
  attribute c_int_width of U0 : label is 64;
  attribute c_last_cfg_dw : string;
  attribute c_last_cfg_dw of U0 : label is "10C";
  attribute c_link_cap_aspm_optionality : string;
  attribute c_link_cap_aspm_optionality of U0 : label is "FALSE";
  attribute c_ll_ack_timeout : string;
  attribute c_ll_ack_timeout of U0 : label is "0000";
  attribute c_ll_ack_timeout_enable : string;
  attribute c_ll_ack_timeout_enable of U0 : label is "FALSE";
  attribute c_ll_ack_timeout_function : string;
  attribute c_ll_ack_timeout_function of U0 : label is "0";
  attribute c_ll_replay_timeout : string;
  attribute c_ll_replay_timeout of U0 : label is "0000";
  attribute c_ll_replay_timeout_enable : string;
  attribute c_ll_replay_timeout_enable of U0 : label is "FALSE";
  attribute c_ll_replay_timeout_func : string;
  attribute c_ll_replay_timeout_func of U0 : label is "1";
  attribute c_lnk_bndwdt_notif : string;
  attribute c_lnk_bndwdt_notif of U0 : label is "FALSE";
  attribute c_msi : string;
  attribute c_msi of U0 : label is "0";
  attribute c_msi_64b_addr : string;
  attribute c_msi_64b_addr of U0 : label is "TRUE";
  attribute c_msi_cap_on : string;
  attribute c_msi_cap_on of U0 : label is "TRUE";
  attribute c_msi_mult_msg_extn : string;
  attribute c_msi_mult_msg_extn of U0 : label is "0";
  attribute c_msi_per_vctr_mask_cap : string;
  attribute c_msi_per_vctr_mask_cap of U0 : label is "FALSE";
  attribute c_msix_cap_on : string;
  attribute c_msix_cap_on of U0 : label is "FALSE";
  attribute c_msix_next_ptr : string;
  attribute c_msix_next_ptr of U0 : label is "00";
  attribute c_msix_pba_bir : string;
  attribute c_msix_pba_bir of U0 : label is "0";
  attribute c_msix_pba_offset : string;
  attribute c_msix_pba_offset of U0 : label is "0";
  attribute c_msix_table_bir : string;
  attribute c_msix_table_bir of U0 : label is "0";
  attribute c_msix_table_offset : string;
  attribute c_msix_table_offset of U0 : label is "0";
  attribute c_msix_table_size : string;
  attribute c_msix_table_size of U0 : label is "000";
  attribute c_pci_cfg_space_addr : string;
  attribute c_pci_cfg_space_addr of U0 : label is "3F";
  attribute c_pcie_blk_locn : string;
  attribute c_pcie_blk_locn of U0 : label is "0";
  attribute c_pcie_cap_next_ptr : string;
  attribute c_pcie_cap_next_ptr of U0 : label is "00";
  attribute c_pcie_cap_slot_implemented : string;
  attribute c_pcie_cap_slot_implemented of U0 : label is "FALSE";
  attribute c_pcie_dbg_ports : string;
  attribute c_pcie_dbg_ports of U0 : label is "FALSE";
  attribute c_pcie_fast_config : integer;
  attribute c_pcie_fast_config of U0 : label is 0;
  attribute c_perf_level_high : string;
  attribute c_perf_level_high of U0 : label is "TRUE";
  attribute c_phantom_functions : string;
  attribute c_phantom_functions of U0 : label is "0";
  attribute c_pm_cap_next_ptr : string;
  attribute c_pm_cap_next_ptr of U0 : label is "48";
  attribute c_pme_support : string;
  attribute c_pme_support of U0 : label is "0F";
  attribute c_rbar_base_ptr : string;
  attribute c_rbar_base_ptr of U0 : label is "000";
  attribute c_rbar_cap_control_encodedbar0 : string;
  attribute c_rbar_cap_control_encodedbar0 of U0 : label is "00";
  attribute c_rbar_cap_control_encodedbar1 : string;
  attribute c_rbar_cap_control_encodedbar1 of U0 : label is "00";
  attribute c_rbar_cap_control_encodedbar2 : string;
  attribute c_rbar_cap_control_encodedbar2 of U0 : label is "00";
  attribute c_rbar_cap_control_encodedbar3 : string;
  attribute c_rbar_cap_control_encodedbar3 of U0 : label is "00";
  attribute c_rbar_cap_control_encodedbar4 : string;
  attribute c_rbar_cap_control_encodedbar4 of U0 : label is "00";
  attribute c_rbar_cap_control_encodedbar5 : string;
  attribute c_rbar_cap_control_encodedbar5 of U0 : label is "00";
  attribute c_rbar_cap_index0 : string;
  attribute c_rbar_cap_index0 of U0 : label is "0";
  attribute c_rbar_cap_index1 : string;
  attribute c_rbar_cap_index1 of U0 : label is "0";
  attribute c_rbar_cap_index2 : string;
  attribute c_rbar_cap_index2 of U0 : label is "0";
  attribute c_rbar_cap_index3 : string;
  attribute c_rbar_cap_index3 of U0 : label is "0";
  attribute c_rbar_cap_index4 : string;
  attribute c_rbar_cap_index4 of U0 : label is "0";
  attribute c_rbar_cap_index5 : string;
  attribute c_rbar_cap_index5 of U0 : label is "0";
  attribute c_rbar_cap_nextptr : string;
  attribute c_rbar_cap_nextptr of U0 : label is "000";
  attribute c_rbar_cap_on : string;
  attribute c_rbar_cap_on of U0 : label is "FALSE";
  attribute c_rbar_cap_sup0 : string;
  attribute c_rbar_cap_sup0 of U0 : label is "00001";
  attribute c_rbar_cap_sup1 : string;
  attribute c_rbar_cap_sup1 of U0 : label is "00001";
  attribute c_rbar_cap_sup2 : string;
  attribute c_rbar_cap_sup2 of U0 : label is "00001";
  attribute c_rbar_cap_sup3 : string;
  attribute c_rbar_cap_sup3 of U0 : label is "00001";
  attribute c_rbar_cap_sup4 : string;
  attribute c_rbar_cap_sup4 of U0 : label is "00001";
  attribute c_rbar_cap_sup5 : string;
  attribute c_rbar_cap_sup5 of U0 : label is "00001";
  attribute c_rbar_num : string;
  attribute c_rbar_num of U0 : label is "0";
  attribute c_rcb : string;
  attribute c_rcb of U0 : label is "0";
  attribute c_recrc_check : string;
  attribute c_recrc_check of U0 : label is "0";
  attribute c_recrc_check_trim : string;
  attribute c_recrc_check_trim of U0 : label is "FALSE";
  attribute c_rev_gt_order : string;
  attribute c_rev_gt_order of U0 : label is "FALSE";
  attribute c_root_cap_crs : string;
  attribute c_root_cap_crs of U0 : label is "FALSE";
  attribute c_rx_raddr_lat : string;
  attribute c_rx_raddr_lat of U0 : label is "0";
  attribute c_rx_ram_limit : string;
  attribute c_rx_ram_limit of U0 : label is "7FF";
  attribute c_rx_rdata_lat : string;
  attribute c_rx_rdata_lat of U0 : label is "2";
  attribute c_rx_write_lat : string;
  attribute c_rx_write_lat of U0 : label is "0";
  attribute c_silicon_rev : string;
  attribute c_silicon_rev of U0 : label is "2";
  attribute c_slot_cap_attn_butn : string;
  attribute c_slot_cap_attn_butn of U0 : label is "FALSE";
  attribute c_slot_cap_attn_ind : string;
  attribute c_slot_cap_attn_ind of U0 : label is "FALSE";
  attribute c_slot_cap_elec_interlock : string;
  attribute c_slot_cap_elec_interlock of U0 : label is "FALSE";
  attribute c_slot_cap_hotplug_cap : string;
  attribute c_slot_cap_hotplug_cap of U0 : label is "FALSE";
  attribute c_slot_cap_hotplug_surprise : string;
  attribute c_slot_cap_hotplug_surprise of U0 : label is "FALSE";
  attribute c_slot_cap_mrl : string;
  attribute c_slot_cap_mrl of U0 : label is "FALSE";
  attribute c_slot_cap_no_cmd_comp_sup : string;
  attribute c_slot_cap_no_cmd_comp_sup of U0 : label is "FALSE";
  attribute c_slot_cap_physical_slot_num : string;
  attribute c_slot_cap_physical_slot_num of U0 : label is "0";
  attribute c_slot_cap_pwr_ctrl : string;
  attribute c_slot_cap_pwr_ctrl of U0 : label is "FALSE";
  attribute c_slot_cap_pwr_ind : string;
  attribute c_slot_cap_pwr_ind of U0 : label is "FALSE";
  attribute c_slot_cap_pwr_limit_scale : string;
  attribute c_slot_cap_pwr_limit_scale of U0 : label is "0";
  attribute c_slot_cap_pwr_limit_value : string;
  attribute c_slot_cap_pwr_limit_value of U0 : label is "0";
  attribute c_surprise_dn_err_cap : string;
  attribute c_surprise_dn_err_cap of U0 : label is "FALSE";
  attribute c_trgt_lnk_spd : string;
  attribute c_trgt_lnk_spd of U0 : label is "0";
  attribute c_trn_np_fc : string;
  attribute c_trn_np_fc of U0 : label is "TRUE";
  attribute c_tx_last_tlp : string;
  attribute c_tx_last_tlp of U0 : label is "29";
  attribute c_tx_raddr_lat : string;
  attribute c_tx_raddr_lat of U0 : label is "0";
  attribute c_tx_rdata_lat : string;
  attribute c_tx_rdata_lat of U0 : label is "2";
  attribute c_tx_write_lat : string;
  attribute c_tx_write_lat of U0 : label is "0";
  attribute c_upconfig_capable : string;
  attribute c_upconfig_capable of U0 : label is "TRUE";
  attribute c_upstream_facing : string;
  attribute c_upstream_facing of U0 : label is "TRUE";
  attribute c_ur_atomic : string;
  attribute c_ur_atomic of U0 : label is "FALSE";
  attribute c_ur_inv_req : string;
  attribute c_ur_inv_req of U0 : label is "TRUE";
  attribute c_ur_prs_response : string;
  attribute c_ur_prs_response of U0 : label is "TRUE";
  attribute c_vc_base_ptr : string;
  attribute c_vc_base_ptr of U0 : label is "000";
  attribute c_vc_cap_enabled : string;
  attribute c_vc_cap_enabled of U0 : label is "FALSE";
  attribute c_vc_cap_reject_snoop : string;
  attribute c_vc_cap_reject_snoop of U0 : label is "FALSE";
  attribute c_vc_next_ptr : string;
  attribute c_vc_next_ptr of U0 : label is "000";
  attribute c_vsec_base_ptr : string;
  attribute c_vsec_base_ptr of U0 : label is "000";
  attribute c_vsec_cap_enabled : string;
  attribute c_vsec_cap_enabled of U0 : label is "FALSE";
  attribute c_vsec_next_ptr : string;
  attribute c_vsec_next_ptr of U0 : label is "000";
  attribute c_xlnx_ref_board : string;
  attribute c_xlnx_ref_board of U0 : label is "NONE";
  attribute cap_ver : string;
  attribute cap_ver of U0 : label is "2";
  attribute cardbus_cis_ptr : string;
  attribute cardbus_cis_ptr of U0 : label is "00000000";
  attribute cmps : string;
  attribute cmps of U0 : label is "2";
  attribute con_scl_fctr_d0_state : string;
  attribute con_scl_fctr_d0_state of U0 : label is "0";
  attribute con_scl_fctr_d1_state : string;
  attribute con_scl_fctr_d1_state of U0 : label is "0";
  attribute con_scl_fctr_d2_state : string;
  attribute con_scl_fctr_d2_state of U0 : label is "0";
  attribute con_scl_fctr_d3_state : string;
  attribute con_scl_fctr_d3_state of U0 : label is "0";
  attribute cost_table : integer;
  attribute cost_table of U0 : label is 1;
  attribute d1_sup : string;
  attribute d1_sup of U0 : label is "0";
  attribute d2_sup : string;
  attribute d2_sup of U0 : label is "0";
  attribute dev_id : string;
  attribute dev_id of U0 : label is "7012";
  attribute dev_port_type : string;
  attribute dev_port_type of U0 : label is "0000";
  attribute dis_scl_fctr_d0_state : string;
  attribute dis_scl_fctr_d0_state of U0 : label is "0";
  attribute dis_scl_fctr_d1_state : string;
  attribute dis_scl_fctr_d1_state of U0 : label is "0";
  attribute dis_scl_fctr_d2_state : string;
  attribute dis_scl_fctr_d2_state of U0 : label is "0";
  attribute dis_scl_fctr_d3_state : string;
  attribute dis_scl_fctr_d3_state of U0 : label is "0";
  attribute downgradeipidentifiedwarnings of U0 : label is "yes";
  attribute dsi : string;
  attribute dsi of U0 : label is "0";
  attribute ep_l0s_accpt_lat : string;
  attribute ep_l0s_accpt_lat of U0 : label is "000";
  attribute ep_l1_accpt_lat : string;
  attribute ep_l1_accpt_lat of U0 : label is "111";
  attribute ext_tag_fld_sup : string;
  attribute ext_tag_fld_sup of U0 : label is "FALSE";
  attribute int_pin : string;
  attribute int_pin of U0 : label is "1";
  attribute intx : string;
  attribute intx of U0 : label is "TRUE";
  attribute max_lnk_spd : string;
  attribute max_lnk_spd of U0 : label is "1";
  attribute max_lnk_wdt : string;
  attribute max_lnk_wdt of U0 : label is "000010";
  attribute mps : string;
  attribute mps of U0 : label is "010";
  attribute no_soft_rst : string;
  attribute no_soft_rst of U0 : label is "TRUE";
  attribute pci_exp_int_freq : integer;
  attribute pci_exp_int_freq of U0 : label is 1;
  attribute pci_exp_ref_freq : string;
  attribute pci_exp_ref_freq of U0 : label is "0";
  attribute phantm_func_sup : string;
  attribute phantm_func_sup of U0 : label is "00";
  attribute pme_sup : string;
  attribute pme_sup of U0 : label is "0F";
  attribute pwr_con_d0_state : string;
  attribute pwr_con_d0_state of U0 : label is "00";
  attribute pwr_con_d1_state : string;
  attribute pwr_con_d1_state of U0 : label is "00";
  attribute pwr_con_d2_state : string;
  attribute pwr_con_d2_state of U0 : label is "00";
  attribute pwr_con_d3_state : string;
  attribute pwr_con_d3_state of U0 : label is "00";
  attribute pwr_dis_d0_state : string;
  attribute pwr_dis_d0_state of U0 : label is "00";
  attribute pwr_dis_d1_state : string;
  attribute pwr_dis_d1_state of U0 : label is "00";
  attribute pwr_dis_d2_state : string;
  attribute pwr_dis_d2_state of U0 : label is "00";
  attribute pwr_dis_d3_state : string;
  attribute pwr_dis_d3_state of U0 : label is "00";
  attribute rev_id : string;
  attribute rev_id of U0 : label is "00";
  attribute slot_clk : string;
  attribute slot_clk of U0 : label is "TRUE";
  attribute subsys_id : string;
  attribute subsys_id of U0 : label is "0007";
  attribute subsys_ven_id : string;
  attribute subsys_ven_id of U0 : label is "10EE";
  attribute ven_id : string;
  attribute ven_id of U0 : label is "10EE";
  attribute xrom_bar : string;
  attribute xrom_bar of U0 : label is "00000000";
  attribute x_interface_info : string;
  attribute x_interface_info of cfg_aer_ecrc_check_en : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err aer_ecrc_check_en";
  attribute x_interface_info of cfg_aer_ecrc_gen_en : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err aer_ecrc_gen_en";
  attribute x_interface_info of cfg_aer_rooterr_corr_err_received : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_corr_err_received";
  attribute x_interface_info of cfg_aer_rooterr_corr_err_reporting_en : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_corr_err_reporting_en";
  attribute x_interface_info of cfg_aer_rooterr_fatal_err_received : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_fatal_err_received";
  attribute x_interface_info of cfg_aer_rooterr_fatal_err_reporting_en : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_fatal_err_reporting_en";
  attribute x_interface_info of cfg_aer_rooterr_non_fatal_err_received : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_non_fatal_err_received";
  attribute x_interface_info of cfg_aer_rooterr_non_fatal_err_reporting_en : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status aer_rooterr_non_fatal_err_reporting_en";
  attribute x_interface_info of cfg_bridge_serr_en : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status bridge_serr_en";
  attribute x_interface_info of cfg_err_acs : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err acs";
  attribute x_interface_info of cfg_err_aer_headerlog_set : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err err_aer_headerlog_set";
  attribute x_interface_info of cfg_err_atomic_egress_blocked : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err atomic_egress_blocked";
  attribute x_interface_info of cfg_err_cor : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cor";
  attribute x_interface_info of cfg_err_cpl_abort : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_abort";
  attribute x_interface_info of cfg_err_cpl_rdy : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_rdy";
  attribute x_interface_info of cfg_err_cpl_timeout : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_timeout";
  attribute x_interface_info of cfg_err_cpl_unexpect : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err cpl_unexpect";
  attribute x_interface_info of cfg_err_ecrc : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err ecrc";
  attribute x_interface_info of cfg_err_internal_cor : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err internal_cor";
  attribute x_interface_info of cfg_err_internal_uncor : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err internal_uncor";
  attribute x_interface_info of cfg_err_locked : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err locked";
  attribute x_interface_info of cfg_err_malformed : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err malformed";
  attribute x_interface_info of cfg_err_mc_blocked : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err mc_blocked";
  attribute x_interface_info of cfg_err_norecovery : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err norecovery";
  attribute x_interface_info of cfg_err_poisoned : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err poisoned";
  attribute x_interface_info of cfg_err_posted : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err posted";
  attribute x_interface_info of cfg_err_ur : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err ur";
  attribute x_interface_info of cfg_interrupt : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt interrupt";
  attribute x_interface_info of cfg_interrupt_assert : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt assert";
  attribute x_interface_info of cfg_interrupt_msienable : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt msienable";
  attribute x_interface_info of cfg_interrupt_msixenable : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt msixenable";
  attribute x_interface_info of cfg_interrupt_msixfm : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt msixfm";
  attribute x_interface_info of cfg_interrupt_rdy : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt rdy";
  attribute x_interface_info of cfg_interrupt_stat : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt stat";
  attribute x_interface_info of cfg_mgmt_rd_en : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READ_EN";
  attribute x_interface_info of cfg_mgmt_rd_wr_done : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READ_WRITE_DONE";
  attribute x_interface_info of cfg_mgmt_wr_en : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt WRITE_EN";
  attribute x_interface_info of cfg_mgmt_wr_readonly : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READONLY";
  attribute x_interface_info of cfg_mgmt_wr_rw1c_as_rw : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt TYPE1_CFG_REG_ACCESS";
  attribute x_interface_info of cfg_pm_force_state_en : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_force_state_en";
  attribute x_interface_info of cfg_pm_halt_aspm_l0s : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_halt_aspm_l0s";
  attribute x_interface_info of cfg_pm_halt_aspm_l1 : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_halt_aspm_l1";
  attribute x_interface_info of cfg_pm_send_pme_to : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_send_pme_to";
  attribute x_interface_info of cfg_pm_wake : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_wake";
  attribute x_interface_info of cfg_pmcsr_pme_en : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pmcsr_pme_en";
  attribute x_interface_info of cfg_pmcsr_pme_status : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pmcsr_pme_status";
  attribute x_interface_info of cfg_received_func_lvl_rst : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status received_func_lvl_rst";
  attribute x_interface_info of cfg_root_control_pme_int_en : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_pme_int_en";
  attribute x_interface_info of cfg_root_control_syserr_corr_err_en : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_syserr_corr_err_en";
  attribute x_interface_info of cfg_root_control_syserr_fatal_err_en : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_syserr_fatal_err_en";
  attribute x_interface_info of cfg_root_control_syserr_non_fatal_err_en : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status root_control_syserr_non_fatal_err_en";
  attribute x_interface_info of cfg_slot_control_electromech_il_ctl_pulse : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status slot_control_electromech_il_ctl_pulse";
  attribute x_interface_info of cfg_to_turnoff : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status turnoff";
  attribute x_interface_info of cfg_trn_pending : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control trn_pending";
  attribute x_interface_info of cfg_turnoff_ok : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control turnoff_ok";
  attribute x_interface_info of m_axis_rx_tlast : signal is "xilinx.com:interface:axis:1.0 m_axis_rx TLAST";
  attribute x_interface_info of m_axis_rx_tready : signal is "xilinx.com:interface:axis:1.0 m_axis_rx TREADY";
  attribute x_interface_info of m_axis_rx_tvalid : signal is "xilinx.com:interface:axis:1.0 m_axis_rx TVALID";
  attribute x_interface_info of pl_directed_change_done : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_change_done";
  attribute x_interface_info of pl_directed_link_auton : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_auton";
  attribute x_interface_info of pl_directed_link_speed : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_speed";
  attribute x_interface_info of pl_downstream_deemph_source : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl downstream_deemph_source";
  attribute x_interface_info of pl_link_gen2_cap : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl link_gen2_cap";
  attribute x_interface_info of pl_link_partner_gen2_supported : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl link_partner_gen2_supported";
  attribute x_interface_info of pl_link_upcfg_cap : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl link_upcfg_cap";
  attribute x_interface_info of pl_phy_lnk_up : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl phy_lnk_up";
  attribute x_interface_info of pl_received_hot_rst : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl received_hot_rst";
  attribute x_interface_info of pl_sel_lnk_rate : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl sel_lnk_rate";
  attribute x_interface_info of pl_transmit_hot_rst : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl transmit_hot_rst";
  attribute x_interface_info of pl_upstream_prefer_deemph : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl upstream_prefer_deemph";
  attribute x_interface_info of rx_np_ok : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control rx_np_ok";
  attribute x_interface_info of rx_np_req : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control rx_np_req";
  attribute x_interface_info of s_axis_tx_tlast : signal is "xilinx.com:interface:axis:1.0 s_axis_tx TLAST";
  attribute x_interface_info of s_axis_tx_tready : signal is "xilinx.com:interface:axis:1.0 s_axis_tx TREADY";
  attribute x_interface_parameter : string;
  attribute x_interface_parameter of s_axis_tx_tready : signal is "XIL_INTERFACENAME s_axis_tx, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 4, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 62500000, PHASE 0.000, CLK_DOMAIN spec7_pcie_7x_0_user_clk_out, LAYERED_METADATA undef, INSERT_VIP 0";
  attribute x_interface_info of s_axis_tx_tvalid : signal is "xilinx.com:interface:axis:1.0 s_axis_tx TVALID";
  attribute x_interface_info of sys_clk : signal is "xilinx.com:signal:clock:1.0 CLK.sys_clk CLK";
  attribute x_interface_parameter of sys_clk : signal is "XIL_INTERFACENAME CLK.sys_clk, FREQ_HZ 100000000, PHASE 0.000, CLK_DOMAIN spec7_pci_clk_n, INSERT_VIP 0";
  attribute x_interface_info of sys_rst_n : signal is "xilinx.com:signal:reset:1.0 RST.sys_rst_n RST";
  attribute x_interface_parameter of sys_rst_n : signal is "XIL_INTERFACENAME RST.sys_rst_n, POLARITY ACTIVE_LOW, INSERT_VIP 0";
  attribute x_interface_info of tx_cfg_gnt : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control tx_cfg_gnt";
  attribute x_interface_info of tx_cfg_req : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status tx_cfg_req";
  attribute x_interface_info of tx_err_drop : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status tx_err_drop";
  attribute x_interface_info of user_clk_out : signal is "xilinx.com:signal:clock:1.0 CLK.user_clk_out CLK";
  attribute x_interface_parameter of user_clk_out : signal is "XIL_INTERFACENAME CLK.user_clk_out, ASSOCIATED_BUSIF m_axis_rx:s_axis_tx, FREQ_HZ 62500000, ASSOCIATED_RESET user_reset_out, PHASE 0.000, CLK_DOMAIN spec7_pcie_7x_0_user_clk_out, INSERT_VIP 0";
  attribute x_interface_info of user_reset_out : signal is "xilinx.com:signal:reset:1.0 RST.user_reset_out RST";
  attribute x_interface_parameter of user_reset_out : signal is "XIL_INTERFACENAME RST.user_reset_out, POLARITY ACTIVE_HIGH, INSERT_VIP 0";
  attribute x_interface_info of cfg_aer_interrupt_msgnum : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err aer_interrupt_msgnum";
  attribute x_interface_info of cfg_bus_number : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status bus_number";
  attribute x_interface_info of cfg_command : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status command";
  attribute x_interface_info of cfg_dcommand : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status dcommand";
  attribute x_interface_info of cfg_dcommand2 : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status dcommand2";
  attribute x_interface_info of cfg_device_number : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status device_number";
  attribute x_interface_info of cfg_ds_bus_number : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control ds_bus_number";
  attribute x_interface_info of cfg_ds_device_number : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control ds_device_number";
  attribute x_interface_info of cfg_ds_function_number : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control ds_function_number";
  attribute x_interface_info of cfg_dsn : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control dsn";
  attribute x_interface_info of cfg_dstatus : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status dstatus";
  attribute x_interface_info of cfg_err_aer_headerlog : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err err_aer_headerlog";
  attribute x_interface_info of cfg_err_tlp_cpl_header : signal is "xilinx.com:interface:pcie2_cfg_err:1.0 pcie2_cfg_err tlp_cpl_header";
  attribute x_interface_info of cfg_function_number : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status function_number";
  attribute x_interface_info of cfg_interrupt_di : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt write_data";
  attribute x_interface_info of cfg_interrupt_do : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt read_data";
  attribute x_interface_info of cfg_interrupt_mmenable : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt mmenable";
  attribute x_interface_info of cfg_lcommand : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status lcommand";
  attribute x_interface_info of cfg_lstatus : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status lstatus";
  attribute x_interface_info of cfg_mgmt_byte_en : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt BYTE_EN";
  attribute x_interface_info of cfg_mgmt_di : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt WRITE_DATA";
  attribute x_interface_info of cfg_mgmt_do : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt READ_DATA";
  attribute x_interface_info of cfg_mgmt_dwaddr : signal is "xilinx.com:interface:pcie_cfg_mgmt:1.0 pcie_cfg_mgmt ADDR";
  attribute x_interface_info of cfg_pcie_link_state : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pcie_link_state";
  attribute x_interface_info of cfg_pciecap_interrupt_msgnum : signal is "xilinx.com:interface:pcie2_cfg_interrupt:1.0 pcie2_cfg_interrupt pciecap_interrupt_msgnum";
  attribute x_interface_info of cfg_pm_force_state : signal is "xilinx.com:interface:pcie2_cfg_control:1.0 pcie2_cfg_control pm_force_state";
  attribute x_interface_info of cfg_pmcsr_powerstate : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status pmcsr_powerstate";
  attribute x_interface_info of cfg_status : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status status";
  attribute x_interface_info of cfg_vc_tcvc_map : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status vc_tcvc_map";
  attribute x_interface_info of fc_cpld : signal is "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc CPLD";
  attribute x_interface_info of fc_cplh : signal is "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc CPLH";
  attribute x_interface_info of fc_npd : signal is "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc NPD";
  attribute x_interface_info of fc_nph : signal is "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc NPH";
  attribute x_interface_info of fc_pd : signal is "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc PD";
  attribute x_interface_info of fc_ph : signal is "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc PH";
  attribute x_interface_info of fc_sel : signal is "xilinx.com:interface:pcie_cfg_fc:1.0 pcie_cfg_fc SEL";
  attribute x_interface_info of m_axis_rx_tdata : signal is "xilinx.com:interface:axis:1.0 m_axis_rx TDATA";
  attribute x_interface_parameter of m_axis_rx_tdata : signal is "XIL_INTERFACENAME m_axis_rx, TDATA_NUM_BYTES 8, TDEST_WIDTH 0, TID_WIDTH 0, TUSER_WIDTH 22, HAS_TREADY 1, HAS_TSTRB 0, HAS_TKEEP 1, HAS_TLAST 1, FREQ_HZ 62500000, PHASE 0.000, CLK_DOMAIN spec7_pcie_7x_0_user_clk_out, LAYERED_METADATA undef, INSERT_VIP 0";
  attribute x_interface_info of m_axis_rx_tkeep : signal is "xilinx.com:interface:axis:1.0 m_axis_rx TKEEP";
  attribute x_interface_info of m_axis_rx_tuser : signal is "xilinx.com:interface:axis:1.0 m_axis_rx TUSER";
  attribute x_interface_info of pci_exp_rxn : signal is "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt rxn";
  attribute x_interface_info of pci_exp_rxp : signal is "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt rxp";
  attribute x_interface_info of pci_exp_txn : signal is "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt txn";
  attribute x_interface_info of pci_exp_txp : signal is "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_7x_mgt txp";
  attribute x_interface_info of pl_directed_link_change : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_change";
  attribute x_interface_info of pl_directed_link_width : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl directed_link_width";
  attribute x_interface_info of pl_initial_link_width : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl initial_link_width";
  attribute x_interface_info of pl_lane_reversal_mode : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl lane_reversal_mode";
  attribute x_interface_info of pl_ltssm_state : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl ltssm_state";
  attribute x_interface_info of pl_rx_pm_state : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl rx_pm_state";
  attribute x_interface_info of pl_sel_lnk_width : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl sel_lnk_width";
  attribute x_interface_info of pl_tx_pm_state : signal is "xilinx.com:interface:pcie2_pl:1.0 pcie2_pl tx_pm_state";
  attribute x_interface_info of s_axis_tx_tdata : signal is "xilinx.com:interface:axis:1.0 s_axis_tx TDATA";
  attribute x_interface_info of s_axis_tx_tkeep : signal is "xilinx.com:interface:axis:1.0 s_axis_tx TKEEP";
  attribute x_interface_info of s_axis_tx_tuser : signal is "xilinx.com:interface:axis:1.0 s_axis_tx TUSER";
  attribute x_interface_info of tx_buf_av : signal is "xilinx.com:interface:pcie2_cfg_status:1.0 pcie2_cfg_status tx_buf_av";
begin
U0: entity work.spec7_pcie_7x_0_spec7_pcie_7x_0_pcie2_top
     port map (
      cfg_aer_ecrc_check_en => cfg_aer_ecrc_check_en,
      cfg_aer_ecrc_gen_en => cfg_aer_ecrc_gen_en,
      cfg_aer_interrupt_msgnum(4 downto 0) => cfg_aer_interrupt_msgnum(4 downto 0),
      cfg_aer_rooterr_corr_err_received => cfg_aer_rooterr_corr_err_received,
      cfg_aer_rooterr_corr_err_reporting_en => cfg_aer_rooterr_corr_err_reporting_en,
      cfg_aer_rooterr_fatal_err_received => cfg_aer_rooterr_fatal_err_received,
      cfg_aer_rooterr_fatal_err_reporting_en => cfg_aer_rooterr_fatal_err_reporting_en,
      cfg_aer_rooterr_non_fatal_err_received => cfg_aer_rooterr_non_fatal_err_received,
      cfg_aer_rooterr_non_fatal_err_reporting_en => cfg_aer_rooterr_non_fatal_err_reporting_en,
      cfg_bridge_serr_en => cfg_bridge_serr_en,
      cfg_bus_number(7 downto 0) => cfg_bus_number(7 downto 0),
      cfg_command(15 downto 0) => cfg_command(15 downto 0),
      cfg_dcommand(15 downto 0) => cfg_dcommand(15 downto 0),
      cfg_dcommand2(15 downto 0) => cfg_dcommand2(15 downto 0),
      cfg_device_number(4 downto 0) => cfg_device_number(4 downto 0),
      cfg_ds_bus_number(7 downto 0) => cfg_ds_bus_number(7 downto 0),
      cfg_ds_device_number(4 downto 0) => cfg_ds_device_number(4 downto 0),
      cfg_ds_function_number(2 downto 0) => cfg_ds_function_number(2 downto 0),
      cfg_dsn(63 downto 0) => cfg_dsn(63 downto 0),
      cfg_dstatus(15 downto 0) => cfg_dstatus(15 downto 0),
      cfg_err_acs => cfg_err_acs,
      cfg_err_aer_headerlog(127 downto 0) => cfg_err_aer_headerlog(127 downto 0),
      cfg_err_aer_headerlog_set => cfg_err_aer_headerlog_set,
      cfg_err_atomic_egress_blocked => cfg_err_atomic_egress_blocked,
      cfg_err_cor => cfg_err_cor,
      cfg_err_cpl_abort => cfg_err_cpl_abort,
      cfg_err_cpl_rdy => cfg_err_cpl_rdy,
      cfg_err_cpl_timeout => cfg_err_cpl_timeout,
      cfg_err_cpl_unexpect => cfg_err_cpl_unexpect,
      cfg_err_ecrc => cfg_err_ecrc,
      cfg_err_internal_cor => cfg_err_internal_cor,
      cfg_err_internal_uncor => cfg_err_internal_uncor,
      cfg_err_locked => cfg_err_locked,
      cfg_err_malformed => cfg_err_malformed,
      cfg_err_mc_blocked => cfg_err_mc_blocked,
      cfg_err_norecovery => cfg_err_norecovery,
      cfg_err_poisoned => cfg_err_poisoned,
      cfg_err_posted => cfg_err_posted,
      cfg_err_tlp_cpl_header(47 downto 0) => cfg_err_tlp_cpl_header(47 downto 0),
      cfg_err_ur => cfg_err_ur,
      cfg_function_number(2 downto 0) => cfg_function_number(2 downto 0),
      cfg_interrupt => cfg_interrupt,
      cfg_interrupt_assert => cfg_interrupt_assert,
      cfg_interrupt_di(7 downto 0) => cfg_interrupt_di(7 downto 0),
      cfg_interrupt_do(7 downto 0) => cfg_interrupt_do(7 downto 0),
      cfg_interrupt_mmenable(2 downto 0) => cfg_interrupt_mmenable(2 downto 0),
      cfg_interrupt_msienable => cfg_interrupt_msienable,
      cfg_interrupt_msixenable => cfg_interrupt_msixenable,
      cfg_interrupt_msixfm => cfg_interrupt_msixfm,
      cfg_interrupt_rdy => cfg_interrupt_rdy,
      cfg_interrupt_stat => cfg_interrupt_stat,
      cfg_lcommand(15 downto 0) => cfg_lcommand(15 downto 0),
      cfg_lstatus(15 downto 0) => cfg_lstatus(15 downto 0),
      cfg_mgmt_byte_en(3 downto 0) => cfg_mgmt_byte_en(3 downto 0),
      cfg_mgmt_di(31 downto 0) => cfg_mgmt_di(31 downto 0),
      cfg_mgmt_do(31 downto 0) => cfg_mgmt_do(31 downto 0),
      cfg_mgmt_dwaddr(9 downto 0) => cfg_mgmt_dwaddr(9 downto 0),
      cfg_mgmt_rd_en => cfg_mgmt_rd_en,
      cfg_mgmt_rd_wr_done => cfg_mgmt_rd_wr_done,
      cfg_mgmt_wr_en => cfg_mgmt_wr_en,
      cfg_mgmt_wr_readonly => cfg_mgmt_wr_readonly,
      cfg_mgmt_wr_rw1c_as_rw => cfg_mgmt_wr_rw1c_as_rw,
      cfg_msg_data(15 downto 0) => NLW_U0_cfg_msg_data_UNCONNECTED(15 downto 0),
      cfg_msg_received => NLW_U0_cfg_msg_received_UNCONNECTED,
      cfg_msg_received_assert_int_a => NLW_U0_cfg_msg_received_assert_int_a_UNCONNECTED,
      cfg_msg_received_assert_int_b => NLW_U0_cfg_msg_received_assert_int_b_UNCONNECTED,
      cfg_msg_received_assert_int_c => NLW_U0_cfg_msg_received_assert_int_c_UNCONNECTED,
      cfg_msg_received_assert_int_d => NLW_U0_cfg_msg_received_assert_int_d_UNCONNECTED,
      cfg_msg_received_deassert_int_a => NLW_U0_cfg_msg_received_deassert_int_a_UNCONNECTED,
      cfg_msg_received_deassert_int_b => NLW_U0_cfg_msg_received_deassert_int_b_UNCONNECTED,
      cfg_msg_received_deassert_int_c => NLW_U0_cfg_msg_received_deassert_int_c_UNCONNECTED,
      cfg_msg_received_deassert_int_d => NLW_U0_cfg_msg_received_deassert_int_d_UNCONNECTED,
      cfg_msg_received_err_cor => NLW_U0_cfg_msg_received_err_cor_UNCONNECTED,
      cfg_msg_received_err_fatal => NLW_U0_cfg_msg_received_err_fatal_UNCONNECTED,
      cfg_msg_received_err_non_fatal => NLW_U0_cfg_msg_received_err_non_fatal_UNCONNECTED,
      cfg_msg_received_pm_as_nak => NLW_U0_cfg_msg_received_pm_as_nak_UNCONNECTED,
      cfg_msg_received_pm_pme => NLW_U0_cfg_msg_received_pm_pme_UNCONNECTED,
      cfg_msg_received_pme_to_ack => NLW_U0_cfg_msg_received_pme_to_ack_UNCONNECTED,
      cfg_msg_received_setslotpowerlimit => NLW_U0_cfg_msg_received_setslotpowerlimit_UNCONNECTED,
      cfg_pcie_link_state(2 downto 0) => cfg_pcie_link_state(2 downto 0),
      cfg_pciecap_interrupt_msgnum(4 downto 0) => cfg_pciecap_interrupt_msgnum(4 downto 0),
      cfg_pm_force_state(1 downto 0) => cfg_pm_force_state(1 downto 0),
      cfg_pm_force_state_en => cfg_pm_force_state_en,
      cfg_pm_halt_aspm_l0s => cfg_pm_halt_aspm_l0s,
      cfg_pm_halt_aspm_l1 => cfg_pm_halt_aspm_l1,
      cfg_pm_send_pme_to => cfg_pm_send_pme_to,
      cfg_pm_wake => cfg_pm_wake,
      cfg_pmcsr_pme_en => cfg_pmcsr_pme_en,
      cfg_pmcsr_pme_status => cfg_pmcsr_pme_status,
      cfg_pmcsr_powerstate(1 downto 0) => cfg_pmcsr_powerstate(1 downto 0),
      cfg_received_func_lvl_rst => cfg_received_func_lvl_rst,
      cfg_root_control_pme_int_en => cfg_root_control_pme_int_en,
      cfg_root_control_syserr_corr_err_en => cfg_root_control_syserr_corr_err_en,
      cfg_root_control_syserr_fatal_err_en => cfg_root_control_syserr_fatal_err_en,
      cfg_root_control_syserr_non_fatal_err_en => cfg_root_control_syserr_non_fatal_err_en,
      cfg_slot_control_electromech_il_ctl_pulse => cfg_slot_control_electromech_il_ctl_pulse,
      cfg_status(15 downto 0) => cfg_status(15 downto 0),
      cfg_to_turnoff => cfg_to_turnoff,
      cfg_trn_pending => cfg_trn_pending,
      cfg_turnoff_ok => cfg_turnoff_ok,
      cfg_vc_tcvc_map(6 downto 0) => cfg_vc_tcvc_map(6 downto 0),
      common_commands_in(11 downto 0) => B"000000000000",
      common_commands_out(11 downto 0) => NLW_U0_common_commands_out_UNCONNECTED(11 downto 0),
      ext_ch_gt_drpaddr(17 downto 0) => B"000000000000000000",
      ext_ch_gt_drpclk => NLW_U0_ext_ch_gt_drpclk_UNCONNECTED,
      ext_ch_gt_drpdi(31 downto 0) => B"00000000000000000000000000000000",
      ext_ch_gt_drpdo(31 downto 0) => NLW_U0_ext_ch_gt_drpdo_UNCONNECTED(31 downto 0),
      ext_ch_gt_drpen(1 downto 0) => B"00",
      ext_ch_gt_drprdy(1 downto 0) => NLW_U0_ext_ch_gt_drprdy_UNCONNECTED(1 downto 0),
      ext_ch_gt_drpwe(1 downto 0) => B"00",
      fc_cpld(11 downto 0) => fc_cpld(11 downto 0),
      fc_cplh(7 downto 0) => fc_cplh(7 downto 0),
      fc_npd(11 downto 0) => fc_npd(11 downto 0),
      fc_nph(7 downto 0) => fc_nph(7 downto 0),
      fc_pd(11 downto 0) => fc_pd(11 downto 0),
      fc_ph(7 downto 0) => fc_ph(7 downto 0),
      fc_sel(2 downto 0) => fc_sel(2 downto 0),
      gt_ch_drp_rdy(1 downto 0) => NLW_U0_gt_ch_drp_rdy_UNCONNECTED(1 downto 0),
      icap_clk => '0',
      icap_csib => '0',
      icap_i(31 downto 0) => B"00000000000000000000000000000000",
      icap_o(31 downto 0) => NLW_U0_icap_o_UNCONNECTED(31 downto 0),
      icap_rdwrb => '0',
      int_dclk_out => NLW_U0_int_dclk_out_UNCONNECTED,
      int_mmcm_lock_out => NLW_U0_int_mmcm_lock_out_UNCONNECTED,
      int_oobclk_out => NLW_U0_int_oobclk_out_UNCONNECTED,
      int_pclk_out_slave => NLW_U0_int_pclk_out_slave_UNCONNECTED,
      int_pclk_sel_slave(1 downto 0) => B"00",
      int_pipe_rxusrclk_out => NLW_U0_int_pipe_rxusrclk_out_UNCONNECTED,
      int_qplllock_out(1 downto 0) => NLW_U0_int_qplllock_out_UNCONNECTED(1 downto 0),
      int_qplloutclk_out(1 downto 0) => NLW_U0_int_qplloutclk_out_UNCONNECTED(1 downto 0),
      int_qplloutrefclk_out(1 downto 0) => NLW_U0_int_qplloutrefclk_out_UNCONNECTED(1 downto 0),
      int_rxoutclk_out(1 downto 0) => NLW_U0_int_rxoutclk_out_UNCONNECTED(1 downto 0),
      int_userclk1_out => NLW_U0_int_userclk1_out_UNCONNECTED,
      int_userclk2_out => NLW_U0_int_userclk2_out_UNCONNECTED,
      m_axis_rx_tdata(63 downto 0) => m_axis_rx_tdata(63 downto 0),
      m_axis_rx_tkeep(7 downto 0) => m_axis_rx_tkeep(7 downto 0),
      m_axis_rx_tlast => m_axis_rx_tlast,
      m_axis_rx_tready => m_axis_rx_tready,
      m_axis_rx_tuser(21 downto 0) => m_axis_rx_tuser(21 downto 0),
      m_axis_rx_tvalid => m_axis_rx_tvalid,
      pci_exp_rxn(1 downto 0) => pci_exp_rxn(1 downto 0),
      pci_exp_rxp(1 downto 0) => pci_exp_rxp(1 downto 0),
      pci_exp_txn(1 downto 0) => pci_exp_txn(1 downto 0),
      pci_exp_txp(1 downto 0) => pci_exp_txp(1 downto 0),
      pcie_drp_addr(8 downto 0) => B"000000000",
      pcie_drp_clk => '1',
      pcie_drp_di(15 downto 0) => B"0000000000000000",
      pcie_drp_do(15 downto 0) => NLW_U0_pcie_drp_do_UNCONNECTED(15 downto 0),
      pcie_drp_en => '0',
      pcie_drp_rdy => NLW_U0_pcie_drp_rdy_UNCONNECTED,
      pcie_drp_we => '0',
      pipe_cpll_lock(1 downto 0) => NLW_U0_pipe_cpll_lock_UNCONNECTED(1 downto 0),
      pipe_dclk_in => '0',
      pipe_debug(31 downto 0) => NLW_U0_pipe_debug_UNCONNECTED(31 downto 0),
      pipe_debug_0(1 downto 0) => NLW_U0_pipe_debug_0_UNCONNECTED(1 downto 0),
      pipe_debug_1(1 downto 0) => NLW_U0_pipe_debug_1_UNCONNECTED(1 downto 0),
      pipe_debug_2(1 downto 0) => NLW_U0_pipe_debug_2_UNCONNECTED(1 downto 0),
      pipe_debug_3(1 downto 0) => NLW_U0_pipe_debug_3_UNCONNECTED(1 downto 0),
      pipe_debug_4(1 downto 0) => NLW_U0_pipe_debug_4_UNCONNECTED(1 downto 0),
      pipe_debug_5(1 downto 0) => NLW_U0_pipe_debug_5_UNCONNECTED(1 downto 0),
      pipe_debug_6(1 downto 0) => NLW_U0_pipe_debug_6_UNCONNECTED(1 downto 0),
      pipe_debug_7(1 downto 0) => NLW_U0_pipe_debug_7_UNCONNECTED(1 downto 0),
      pipe_debug_8(1 downto 0) => NLW_U0_pipe_debug_8_UNCONNECTED(1 downto 0),
      pipe_debug_9(1 downto 0) => NLW_U0_pipe_debug_9_UNCONNECTED(1 downto 0),
      pipe_dmonitorout(29 downto 0) => NLW_U0_pipe_dmonitorout_UNCONNECTED(29 downto 0),
      pipe_drp_fsm(13 downto 0) => NLW_U0_pipe_drp_fsm_UNCONNECTED(13 downto 0),
      pipe_eyescandataerror(1 downto 0) => NLW_U0_pipe_eyescandataerror_UNCONNECTED(1 downto 0),
      pipe_gen3_out => NLW_U0_pipe_gen3_out_UNCONNECTED,
      pipe_loopback(2 downto 0) => B"000",
      pipe_mmcm_lock_in => '1',
      pipe_mmcm_rst_n => '1',
      pipe_oobclk_in => '0',
      pipe_pclk_in => '0',
      pipe_pclk_sel_out(1 downto 0) => NLW_U0_pipe_pclk_sel_out_UNCONNECTED(1 downto 0),
      pipe_qpll_lock(0) => NLW_U0_pipe_qpll_lock_UNCONNECTED(0),
      pipe_qrst_fsm(11 downto 0) => NLW_U0_pipe_qrst_fsm_UNCONNECTED(11 downto 0),
      pipe_qrst_idle => NLW_U0_pipe_qrst_idle_UNCONNECTED,
      pipe_rate_fsm(9 downto 0) => NLW_U0_pipe_rate_fsm_UNCONNECTED(9 downto 0),
      pipe_rate_idle => NLW_U0_pipe_rate_idle_UNCONNECTED,
      pipe_rst_fsm(4 downto 0) => NLW_U0_pipe_rst_fsm_UNCONNECTED(4 downto 0),
      pipe_rst_idle => NLW_U0_pipe_rst_idle_UNCONNECTED,
      pipe_rx_0_sigs(24 downto 0) => B"0000000000000000000000000",
      pipe_rx_1_sigs(24 downto 0) => B"0000000000000000000000000",
      pipe_rx_2_sigs(24 downto 0) => B"0000000000000000000000000",
      pipe_rx_3_sigs(24 downto 0) => B"0000000000000000000000000",
      pipe_rx_4_sigs(24 downto 0) => B"0000000000000000000000000",
      pipe_rx_5_sigs(24 downto 0) => B"0000000000000000000000000",
      pipe_rx_6_sigs(24 downto 0) => B"0000000000000000000000000",
      pipe_rx_7_sigs(24 downto 0) => B"0000000000000000000000000",
      pipe_rxbufstatus(5 downto 0) => NLW_U0_pipe_rxbufstatus_UNCONNECTED(5 downto 0),
      pipe_rxcommadet(1 downto 0) => NLW_U0_pipe_rxcommadet_UNCONNECTED(1 downto 0),
      pipe_rxdisperr(15 downto 0) => NLW_U0_pipe_rxdisperr_UNCONNECTED(15 downto 0),
      pipe_rxdlysresetdone(1 downto 0) => NLW_U0_pipe_rxdlysresetdone_UNCONNECTED(1 downto 0),
      pipe_rxnotintable(15 downto 0) => NLW_U0_pipe_rxnotintable_UNCONNECTED(15 downto 0),
      pipe_rxoutclk_in(1 downto 0) => B"00",
      pipe_rxoutclk_out(1 downto 0) => NLW_U0_pipe_rxoutclk_out_UNCONNECTED(1 downto 0),
      pipe_rxphaligndone(1 downto 0) => NLW_U0_pipe_rxphaligndone_UNCONNECTED(1 downto 0),
      pipe_rxpmaresetdone(1 downto 0) => NLW_U0_pipe_rxpmaresetdone_UNCONNECTED(1 downto 0),
      pipe_rxprbscntreset => '0',
      pipe_rxprbserr(1 downto 0) => NLW_U0_pipe_rxprbserr_UNCONNECTED(1 downto 0),
      pipe_rxprbssel(2 downto 0) => B"000",
      pipe_rxstatus(5 downto 0) => NLW_U0_pipe_rxstatus_UNCONNECTED(5 downto 0),
      pipe_rxsyncdone(1 downto 0) => NLW_U0_pipe_rxsyncdone_UNCONNECTED(1 downto 0),
      pipe_rxusrclk_in => '0',
      pipe_sync_fsm_rx(13 downto 0) => NLW_U0_pipe_sync_fsm_rx_UNCONNECTED(13 downto 0),
      pipe_sync_fsm_tx(11 downto 0) => NLW_U0_pipe_sync_fsm_tx_UNCONNECTED(11 downto 0),
      pipe_tx_0_sigs(24 downto 0) => NLW_U0_pipe_tx_0_sigs_UNCONNECTED(24 downto 0),
      pipe_tx_1_sigs(24 downto 0) => NLW_U0_pipe_tx_1_sigs_UNCONNECTED(24 downto 0),
      pipe_tx_2_sigs(24 downto 0) => NLW_U0_pipe_tx_2_sigs_UNCONNECTED(24 downto 0),
      pipe_tx_3_sigs(24 downto 0) => NLW_U0_pipe_tx_3_sigs_UNCONNECTED(24 downto 0),
      pipe_tx_4_sigs(24 downto 0) => NLW_U0_pipe_tx_4_sigs_UNCONNECTED(24 downto 0),
      pipe_tx_5_sigs(24 downto 0) => NLW_U0_pipe_tx_5_sigs_UNCONNECTED(24 downto 0),
      pipe_tx_6_sigs(24 downto 0) => NLW_U0_pipe_tx_6_sigs_UNCONNECTED(24 downto 0),
      pipe_tx_7_sigs(24 downto 0) => NLW_U0_pipe_tx_7_sigs_UNCONNECTED(24 downto 0),
      pipe_txdlysresetdone(1 downto 0) => NLW_U0_pipe_txdlysresetdone_UNCONNECTED(1 downto 0),
      pipe_txinhibit(1 downto 0) => B"00",
      pipe_txoutclk_out => NLW_U0_pipe_txoutclk_out_UNCONNECTED,
      pipe_txphaligndone(1 downto 0) => NLW_U0_pipe_txphaligndone_UNCONNECTED(1 downto 0),
      pipe_txphinitdone(1 downto 0) => NLW_U0_pipe_txphinitdone_UNCONNECTED(1 downto 0),
      pipe_txprbsforceerr => '0',
      pipe_txprbssel(2 downto 0) => B"000",
      pipe_userclk1_in => '1',
      pipe_userclk2_in => '0',
      pl_directed_change_done => pl_directed_change_done,
      pl_directed_link_auton => pl_directed_link_auton,
      pl_directed_link_change(1 downto 0) => pl_directed_link_change(1 downto 0),
      pl_directed_link_speed => pl_directed_link_speed,
      pl_directed_link_width(1 downto 0) => pl_directed_link_width(1 downto 0),
      pl_downstream_deemph_source => pl_downstream_deemph_source,
      pl_initial_link_width(2 downto 0) => pl_initial_link_width(2 downto 0),
      pl_lane_reversal_mode(1 downto 0) => pl_lane_reversal_mode(1 downto 0),
      pl_link_gen2_cap => pl_link_gen2_cap,
      pl_link_partner_gen2_supported => pl_link_partner_gen2_supported,
      pl_link_upcfg_cap => pl_link_upcfg_cap,
      pl_ltssm_state(5 downto 0) => pl_ltssm_state(5 downto 0),
      pl_phy_lnk_up => pl_phy_lnk_up,
      pl_received_hot_rst => pl_received_hot_rst,
      pl_rx_pm_state(1 downto 0) => pl_rx_pm_state(1 downto 0),
      pl_sel_lnk_rate => pl_sel_lnk_rate,
      pl_sel_lnk_width(1 downto 0) => pl_sel_lnk_width(1 downto 0),
      pl_transmit_hot_rst => pl_transmit_hot_rst,
      pl_tx_pm_state(2 downto 0) => pl_tx_pm_state(2 downto 0),
      pl_upstream_prefer_deemph => pl_upstream_prefer_deemph,
      qpll_drp_clk => NLW_U0_qpll_drp_clk_UNCONNECTED,
      qpll_drp_crscode(11 downto 0) => B"000000000000",
      qpll_drp_done(1 downto 0) => B"00",
      qpll_drp_fsm(17 downto 0) => B"000000000000000000",
      qpll_drp_gen3 => NLW_U0_qpll_drp_gen3_UNCONNECTED,
      qpll_drp_ovrd => NLW_U0_qpll_drp_ovrd_UNCONNECTED,
      qpll_drp_reset(1 downto 0) => B"00",
      qpll_drp_rst_n => NLW_U0_qpll_drp_rst_n_UNCONNECTED,
      qpll_drp_start => NLW_U0_qpll_drp_start_UNCONNECTED,
      qpll_qplld => NLW_U0_qpll_qplld_UNCONNECTED,
      qpll_qplllock(1 downto 0) => B"00",
      qpll_qplloutclk(1 downto 0) => B"00",
      qpll_qplloutrefclk(1 downto 0) => B"00",
      qpll_qpllreset(1 downto 0) => NLW_U0_qpll_qpllreset_UNCONNECTED(1 downto 0),
      rx_np_ok => rx_np_ok,
      rx_np_req => rx_np_req,
      s_axis_tx_tdata(63 downto 0) => s_axis_tx_tdata(63 downto 0),
      s_axis_tx_tkeep(7 downto 0) => s_axis_tx_tkeep(7 downto 0),
      s_axis_tx_tlast => s_axis_tx_tlast,
      s_axis_tx_tready => s_axis_tx_tready,
      s_axis_tx_tuser(3 downto 0) => s_axis_tx_tuser(3 downto 0),
      s_axis_tx_tvalid => s_axis_tx_tvalid,
      startup_cfgclk => NLW_U0_startup_cfgclk_UNCONNECTED,
      startup_cfgmclk => NLW_U0_startup_cfgmclk_UNCONNECTED,
      startup_clk => '0',
      startup_eos => NLW_U0_startup_eos_UNCONNECTED,
      startup_eos_in => '0',
      startup_gsr => '0',
      startup_gts => '0',
      startup_keyclearb => '1',
      startup_pack => '0',
      startup_preq => NLW_U0_startup_preq_UNCONNECTED,
      startup_usrcclko => '1',
      startup_usrcclkts => '0',
      startup_usrdoneo => '0',
      startup_usrdonets => '1',
      sys_clk => sys_clk,
      sys_rst_n => sys_rst_n,
      tx_buf_av(5 downto 0) => tx_buf_av(5 downto 0),
      tx_cfg_gnt => tx_cfg_gnt,
      tx_cfg_req => tx_cfg_req,
      tx_err_drop => tx_err_drop,
      user_app_rdy => user_app_rdy,
      user_clk_out => user_clk_out,
      user_lnk_up => user_lnk_up,
      user_reset_out => user_reset_out
    );
end STRUCTURE;
