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//------------------------------------------------------------------------------------
// Filename:    spec7_ps7_0_stub.sv
// Description: This HDL file is intended to be used with following simulators only:
//
//   Vivado Simulator (XSim)
//   Cadence Xcelium Simulator
//   Aldec Riviera-PRO Simulator
//
//------------------------------------------------------------------------------------
`ifdef XILINX_SIMULATOR

`ifndef XILINX_SIMULATOR_BITASBOOL
`define XILINX_SIMULATOR_BITASBOOL
typedef bit bit_as_bool;
`endif

(* SC_MODULE_EXPORT *)
module spec7_ps7_0 (
  output bit [0 : 0] ENET0_GMII_TX_EN,
  output bit [0 : 0] ENET0_GMII_TX_ER,
  output bit_as_bool ENET0_MDIO_MDC,
  output bit_as_bool ENET0_MDIO_O,
  output bit_as_bool ENET0_MDIO_T,
  output bit [7 : 0] ENET0_GMII_TXD,
  input bit_as_bool ENET0_GMII_COL,
  input bit_as_bool ENET0_GMII_CRS,
  input bit_as_bool ENET0_GMII_RX_CLK,
  input bit_as_bool ENET0_GMII_RX_DV,
  input bit_as_bool ENET0_GMII_RX_ER,
  input bit_as_bool ENET0_GMII_TX_CLK,
  input bit_as_bool ENET0_MDIO_I,
  input bit_as_bool ENET0_EXT_INTIN,
  input bit [7 : 0] ENET0_GMII_RXD,
  input bit_as_bool I2C0_SDA_I,
  output bit_as_bool I2C0_SDA_O,
  output bit_as_bool I2C0_SDA_T,
  input bit_as_bool I2C0_SCL_I,
  output bit_as_bool I2C0_SCL_O,
  output bit_as_bool I2C0_SCL_T,
  input bit_as_bool SDIO0_CDN,
  input bit_as_bool SDIO0_WP,
  output bit_as_bool UART0_TX,
  input bit_as_bool UART0_RX,
  output bit [1 : 0] USB0_PORT_INDCTL,
  output bit_as_bool USB0_VBUS_PWRSELECT,
  input bit_as_bool USB0_VBUS_PWRFAULT,
  output bit_as_bool M_AXI_GP0_ARVALID,
  output bit_as_bool M_AXI_GP0_AWVALID,
  output bit_as_bool M_AXI_GP0_BREADY,
  output bit_as_bool M_AXI_GP0_RREADY,
  output bit_as_bool M_AXI_GP0_WLAST,
  output bit_as_bool M_AXI_GP0_WVALID,
  output bit [11 : 0] M_AXI_GP0_ARID,
  output bit [11 : 0] M_AXI_GP0_AWID,
  output bit [11 : 0] M_AXI_GP0_WID,
  output bit [1 : 0] M_AXI_GP0_ARBURST,
  output bit [1 : 0] M_AXI_GP0_ARLOCK,
  output bit [2 : 0] M_AXI_GP0_ARSIZE,
  output bit [1 : 0] M_AXI_GP0_AWBURST,
  output bit [1 : 0] M_AXI_GP0_AWLOCK,
  output bit [2 : 0] M_AXI_GP0_AWSIZE,
  output bit [2 : 0] M_AXI_GP0_ARPROT,
  output bit [2 : 0] M_AXI_GP0_AWPROT,
  output bit [31 : 0] M_AXI_GP0_ARADDR,
  output bit [31 : 0] M_AXI_GP0_AWADDR,
  output bit [31 : 0] M_AXI_GP0_WDATA,
  output bit [3 : 0] M_AXI_GP0_ARCACHE,
  output bit [3 : 0] M_AXI_GP0_ARLEN,
  output bit [3 : 0] M_AXI_GP0_ARQOS,
  output bit [3 : 0] M_AXI_GP0_AWCACHE,
  output bit [3 : 0] M_AXI_GP0_AWLEN,
  output bit [3 : 0] M_AXI_GP0_AWQOS,
  output bit [3 : 0] M_AXI_GP0_WSTRB,
  input bit_as_bool M_AXI_GP0_ACLK,
  input bit_as_bool M_AXI_GP0_ARREADY,
  input bit_as_bool M_AXI_GP0_AWREADY,
  input bit_as_bool M_AXI_GP0_BVALID,
  input bit_as_bool M_AXI_GP0_RLAST,
  input bit_as_bool M_AXI_GP0_RVALID,
  input bit_as_bool M_AXI_GP0_WREADY,
  input bit [11 : 0] M_AXI_GP0_BID,
  input bit [11 : 0] M_AXI_GP0_RID,
  input bit [1 : 0] M_AXI_GP0_BRESP,
  input bit [1 : 0] M_AXI_GP0_RRESP,
  input bit [31 : 0] M_AXI_GP0_RDATA,
  output bit_as_bool S_AXI_HP0_ARREADY,
  output bit_as_bool S_AXI_HP0_AWREADY,
  output bit_as_bool S_AXI_HP0_BVALID,
  output bit_as_bool S_AXI_HP0_RLAST,
  output bit_as_bool S_AXI_HP0_RVALID,
  output bit_as_bool S_AXI_HP0_WREADY,
  output bit [1 : 0] S_AXI_HP0_BRESP,
  output bit [1 : 0] S_AXI_HP0_RRESP,
  output bit [5 : 0] S_AXI_HP0_BID,
  output bit [5 : 0] S_AXI_HP0_RID,
  output bit [31 : 0] S_AXI_HP0_RDATA,
  output bit [7 : 0] S_AXI_HP0_RCOUNT,
  output bit [7 : 0] S_AXI_HP0_WCOUNT,
  output bit [2 : 0] S_AXI_HP0_RACOUNT,
  output bit [5 : 0] S_AXI_HP0_WACOUNT,
  input bit_as_bool S_AXI_HP0_ACLK,
  input bit_as_bool S_AXI_HP0_ARVALID,
  input bit_as_bool S_AXI_HP0_AWVALID,
  input bit_as_bool S_AXI_HP0_BREADY,
  input bit_as_bool S_AXI_HP0_RDISSUECAP1_EN,
  input bit_as_bool S_AXI_HP0_RREADY,
  input bit_as_bool S_AXI_HP0_WLAST,
  input bit_as_bool S_AXI_HP0_WRISSUECAP1_EN,
  input bit_as_bool S_AXI_HP0_WVALID,
  input bit [1 : 0] S_AXI_HP0_ARBURST,
  input bit [1 : 0] S_AXI_HP0_ARLOCK,
  input bit [2 : 0] S_AXI_HP0_ARSIZE,
  input bit [1 : 0] S_AXI_HP0_AWBURST,
  input bit [1 : 0] S_AXI_HP0_AWLOCK,
  input bit [2 : 0] S_AXI_HP0_AWSIZE,
  input bit [2 : 0] S_AXI_HP0_ARPROT,
  input bit [2 : 0] S_AXI_HP0_AWPROT,
  input bit [31 : 0] S_AXI_HP0_ARADDR,
  input bit [31 : 0] S_AXI_HP0_AWADDR,
  input bit [3 : 0] S_AXI_HP0_ARCACHE,
  input bit [3 : 0] S_AXI_HP0_ARLEN,
  input bit [3 : 0] S_AXI_HP0_ARQOS,
  input bit [3 : 0] S_AXI_HP0_AWCACHE,
  input bit [3 : 0] S_AXI_HP0_AWLEN,
  input bit [3 : 0] S_AXI_HP0_AWQOS,
  input bit [5 : 0] S_AXI_HP0_ARID,
  input bit [5 : 0] S_AXI_HP0_AWID,
  input bit [5 : 0] S_AXI_HP0_WID,
  input bit [31 : 0] S_AXI_HP0_WDATA,
  input bit [3 : 0] S_AXI_HP0_WSTRB,
  output bit_as_bool FCLK_CLK0,
  output bit_as_bool FCLK_RESET0_N,
  output bit [53 : 0] MIO,
  output bit_as_bool DDR_CAS_n,
  output bit_as_bool DDR_CKE,
  output bit_as_bool DDR_Clk_n,
  output bit_as_bool DDR_Clk,
  output bit_as_bool DDR_CS_n,
  output bit_as_bool DDR_DRSTB,
  output bit_as_bool DDR_ODT,
  output bit_as_bool DDR_RAS_n,
  output bit_as_bool DDR_WEB,
  output bit [2 : 0] DDR_BankAddr,
  output bit [14 : 0] DDR_Addr,
  output bit_as_bool DDR_VRN,
  output bit_as_bool DDR_VRP,
  output bit [3 : 0] DDR_DM,
  output bit [31 : 0] DDR_DQ,
  output bit [3 : 0] DDR_DQS_n,
  output bit [3 : 0] DDR_DQS,
  output bit_as_bool PS_SRSTB,
  output bit_as_bool PS_CLK,
  output bit_as_bool PS_PORB
);
endmodule
`endif

`ifdef XCELIUM
(* XMSC_MODULE_EXPORT *)
module spec7_ps7_0 (ENET0_GMII_TX_EN,ENET0_GMII_TX_ER,ENET0_MDIO_MDC,ENET0_MDIO_O,ENET0_MDIO_T,ENET0_GMII_TXD,ENET0_GMII_COL,ENET0_GMII_CRS,ENET0_GMII_RX_CLK,ENET0_GMII_RX_DV,ENET0_GMII_RX_ER,ENET0_GMII_TX_CLK,ENET0_MDIO_I,ENET0_EXT_INTIN,ENET0_GMII_RXD,I2C0_SDA_I,I2C0_SDA_O,I2C0_SDA_T,I2C0_SCL_I,I2C0_SCL_O,I2C0_SCL_T,SDIO0_CDN,SDIO0_WP,UART0_TX,UART0_RX,USB0_PORT_INDCTL,USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID,M_AXI_GP0_AWID,M_AXI_GP0_WID,M_AXI_GP0_ARBURST,M_AXI_GP0_ARLOCK,M_AXI_GP0_ARSIZE,M_AXI_GP0_AWBURST,M_AXI_GP0_AWLOCK,M_AXI_GP0_AWSIZE,M_AXI_GP0_ARPROT,M_AXI_GP0_AWPROT,M_AXI_GP0_ARADDR,M_AXI_GP0_AWADDR,M_AXI_GP0_WDATA,M_AXI_GP0_ARCACHE,M_AXI_GP0_ARLEN,M_AXI_GP0_ARQOS,M_AXI_GP0_AWCACHE,M_AXI_GP0_AWLEN,M_AXI_GP0_AWQOS,M_AXI_GP0_WSTRB,M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID,M_AXI_GP0_RID,M_AXI_GP0_BRESP,M_AXI_GP0_RRESP,M_AXI_GP0_RDATA,S_AXI_HP0_ARREADY,S_AXI_HP0_AWREADY,S_AXI_HP0_BVALID,S_AXI_HP0_RLAST,S_AXI_HP0_RVALID,S_AXI_HP0_WREADY,S_AXI_HP0_BRESP,S_AXI_HP0_RRESP,S_AXI_HP0_BID,S_AXI_HP0_RID,S_AXI_HP0_RDATA,S_AXI_HP0_RCOUNT,S_AXI_HP0_WCOUNT,S_AXI_HP0_RACOUNT,S_AXI_HP0_WACOUNT,S_AXI_HP0_ACLK,S_AXI_HP0_ARVALID,S_AXI_HP0_AWVALID,S_AXI_HP0_BREADY,S_AXI_HP0_RDISSUECAP1_EN,S_AXI_HP0_RREADY,S_AXI_HP0_WLAST,S_AXI_HP0_WRISSUECAP1_EN,S_AXI_HP0_WVALID,S_AXI_HP0_ARBURST,S_AXI_HP0_ARLOCK,S_AXI_HP0_ARSIZE,S_AXI_HP0_AWBURST,S_AXI_HP0_AWLOCK,S_AXI_HP0_AWSIZE,S_AXI_HP0_ARPROT,S_AXI_HP0_AWPROT,S_AXI_HP0_ARADDR,S_AXI_HP0_AWADDR,S_AXI_HP0_ARCACHE,S_AXI_HP0_ARLEN,S_AXI_HP0_ARQOS,S_AXI_HP0_AWCACHE,S_AXI_HP0_AWLEN,S_AXI_HP0_AWQOS,S_AXI_HP0_ARID,S_AXI_HP0_AWID,S_AXI_HP0_WID,S_AXI_HP0_WDATA,S_AXI_HP0_WSTRB,FCLK_CLK0,FCLK_RESET0_N,MIO,DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr,DDR_Addr,DDR_VRN,DDR_VRP,DDR_DM,DDR_DQ,DDR_DQS_n,DDR_DQS,PS_SRSTB,PS_CLK,PS_PORB)
(* integer foreign = "SystemC";
*);
  output wire [0 : 0] ENET0_GMII_TX_EN;
  output wire [0 : 0] ENET0_GMII_TX_ER;
  output wire ENET0_MDIO_MDC;
  output wire ENET0_MDIO_O;
  output wire ENET0_MDIO_T;
  output wire [7 : 0] ENET0_GMII_TXD;
  input bit ENET0_GMII_COL;
  input bit ENET0_GMII_CRS;
  input bit ENET0_GMII_RX_CLK;
  input bit ENET0_GMII_RX_DV;
  input bit ENET0_GMII_RX_ER;
  input bit ENET0_GMII_TX_CLK;
  input bit ENET0_MDIO_I;
  input bit ENET0_EXT_INTIN;
  input bit [7 : 0] ENET0_GMII_RXD;
  input bit I2C0_SDA_I;
  output wire I2C0_SDA_O;
  output wire I2C0_SDA_T;
  input bit I2C0_SCL_I;
  output wire I2C0_SCL_O;
  output wire I2C0_SCL_T;
  input bit SDIO0_CDN;
  input bit SDIO0_WP;
  output wire UART0_TX;
  input bit UART0_RX;
  output wire [1 : 0] USB0_PORT_INDCTL;
  output wire USB0_VBUS_PWRSELECT;
  input bit USB0_VBUS_PWRFAULT;
  output wire M_AXI_GP0_ARVALID;
  output wire M_AXI_GP0_AWVALID;
  output wire M_AXI_GP0_BREADY;
  output wire M_AXI_GP0_RREADY;
  output wire M_AXI_GP0_WLAST;
  output wire M_AXI_GP0_WVALID;
  output wire [11 : 0] M_AXI_GP0_ARID;
  output wire [11 : 0] M_AXI_GP0_AWID;
  output wire [11 : 0] M_AXI_GP0_WID;
  output wire [1 : 0] M_AXI_GP0_ARBURST;
  output wire [1 : 0] M_AXI_GP0_ARLOCK;
  output wire [2 : 0] M_AXI_GP0_ARSIZE;
  output wire [1 : 0] M_AXI_GP0_AWBURST;
  output wire [1 : 0] M_AXI_GP0_AWLOCK;
  output wire [2 : 0] M_AXI_GP0_AWSIZE;
  output wire [2 : 0] M_AXI_GP0_ARPROT;
  output wire [2 : 0] M_AXI_GP0_AWPROT;
  output wire [31 : 0] M_AXI_GP0_ARADDR;
  output wire [31 : 0] M_AXI_GP0_AWADDR;
  output wire [31 : 0] M_AXI_GP0_WDATA;
  output wire [3 : 0] M_AXI_GP0_ARCACHE;
  output wire [3 : 0] M_AXI_GP0_ARLEN;
  output wire [3 : 0] M_AXI_GP0_ARQOS;
  output wire [3 : 0] M_AXI_GP0_AWCACHE;
  output wire [3 : 0] M_AXI_GP0_AWLEN;
  output wire [3 : 0] M_AXI_GP0_AWQOS;
  output wire [3 : 0] M_AXI_GP0_WSTRB;
  input bit M_AXI_GP0_ACLK;
  input bit M_AXI_GP0_ARREADY;
  input bit M_AXI_GP0_AWREADY;
  input bit M_AXI_GP0_BVALID;
  input bit M_AXI_GP0_RLAST;
  input bit M_AXI_GP0_RVALID;
  input bit M_AXI_GP0_WREADY;
  input bit [11 : 0] M_AXI_GP0_BID;
  input bit [11 : 0] M_AXI_GP0_RID;
  input bit [1 : 0] M_AXI_GP0_BRESP;
  input bit [1 : 0] M_AXI_GP0_RRESP;
  input bit [31 : 0] M_AXI_GP0_RDATA;
  output wire S_AXI_HP0_ARREADY;
  output wire S_AXI_HP0_AWREADY;
  output wire S_AXI_HP0_BVALID;
  output wire S_AXI_HP0_RLAST;
  output wire S_AXI_HP0_RVALID;
  output wire S_AXI_HP0_WREADY;
  output wire [1 : 0] S_AXI_HP0_BRESP;
  output wire [1 : 0] S_AXI_HP0_RRESP;
  output wire [5 : 0] S_AXI_HP0_BID;
  output wire [5 : 0] S_AXI_HP0_RID;
  output wire [31 : 0] S_AXI_HP0_RDATA;
  output wire [7 : 0] S_AXI_HP0_RCOUNT;
  output wire [7 : 0] S_AXI_HP0_WCOUNT;
  output wire [2 : 0] S_AXI_HP0_RACOUNT;
  output wire [5 : 0] S_AXI_HP0_WACOUNT;
  input bit S_AXI_HP0_ACLK;
  input bit S_AXI_HP0_ARVALID;
  input bit S_AXI_HP0_AWVALID;
  input bit S_AXI_HP0_BREADY;
  input bit S_AXI_HP0_RDISSUECAP1_EN;
  input bit S_AXI_HP0_RREADY;
  input bit S_AXI_HP0_WLAST;
  input bit S_AXI_HP0_WRISSUECAP1_EN;
  input bit S_AXI_HP0_WVALID;
  input bit [1 : 0] S_AXI_HP0_ARBURST;
  input bit [1 : 0] S_AXI_HP0_ARLOCK;
  input bit [2 : 0] S_AXI_HP0_ARSIZE;
  input bit [1 : 0] S_AXI_HP0_AWBURST;
  input bit [1 : 0] S_AXI_HP0_AWLOCK;
  input bit [2 : 0] S_AXI_HP0_AWSIZE;
  input bit [2 : 0] S_AXI_HP0_ARPROT;
  input bit [2 : 0] S_AXI_HP0_AWPROT;
  input bit [31 : 0] S_AXI_HP0_ARADDR;
  input bit [31 : 0] S_AXI_HP0_AWADDR;
  input bit [3 : 0] S_AXI_HP0_ARCACHE;
  input bit [3 : 0] S_AXI_HP0_ARLEN;
  input bit [3 : 0] S_AXI_HP0_ARQOS;
  input bit [3 : 0] S_AXI_HP0_AWCACHE;
  input bit [3 : 0] S_AXI_HP0_AWLEN;
  input bit [3 : 0] S_AXI_HP0_AWQOS;
  input bit [5 : 0] S_AXI_HP0_ARID;
  input bit [5 : 0] S_AXI_HP0_AWID;
  input bit [5 : 0] S_AXI_HP0_WID;
  input bit [31 : 0] S_AXI_HP0_WDATA;
  input bit [3 : 0] S_AXI_HP0_WSTRB;
  output wire FCLK_CLK0;
  output wire FCLK_RESET0_N;
  inout wire [53 : 0] MIO;
  inout wire DDR_CAS_n;
  inout wire DDR_CKE;
  inout wire DDR_Clk_n;
  inout wire DDR_Clk;
  inout wire DDR_CS_n;
  inout wire DDR_DRSTB;
  inout wire DDR_ODT;
  inout wire DDR_RAS_n;
  inout wire DDR_WEB;
  inout wire [2 : 0] DDR_BankAddr;
  inout wire [14 : 0] DDR_Addr;
  inout wire DDR_VRN;
  inout wire DDR_VRP;
  inout wire [3 : 0] DDR_DM;
  inout wire [31 : 0] DDR_DQ;
  inout wire [3 : 0] DDR_DQS_n;
  inout wire [3 : 0] DDR_DQS;
  inout wire PS_SRSTB;
  inout wire PS_CLK;
  inout wire PS_PORB;
endmodule
`endif

`ifdef RIVIERA
(* SC_MODULE_EXPORT *)
module spec7_ps7_0 (ENET0_GMII_TX_EN,ENET0_GMII_TX_ER,ENET0_MDIO_MDC,ENET0_MDIO_O,ENET0_MDIO_T,ENET0_GMII_TXD,ENET0_GMII_COL,ENET0_GMII_CRS,ENET0_GMII_RX_CLK,ENET0_GMII_RX_DV,ENET0_GMII_RX_ER,ENET0_GMII_TX_CLK,ENET0_MDIO_I,ENET0_EXT_INTIN,ENET0_GMII_RXD,I2C0_SDA_I,I2C0_SDA_O,I2C0_SDA_T,I2C0_SCL_I,I2C0_SCL_O,I2C0_SCL_T,SDIO0_CDN,SDIO0_WP,UART0_TX,UART0_RX,USB0_PORT_INDCTL,USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID,M_AXI_GP0_AWID,M_AXI_GP0_WID,M_AXI_GP0_ARBURST,M_AXI_GP0_ARLOCK,M_AXI_GP0_ARSIZE,M_AXI_GP0_AWBURST,M_AXI_GP0_AWLOCK,M_AXI_GP0_AWSIZE,M_AXI_GP0_ARPROT,M_AXI_GP0_AWPROT,M_AXI_GP0_ARADDR,M_AXI_GP0_AWADDR,M_AXI_GP0_WDATA,M_AXI_GP0_ARCACHE,M_AXI_GP0_ARLEN,M_AXI_GP0_ARQOS,M_AXI_GP0_AWCACHE,M_AXI_GP0_AWLEN,M_AXI_GP0_AWQOS,M_AXI_GP0_WSTRB,M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID,M_AXI_GP0_RID,M_AXI_GP0_BRESP,M_AXI_GP0_RRESP,M_AXI_GP0_RDATA,S_AXI_HP0_ARREADY,S_AXI_HP0_AWREADY,S_AXI_HP0_BVALID,S_AXI_HP0_RLAST,S_AXI_HP0_RVALID,S_AXI_HP0_WREADY,S_AXI_HP0_BRESP,S_AXI_HP0_RRESP,S_AXI_HP0_BID,S_AXI_HP0_RID,S_AXI_HP0_RDATA,S_AXI_HP0_RCOUNT,S_AXI_HP0_WCOUNT,S_AXI_HP0_RACOUNT,S_AXI_HP0_WACOUNT,S_AXI_HP0_ACLK,S_AXI_HP0_ARVALID,S_AXI_HP0_AWVALID,S_AXI_HP0_BREADY,S_AXI_HP0_RDISSUECAP1_EN,S_AXI_HP0_RREADY,S_AXI_HP0_WLAST,S_AXI_HP0_WRISSUECAP1_EN,S_AXI_HP0_WVALID,S_AXI_HP0_ARBURST,S_AXI_HP0_ARLOCK,S_AXI_HP0_ARSIZE,S_AXI_HP0_AWBURST,S_AXI_HP0_AWLOCK,S_AXI_HP0_AWSIZE,S_AXI_HP0_ARPROT,S_AXI_HP0_AWPROT,S_AXI_HP0_ARADDR,S_AXI_HP0_AWADDR,S_AXI_HP0_ARCACHE,S_AXI_HP0_ARLEN,S_AXI_HP0_ARQOS,S_AXI_HP0_AWCACHE,S_AXI_HP0_AWLEN,S_AXI_HP0_AWQOS,S_AXI_HP0_ARID,S_AXI_HP0_AWID,S_AXI_HP0_WID,S_AXI_HP0_WDATA,S_AXI_HP0_WSTRB,FCLK_CLK0,FCLK_RESET0_N,MIO,DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr,DDR_Addr,DDR_VRN,DDR_VRP,DDR_DM,DDR_DQ,DDR_DQS_n,DDR_DQS,PS_SRSTB,PS_CLK,PS_PORB)
  output wire [0 : 0] ENET0_GMII_TX_EN;
  output wire [0 : 0] ENET0_GMII_TX_ER;
  output wire ENET0_MDIO_MDC;
  output wire ENET0_MDIO_O;
  output wire ENET0_MDIO_T;
  output wire [7 : 0] ENET0_GMII_TXD;
  input bit ENET0_GMII_COL;
  input bit ENET0_GMII_CRS;
  input bit ENET0_GMII_RX_CLK;
  input bit ENET0_GMII_RX_DV;
  input bit ENET0_GMII_RX_ER;
  input bit ENET0_GMII_TX_CLK;
  input bit ENET0_MDIO_I;
  input bit ENET0_EXT_INTIN;
  input bit [7 : 0] ENET0_GMII_RXD;
  input bit I2C0_SDA_I;
  output wire I2C0_SDA_O;
  output wire I2C0_SDA_T;
  input bit I2C0_SCL_I;
  output wire I2C0_SCL_O;
  output wire I2C0_SCL_T;
  input bit SDIO0_CDN;
  input bit SDIO0_WP;
  output wire UART0_TX;
  input bit UART0_RX;
  output wire [1 : 0] USB0_PORT_INDCTL;
  output wire USB0_VBUS_PWRSELECT;
  input bit USB0_VBUS_PWRFAULT;
  output wire M_AXI_GP0_ARVALID;
  output wire M_AXI_GP0_AWVALID;
  output wire M_AXI_GP0_BREADY;
  output wire M_AXI_GP0_RREADY;
  output wire M_AXI_GP0_WLAST;
  output wire M_AXI_GP0_WVALID;
  output wire [11 : 0] M_AXI_GP0_ARID;
  output wire [11 : 0] M_AXI_GP0_AWID;
  output wire [11 : 0] M_AXI_GP0_WID;
  output wire [1 : 0] M_AXI_GP0_ARBURST;
  output wire [1 : 0] M_AXI_GP0_ARLOCK;
  output wire [2 : 0] M_AXI_GP0_ARSIZE;
  output wire [1 : 0] M_AXI_GP0_AWBURST;
  output wire [1 : 0] M_AXI_GP0_AWLOCK;
  output wire [2 : 0] M_AXI_GP0_AWSIZE;
  output wire [2 : 0] M_AXI_GP0_ARPROT;
  output wire [2 : 0] M_AXI_GP0_AWPROT;
  output wire [31 : 0] M_AXI_GP0_ARADDR;
  output wire [31 : 0] M_AXI_GP0_AWADDR;
  output wire [31 : 0] M_AXI_GP0_WDATA;
  output wire [3 : 0] M_AXI_GP0_ARCACHE;
  output wire [3 : 0] M_AXI_GP0_ARLEN;
  output wire [3 : 0] M_AXI_GP0_ARQOS;
  output wire [3 : 0] M_AXI_GP0_AWCACHE;
  output wire [3 : 0] M_AXI_GP0_AWLEN;
  output wire [3 : 0] M_AXI_GP0_AWQOS;
  output wire [3 : 0] M_AXI_GP0_WSTRB;
  input bit M_AXI_GP0_ACLK;
  input bit M_AXI_GP0_ARREADY;
  input bit M_AXI_GP0_AWREADY;
  input bit M_AXI_GP0_BVALID;
  input bit M_AXI_GP0_RLAST;
  input bit M_AXI_GP0_RVALID;
  input bit M_AXI_GP0_WREADY;
  input bit [11 : 0] M_AXI_GP0_BID;
  input bit [11 : 0] M_AXI_GP0_RID;
  input bit [1 : 0] M_AXI_GP0_BRESP;
  input bit [1 : 0] M_AXI_GP0_RRESP;
  input bit [31 : 0] M_AXI_GP0_RDATA;
  output wire S_AXI_HP0_ARREADY;
  output wire S_AXI_HP0_AWREADY;
  output wire S_AXI_HP0_BVALID;
  output wire S_AXI_HP0_RLAST;
  output wire S_AXI_HP0_RVALID;
  output wire S_AXI_HP0_WREADY;
  output wire [1 : 0] S_AXI_HP0_BRESP;
  output wire [1 : 0] S_AXI_HP0_RRESP;
  output wire [5 : 0] S_AXI_HP0_BID;
  output wire [5 : 0] S_AXI_HP0_RID;
  output wire [31 : 0] S_AXI_HP0_RDATA;
  output wire [7 : 0] S_AXI_HP0_RCOUNT;
  output wire [7 : 0] S_AXI_HP0_WCOUNT;
  output wire [2 : 0] S_AXI_HP0_RACOUNT;
  output wire [5 : 0] S_AXI_HP0_WACOUNT;
  input bit S_AXI_HP0_ACLK;
  input bit S_AXI_HP0_ARVALID;
  input bit S_AXI_HP0_AWVALID;
  input bit S_AXI_HP0_BREADY;
  input bit S_AXI_HP0_RDISSUECAP1_EN;
  input bit S_AXI_HP0_RREADY;
  input bit S_AXI_HP0_WLAST;
  input bit S_AXI_HP0_WRISSUECAP1_EN;
  input bit S_AXI_HP0_WVALID;
  input bit [1 : 0] S_AXI_HP0_ARBURST;
  input bit [1 : 0] S_AXI_HP0_ARLOCK;
  input bit [2 : 0] S_AXI_HP0_ARSIZE;
  input bit [1 : 0] S_AXI_HP0_AWBURST;
  input bit [1 : 0] S_AXI_HP0_AWLOCK;
  input bit [2 : 0] S_AXI_HP0_AWSIZE;
  input bit [2 : 0] S_AXI_HP0_ARPROT;
  input bit [2 : 0] S_AXI_HP0_AWPROT;
  input bit [31 : 0] S_AXI_HP0_ARADDR;
  input bit [31 : 0] S_AXI_HP0_AWADDR;
  input bit [3 : 0] S_AXI_HP0_ARCACHE;
  input bit [3 : 0] S_AXI_HP0_ARLEN;
  input bit [3 : 0] S_AXI_HP0_ARQOS;
  input bit [3 : 0] S_AXI_HP0_AWCACHE;
  input bit [3 : 0] S_AXI_HP0_AWLEN;
  input bit [3 : 0] S_AXI_HP0_AWQOS;
  input bit [5 : 0] S_AXI_HP0_ARID;
  input bit [5 : 0] S_AXI_HP0_AWID;
  input bit [5 : 0] S_AXI_HP0_WID;
  input bit [31 : 0] S_AXI_HP0_WDATA;
  input bit [3 : 0] S_AXI_HP0_WSTRB;
  output wire FCLK_CLK0;
  output wire FCLK_RESET0_N;
  inout wire [53 : 0] MIO;
  inout wire DDR_CAS_n;
  inout wire DDR_CKE;
  inout wire DDR_Clk_n;
  inout wire DDR_Clk;
  inout wire DDR_CS_n;
  inout wire DDR_DRSTB;
  inout wire DDR_ODT;
  inout wire DDR_RAS_n;
  inout wire DDR_WEB;
  inout wire [2 : 0] DDR_BankAddr;
  inout wire [14 : 0] DDR_Addr;
  inout wire DDR_VRN;
  inout wire DDR_VRP;
  inout wire [3 : 0] DDR_DM;
  inout wire [31 : 0] DDR_DQ;
  inout wire [3 : 0] DDR_DQS_n;
  inout wire [3 : 0] DDR_DQS;
  inout wire PS_SRSTB;
  inout wire PS_CLK;
  inout wire PS_PORB;
endmodule
`endif
