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// IP VLNV: xilinx.com:user:axi_master:1.0
// IP Revision: 8

(* X_CORE_INFO = "axi_master,Vivado 2019.2" *)
(* CHECK_LICENSE_TYPE = "spec7_axi_master_0,axi_master,{}" *)
(* CORE_GENERATION_INFO = "spec7_axi_master_0,axi_master,{x_ipProduct=Vivado 2019.2,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=axi_master,x_ipVersion=1.0,x_ipCoreRevision=8,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,M_ID_WIDTH=4,M_ADDR_WIDTH=32,M_LEN_WIDTH=4,M_DATA_WIDTH=32,NUM_BYTES_WIDTH=32}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module spec7_axi_master_0 (
  ps_image_read,
  m_clk,
  m_resetn,
  pio_valid_in,
  pio_data_in,
  BASE_ADDR_MM,
  NUM_BYTES,
  m_awvalid,
  m_awready,
  m_awid,
  m_awaddr,
  m_awlen,
  m_awsize,
  m_awburst,
  m_awprot,
  m_awcache,
  m_wvalid,
  m_wready,
  m_wid,
  m_wdata,
  m_wstrb,
  m_wlast,
  m_bvalid,
  m_bready,
  m_bid,
  m_bresp,
  m_arvalid,
  m_arready,
  m_arid,
  m_araddr,
  m_arlen,
  m_arsize,
  m_arburst,
  m_arprot,
  m_arcache,
  m_rvalid,
  m_rready,
  m_rid,
  m_rdata,
  m_rresp,
  m_rlast,
  trnfr_cmpl
);

input wire [0 : 0] ps_image_read;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_signal_clock, ASSOCIATED_BUSIF m, ASSOCIATED_RESET m_resetn, FREQ_HZ 62500000, PHASE 0.000, CLK_DOMAIN spec7_pcie_7x_0_user_clk_out, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 m_signal_clock CLK" *)
input wire m_clk;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m_signal_reset, POLARITY ACTIVE_LOW, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 m_signal_reset RST" *)
input wire m_resetn;
input wire pio_valid_in;
input wire [31 : 0] pio_data_in;
input wire [31 : 0] BASE_ADDR_MM;
input wire [31 : 0] NUM_BYTES;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m AWVALID" *)
output wire m_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m AWREADY" *)
input wire m_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m AWID" *)
output wire [3 : 0] m_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m AWADDR" *)
output wire [31 : 0] m_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m AWLEN" *)
output wire [3 : 0] m_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m AWSIZE" *)
output wire [2 : 0] m_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m AWBURST" *)
output wire [1 : 0] m_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m AWPROT" *)
output wire [2 : 0] m_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m AWCACHE" *)
output wire [3 : 0] m_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m WVALID" *)
output wire m_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m WREADY" *)
input wire m_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m WID" *)
output wire [3 : 0] m_wid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m WDATA" *)
output wire [31 : 0] m_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m WSTRB" *)
output wire [3 : 0] m_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m WLAST" *)
output wire m_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m BVALID" *)
input wire m_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m BREADY" *)
output wire m_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m BID" *)
input wire [3 : 0] m_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m BRESP" *)
input wire [1 : 0] m_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m ARVALID" *)
output wire m_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m ARREADY" *)
input wire m_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m ARID" *)
output wire [3 : 0] m_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m ARADDR" *)
output wire [31 : 0] m_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m ARLEN" *)
output wire [3 : 0] m_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m ARSIZE" *)
output wire [2 : 0] m_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m ARBURST" *)
output wire [1 : 0] m_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m ARPROT" *)
output wire [2 : 0] m_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m ARCACHE" *)
output wire [3 : 0] m_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m RVALID" *)
input wire m_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m RREADY" *)
output wire m_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m RID" *)
input wire [3 : 0] m_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m RDATA" *)
input wire [31 : 0] m_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m RRESP" *)
input wire [1 : 0] m_rresp;
(* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME m, DATA_WIDTH 32, PROTOCOL AXI3, FREQ_HZ 62500000, ID_WIDTH 4, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 1, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 16, PHASE 0.000, CLK_DOMAIN spec7_pcie_7x_0_user_clk_out, NUM_READ_THREADS 1, NUM_WRITE_THREAD\
S 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0, INSERT_VIP 0" *)
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 m RLAST" *)
input wire m_rlast;
output wire [0 : 0] trnfr_cmpl;

  axi_master #(
    .M_ID_WIDTH(4),
    .M_ADDR_WIDTH(32),
    .M_LEN_WIDTH(4),
    .M_DATA_WIDTH(32),
    .NUM_BYTES_WIDTH(32)
  ) inst (
    .ps_image_read(ps_image_read),
    .m_clk(m_clk),
    .m_resetn(m_resetn),
    .pio_valid_in(pio_valid_in),
    .pio_data_in(pio_data_in),
    .BASE_ADDR_MM(BASE_ADDR_MM),
    .NUM_BYTES(NUM_BYTES),
    .m_awvalid(m_awvalid),
    .m_awready(m_awready),
    .m_awid(m_awid),
    .m_awaddr(m_awaddr),
    .m_awlen(m_awlen),
    .m_awsize(m_awsize),
    .m_awburst(m_awburst),
    .m_awprot(m_awprot),
    .m_awcache(m_awcache),
    .m_wvalid(m_wvalid),
    .m_wready(m_wready),
    .m_wid(m_wid),
    .m_wdata(m_wdata),
    .m_wstrb(m_wstrb),
    .m_wlast(m_wlast),
    .m_bvalid(m_bvalid),
    .m_bready(m_bready),
    .m_bid(m_bid),
    .m_bresp(m_bresp),
    .m_arvalid(m_arvalid),
    .m_arready(m_arready),
    .m_arid(m_arid),
    .m_araddr(m_araddr),
    .m_arlen(m_arlen),
    .m_arsize(m_arsize),
    .m_arburst(m_arburst),
    .m_arprot(m_arprot),
    .m_arcache(m_arcache),
    .m_rvalid(m_rvalid),
    .m_rready(m_rready),
    .m_rid(m_rid),
    .m_rdata(m_rdata),
    .m_rresp(m_rresp),
    .m_rlast(m_rlast),
    .trnfr_cmpl(trnfr_cmpl)
  );
endmodule
