-------------------------------------------------------------------------------
-- Title      : Tandem Boot for SPEC7
--            : based on ZYNQ Z030/Z035/Z045
-- Project    : WR PTP Core and EMPIR 17IND14 WRITE 
-- URL        : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
--            : http://empir.npl.co.uk/write/
-------------------------------------------------------------------------------
-- File       : spec7_tandem_boot_top.vhd
-- Author(s)  : Peter Jansweijer <peterj@nikhef.nl>
--            : Mamta Ramendra Shukla <mamta.ramendra.shukla@cern.ch>
--            : Javier D. Garcia <jgarcia@gl-research.com>
-- Company    : Nikhef, CERN
-- Created    : 2021-06-27
-- Last update: 2021-06-27
-- Standard   : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for Tandem Boot for SPEC7.
--              See also EMPIR 17IND14 WRITE Project (http://empir.npl.co.uk/write/)
--
-- This Tandem Boot design is a bare minimal PCIe core that enables early
-- PCIe enumeration for the SPEC7 by providing a Tandem PROM mode boot design
-- that reserves the appropriated BAR sizes for SPEC7 designs based on the
-- non Tandem capable Xilinx XDMA core that are loaded afterwards.
--
-------------------------------------------------------------------------------
-- Copyright (c) 2021 Nikhef, CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE.  See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity spec7_tandem_boot_top is
  port (
    DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
    DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
    DDR_cas_n : inout STD_LOGIC;
    DDR_ck_n : inout STD_LOGIC;
    DDR_ck_p : inout STD_LOGIC;
    DDR_cke : inout STD_LOGIC;
    DDR_cs_n : inout STD_LOGIC;
    DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
    DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
    DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
    DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
    DDR_odt : inout STD_LOGIC;
    DDR_ras_n : inout STD_LOGIC;
    DDR_reset_n : inout STD_LOGIC;
    DDR_we_n : inout STD_LOGIC;
    FIXED_IO_ddr_vrn : inout STD_LOGIC;
    FIXED_IO_ddr_vrp : inout STD_LOGIC;
    FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
    FIXED_IO_ps_clk : inout STD_LOGIC;
    FIXED_IO_ps_porb : inout STD_LOGIC;
    FIXED_IO_ps_srstb : inout STD_LOGIC;
    pci_clk_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    pci_clk_p : in STD_LOGIC_VECTOR ( 0 to 0 );
    perst_n : in STD_LOGIC;
    rxn : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    txn : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txp : out STD_LOGIC_VECTOR ( 1 downto 0 )
  );
end spec7_tandem_boot_top;

architecture STRUCTURE of spec7_tandem_boot_top is
  component ps_pci_tandem_wrapper is
  port (
    pci_clk_n : in STD_LOGIC_VECTOR ( 0 to 0 );
    pci_clk_p : in STD_LOGIC_VECTOR ( 0 to 0 );
    perst_n : in STD_LOGIC;
    rxn : in STD_LOGIC_VECTOR ( 1 downto 0 );
    rxp : in STD_LOGIC_VECTOR ( 1 downto 0 );
    txn : out STD_LOGIC_VECTOR ( 1 downto 0 );
    txp : out STD_LOGIC_VECTOR ( 1 downto 0 );
    DDR_cas_n : inout STD_LOGIC;
    DDR_cke : inout STD_LOGIC;
    DDR_ck_n : inout STD_LOGIC;
    DDR_ck_p : inout STD_LOGIC;
    DDR_cs_n : inout STD_LOGIC;
    DDR_reset_n : inout STD_LOGIC;
    DDR_odt : inout STD_LOGIC;
    DDR_ras_n : inout STD_LOGIC;
    DDR_we_n : inout STD_LOGIC;
    DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
    DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
    DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
    DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
    DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
    DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
    FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
    FIXED_IO_ddr_vrn : inout STD_LOGIC;
    FIXED_IO_ddr_vrp : inout STD_LOGIC;
    FIXED_IO_ps_srstb : inout STD_LOGIC;
    FIXED_IO_ps_clk : inout STD_LOGIC;
    FIXED_IO_ps_porb : inout STD_LOGIC
  );
  end component ps_pci_tandem_wrapper;
begin
ps_pci_tandem_wrapper_i: component ps_pci_tandem_wrapper
     port map (
      DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
      DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
      DDR_cas_n => DDR_cas_n,
      DDR_ck_n => DDR_ck_n,
      DDR_ck_p => DDR_ck_p,
      DDR_cke => DDR_cke,
      DDR_cs_n => DDR_cs_n,
      DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
      DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
      DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
      DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
      DDR_odt => DDR_odt,
      DDR_ras_n => DDR_ras_n,
      DDR_reset_n => DDR_reset_n,
      DDR_we_n => DDR_we_n,
      FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
      FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
      FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
      FIXED_IO_ps_clk => FIXED_IO_ps_clk,
      FIXED_IO_ps_porb => FIXED_IO_ps_porb,
      FIXED_IO_ps_srstb => FIXED_IO_ps_srstb,
      pci_clk_n(0) => pci_clk_n(0),
      pci_clk_p(0) => pci_clk_p(0),
      perst_n => perst_n,
      rxn(1 downto 0) => rxn(1 downto 0),
      rxp(1 downto 0) => rxp(1 downto 0),
      txn(1 downto 0) => txn(1 downto 0),
      txp(1 downto 0) => txp(1 downto 0)
    );
end STRUCTURE;
