--------------------------------------------------------------------------------
--
-- This VHDL file was generated by EASE/HDL 8.3 Revision 5 from HDL Works B.V.
--
-- Ease library  : design
-- HDL library   : work
-- Host name     : SERING
-- User name     : peterj
-- Time stamp    : Tue Nov 26 16:59:52 2019
--
-- Designed by   : 
-- Company       : 
-- Project info  : 
--
--------------------------------------------------------------------------------

--------------------------------------------------------------------------------
-- Object        : Entity design.KnightRider
-- Last modified : Thu Nov 14 16:30:02 2019
--------------------------------------------------------------------------------



library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity KnightRider is
  port (
    Clk : in     std_logic;
    En  : in     std_logic;
    LED : out    std_logic_vector(3 downto 0));
end entity KnightRider;

--------------------------------------------------------------------------------
-- Object        : Architecture design.KnightRider.structure
-- Last modified : Thu Nov 14 16:30:02 2019
--------------------------------------------------------------------------------


architecture structure of KnightRider is

begin
   Process (Clk)
      Variable Cnt : Unsigned(3 Downto 0) := (Others => '0');
   Begin       
      If Rising_Edge(Clk) Then
         If En = '1' Then
            If (Cnt = x"6") Then
               Cnt := (Others => '0');
            Else
               Cnt := Cnt + 1;
            End If;
         End If;
         Case Cnt is
            when X"0" => LED <= "0001";
            when X"1" => LED <= "0010";
            when x"2" => LED <= "0100";
            when x"3" => LED <= "1000";
            when x"4" => LED <= "0100";
            when x"5" => LED <= "0010";
            when others => LED <= "0001";
         End Case ;
      End If;
   End Process;
end architecture structure ; -- of KnightRider

--------------------------------------------------------------------------------
-- Object        : Entity design.AndInv
-- Last modified : Thu Nov 14 15:46:00 2019
--------------------------------------------------------------------------------



library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity AndInv is
  port (
    A  : in     std_logic;
    Bn : in     std_logic;
    O  : out    std_logic);
end entity AndInv;

--------------------------------------------------------------------------------
-- Object        : Architecture design.AndInv.rtl
-- Last modified : Thu Nov 14 15:46:00 2019
--------------------------------------------------------------------------------


architecture rtl of AndInv is

begin
   O <= A And NOT Bn;
end architecture rtl ; -- of AndInv

--------------------------------------------------------------------------------
-- Object        : Entity design.Reg1
-- Last modified : Thu Nov 14 15:46:00 2019
--------------------------------------------------------------------------------



library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Reg1 is
  port (
    Clk : in     std_logic;
    D   : in     std_logic;
    Q   : out    std_logic);
end entity Reg1;

--------------------------------------------------------------------------------
-- Object        : Architecture design.Reg1.structure
-- Last modified : Thu Nov 14 15:46:00 2019
--------------------------------------------------------------------------------


architecture structure of Reg1 is

begin
   Process (Clk)
   Begin       
      If Rising_Edge(Clk) Then
         Q <= D;
      End If;
   End Process;
end architecture structure ; -- of Reg1

--------------------------------------------------------------------------------
-- Object        : Entity design.Counter
-- Last modified : Thu Nov 14 15:46:00 2019
--------------------------------------------------------------------------------



library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity Counter is
  port (
    Clk : in     std_logic;
    Q   : out    std_logic_vector(31 downto 0));
end entity Counter;

--------------------------------------------------------------------------------
-- Object        : Architecture design.Counter.rtl
-- Last modified : Thu Nov 14 15:46:00 2019
--------------------------------------------------------------------------------


architecture rtl of Counter is

begin
   Process (Clk)
      Variable Count: Unsigned(31 downto 0) := (Others => '0');
   Begin       
      If Rising_Edge(Clk) Then
         Count := Count + 1;
      End If;
      Q <= Std_Logic_Vector (Count);
   End Process;

end architecture rtl ; -- of Counter

--------------------------------------------------------------------------------
-- Object        : Entity design.spec7_blink
-- Last modified : Tue Nov 26 16:59:44 2019
--------------------------------------------------------------------------------



library ieee, unisim;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use unisim.VCOMPONENTS.all;

entity spec7_blink is
  generic(
    Q : natural := 24);
  port (
    CLK_DMTD_N    : in     std_logic;
    CLK_DMTD_P    : in     std_logic;
    LED           : out    std_logic_vector(3 downto 0);
    prsnt_m2c_l_i : in     std_logic;
    suicide_n_o   : out    std_logic;
    wdog_n_o      : out    std_logic);
end entity spec7_blink;

--------------------------------------------------------------------------------
-- Object        : Architecture design.spec7_blink.structure
-- Last modified : Tue Nov 26 16:59:44 2019
--------------------------------------------------------------------------------

architecture structure of spec7_blink is

  signal O    : std_ulogic;
  signal u0_Q : std_logic_vector(31 downto 0);
  signal u2_Q : std_logic;
  signal u3_O : std_logic;

  component Counter
    port (
      Clk : in     std_logic;
      Q   : out    std_logic_vector(31 downto 0));
  end component Counter;

  component Reg1
    port (
      Clk : in     std_logic;
      D   : in     std_logic;
      Q   : out    std_logic);
  end component Reg1;

  component AndInv
    port (
      A  : in     std_logic;
      Bn : in     std_logic;
      O  : out    std_logic);
  end component AndInv;

  component KnightRider
    port (
      Clk : in     std_logic;
      En  : in     std_logic;
      LED : out    std_logic_vector(3 downto 0));
  end component KnightRider;

begin
  --For normal operation choose Q24 (@ 200 MHz)
  --For quick simulation choose Q4
  --PRSNT_M2C_L must be defined as input.
  --Driving this pin closes the TDO line to the JTAG programmer if there is no FMC card on board
  -- 
  suicide_n_o <= '1';
  wdog_n_o <= '1';

  u0: Counter
    port map(
      Clk => O,
      Q   => u0_Q);

  u2: Reg1
    port map(
      Clk => O,
      D   => u0_Q(Q),
      Q   => u2_Q);

  u3: AndInv
    port map(
      A  => u0_Q(Q),
      Bn => u2_Q,
      O  => u3_O);

  u1: KnightRider
    port map(
      Clk => O,
      En  => u3_O,
      LED => LED);

  u4: IBUFDS
    generic map(
      CAPACITANCE      => "DONT_CARE",
      DIFF_TERM        => TRUE,
      IBUF_DELAY_VALUE => "0",
      IBUF_LOW_PWR     => TRUE,
      IFD_DELAY_VALUE  => "AUTO",
      IOSTANDARD       => "DEFAULT",
      DQS_BIAS         => "FALSE")
    port map(
      O  => O,
      I  => CLK_DMTD_P,
      IB => CLK_DMTD_N);
end architecture structure ; -- of spec7_blink

