#
# projetc_properties.tcl
# This file contains the general project properties such as the project name and
# the directory where Vivado is doing it's job
#
# ====================================================

# ====================================================
# SELECT DESIGN TO BUILD:
# ====================================================
set version ""
# Reference Design (using fmc-dio-5chttla => https://ohwr.org/project/fmc-dio-5chttla/wikis/home)
# HPSEC Design (using Bulls-Eye connector)
set spec7_design spec7_ref_top
#set spec7_design spec7_hpsec_top
# Uncomment the line below for older SPEC7v2
set version "_v2"
# ====================================================

# ====================================================
# SELECT DEVICE TO BUILD:
# ====================================================
# SPEC7 equipped with ZYNQ XC7Z035FBG676-1 (speed grade -1 has lowest performance)
set device xc7z035fbg676-1
#set device xc7z030fbg676-1
# ====================================================

# ====================================================
# SELECT PPS SINLGE / DIFFERENTIAL:
# ====================================================
# When Bulls-Eye connector is used as input (HPSEC).
# Differential: B01/B02 (LVDS)
# Single-ended: B11     (TTL, 5V tolerant) 
set pps_in "single"
#set pps_in "diff"
# ====================================================

# ====================================================
# SELECT REFERENCE OSCILATOR TUNE SLOPE (DEFAULT TRUE):
# ====================================================
# Uncomment the line below when the reference oscillator has negative tune slope.
#set refclk_tune_pos_slope FALSE
# ====================================================

# ====================================================
# ENABLE IRIG_B OUTPUT  (DEFAULT FALSE):
# ====================================================
# Uncomment the line below to enable IRIG_B on LA32
#set irig_b_enable TRUE
# ====================================================

# Translate True/False into boolean values 1'b1, 1'b0, that are accepted by Vivado 
set vivbool_refclk_tune_pos_slope 1'b1
if [info exists refclk_tune_pos_slope] {
  if (!$refclk_tune_pos_slope) {
    set vivbool_refclk_tune_pos_slope 1'b0
  }
}
set vivbool_irig_b_enable 1'b0
if [info exists irig_b_enable] {
  if ($irig_b_enable) {
    set vivbool_irig_b_enable 1'b1
  }
}

set proj_name spec7_wr_ref_top
set proj_dir work
set script_dir [pwd]/../../../sw/scripts
set wrpc_cpu_initf [pwd]/../../../sw/precompiled/wrps-sw-v5_spec7/wrc.bram
set wrpc_cpu_elf [pwd]/../../../sw/precompiled/wrps-sw-v5_spec7/wrc.elf
set wrpc_cpu_instpath "wrpc_cpu_memory"

# update revision except when argument "no_update_revison" is passed (as for example by viv_do_programm.tcl)
if {$argc == 0 || $argv != "no_update_revision"} {
  source $script_dir/revisiondate.tcl

  set generics "g_design=$spec7_design \
                g_use_pps_in=$pps_in \
                g_dpram_initf=$wrpc_cpu_initf \
                g_refclk_tune_pos_slope=$vivbool_refclk_tune_pos_slope \
                g_irig_b_enable=$vivbool_irig_b_enable"
}
