# From directory ....spec7/hdl/syn/spec7_ref_design
# hdlmake list-files > proj_file_list.txt

# Note: for the REFerence and HPSEC design,
# the XDC file selection is done in sw/scripts/viv_do_all.tcl, based on $spec7_design
#../../top/spec7_ref_design/spec7_wr_ref_top.xdc
#../../top/spec7_ref_design/spec7_wr_hpsec_top.xdc

../../top/spec7_ref_design/wr_irigb_conv.vhd
../../top/spec7_ref_design/pll_62m5_500m.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_dec_8b10b.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_edge_detect.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_enc_8b10b.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_reset.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_serial_dac.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_sync.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_sync_register.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gencores_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/jtag_tap.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/platform/generic/lm32_multiplier.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
../../wr-cores/modules/fabric/xwrf_loopback/lbk_pkg.vhd
../../wr-cores/modules/timing/pulse_stamper.vhd
../../wr-cores/modules/wr_endpoint/ep_crc32_pkg.vhd
../../wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
../../wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd
../../wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd
../../wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd
../../wr-cores/modules/wr_streamers/escape_detector.vhd
../../wr-cores/modules/wr_streamers/escape_inserter.vhd
../../wr-cores/modules/wr_streamers/fifo_showahead_adapter.vhd
../../wr-cores/modules/wr_streamers/wr_streamers_wbgen2_pkg.vhd
../../wr-cores/modules/wr_tbi_phy/disparity_gen_pkg.vhd
../../wr-cores/modules/wrc_core/wrc_diags_pkg.vhd
../../wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd
../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx-lp/gtx_comma_detect_lp.vhd
../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx-lp/whiterabbit_gtxe2_channel_wrapper_gt_lp.vhd
../../wr-cores/ip_cores/general-cores/modules/axi/axi4_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_crc_gen.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/genram_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd
../../wr-cores/modules/fabric/wr_fabric_pkg.vhd
../../wr-cores/modules/fabric/xwrf_loopback/lbk_wishbone_controller.vhd
../../wr-cores/modules/timing/dmtd_sampler.vhd
../../wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd
../../wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd
../../wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
../../wr-cores/modules/wr_streamers/wr_streamers_wb.vhd
../../wr-cores/modules/wrc_core/wrc_diags_wb.vhd
../../wr-cores/modules/wrc_core/wrc_syscon_wb.vhd
../../board/even_odd_det.vhd
../../top/spec7_ref_design/gen_10mhz.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_async_counter_diff.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_sync_word_wr.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
../../wr-cores/modules/fabric/xwrf_mux.vhd
../../wr-cores/modules/timing/dmtd_sampler.vhd
../../wr-cores/modules/timing/pulse_stamper_sync.vhd
../../wr-cores/modules/wr_endpoint/endpoint_pkg.vhd
../../wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd
../../wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd
../../wr-cores/modules/wr_softpll_ng/spll_aligner.vhd
../../wr-cores/modules/wr_streamers/dropping_buffer.vhd
../../wr-cores/modules/wr_streamers/fixed_latency_ts_match.vhd
../../wr-cores/modules/wr_streamers/ts_restore_tai.vhd
../../wr-cores/modules/wrc_core/xwrc_diags_wb.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo_dual_rst.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_split.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
../../wr-cores/modules/timing/dmtd_with_deglitcher.vhd
../../wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd
../../wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd
../../wr-cores/modules/wrc_core/wrcore_pkg.vhd
../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx-lp/wr_gtx_phy_family7_lp.vhd
../../wr-cores/platform/xilinx/wr_xilinx_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
../../wr-cores/modules/fabric/xwb_fabric_sink.vhd
../../wr-cores/modules/fabric/xwb_fabric_source.vhd
../../wr-cores/modules/timing/dmtd_phase_meas.vhd
../../wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd
../../wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd
../../wr-cores/modules/wr_endpoint/ep_leds_controller.vhd
../../wr-cores/modules/wr_endpoint/ep_rtu_header_extract.vhd
../../wr-cores/modules/wr_endpoint/ep_rx_crc_size_check.vhd
../../wr-cores/modules/wr_endpoint/ep_rx_early_address_match.vhd
../../wr-cores/modules/wr_endpoint/ep_rx_oob_insert.vhd
../../wr-cores/modules/wr_endpoint/ep_rx_status_reg_insert.vhd
../../wr-cores/modules/wr_endpoint/ep_rx_vlan_unit.vhd
../../wr-cores/modules/wr_endpoint/ep_rx_wb_master.vhd
../../wr-cores/modules/wr_endpoint/ep_sync_detect.vhd
../../wr-cores/modules/wr_endpoint/ep_sync_detect_16bit.vhd
../../wr-cores/modules/wr_endpoint/ep_ts_counter.vhd
../../wr-cores/modules/wr_endpoint/ep_tx_crc_inserter.vhd
../../wr-cores/modules/wr_endpoint/ep_tx_header_processor.vhd
../../wr-cores/modules/wr_endpoint/ep_tx_inject_ctrl.vhd
../../wr-cores/modules/wr_endpoint/ep_tx_packet_injection.vhd
../../wr-cores/modules/wr_endpoint/ep_tx_pcs_16bit.vhd
../../wr-cores/modules/wr_endpoint/ep_tx_pcs_8bit.vhd
../../wr-cores/modules/wr_streamers/streamers_pkg.vhd
../../wr-cores/board/common/wr_board_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/common/inferred_sync_fifo.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_simple_dpram.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd
../../wr-cores/modules/wr_endpoint/ep_packet_filter.vhd
../../wr-cores/modules/wr_endpoint/ep_rx_pcs_16bit.vhd
../../wr-cores/modules/wr_endpoint/ep_rx_pcs_8bit.vhd
../../wr-cores/modules/wr_endpoint/ep_timestamping_unit.vhd
../../wr-cores/modules/wr_endpoint/ep_tx_vlan_unit.vhd
../../wr-cores/modules/wr_streamers/streamers_priv_pkg.vhd
../../wr-cores/modules/wr_streamers/xrx_streamers_stats.vhd
../../wr-cores/modules/wr_streamers/xtx_streamers_stats.vhd
../../board/wr_spec7_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.vhd
../../wr-cores/modules/wr_endpoint/ep_1000basex_pcs.vhd
../../wr-cores/modules/wr_endpoint/ep_tx_path.vhd
../../wr-cores/modules/wr_streamers/fixed_latency_delay.vhd
../../wr-cores/modules/wr_streamers/xrtx_streamers_stats.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd
../../wr-cores/modules/fabric/xwrf_loopback/xwrf_loopback.vhd
../../wr-cores/modules/wr_endpoint/ep_rx_buffer.vhd
../../wr-cores/modules/wr_mini_nic/wr_mini_nic.vhd
../../wr-cores/modules/wr_streamers/xrx_streamer.vhd
../../wr-cores/modules/wr_streamers/xtx_streamer.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd
../../wr-cores/modules/wr_endpoint/ep_rx_path.vhd
../../wr-cores/modules/wr_mini_nic/xwr_mini_nic.vhd
../../wr-cores/modules/wr_softpll_ng/spll_wb_slave.vhd
../../wr-cores/modules/wr_streamers/xwr_streamers.vhd
../../wr-cores/modules/wr_endpoint/wr_endpoint.vhd
../../wr-cores/modules/wr_softpll_ng/wr_softpll_ng.vhd
../../wr-cores/modules/wrc_core/wrc_periph.vhd
../../wr-cores/modules/wr_endpoint/xwr_endpoint.vhd
../../wr-cores/modules/wr_softpll_ng/xwr_softpll_ng.vhd
../../wr-cores/modules/wrc_core/wr_core.vhd
../../wr-cores/modules/wrc_core/xwr_core.vhd
../../wr-cores/board/common/xwrc_board_common.vhd
../../board/xwrc_board_spec7.vhd
../../top/spec7_ref_design/spec7_wr_ref_top.vhd


# bmm not supported by hdlmake? Need to add it manually...
../../ip/ps_pcie.bd
../../ip/ip/bcd_divider/bcd_divider.xci
../../ip/ip/tai_divider/tai_divider.xci
../../top/spec7_ref_design/spec7_wr_ref_top.bmm

# include hardware version ID un FPGA USER_ID register:
hdl_version.xdc
