#
#	viv_gen_bin_mcs.tcl
#	Implement the design
#

# set proj_name and proj_dir (without updating the revision!):
set argv [list no_update_revision ]
set argc 2
source proj_properties.tcl

puts "generate bin and mcs files"
#open_run impl_1
write_cfgmem -force -format mcs -interface spix4 -size 128 -loadbit {up 0x0 fpga_elf.bit} -file fpga_elf.mcs
write_cfgmem -force -format bin -size 512 -interface spix4 -loadbit {up 0x0 fpga_elf.bit} -file fpga_elf.bin
