variables:
  GIT_SUBMODULE_STRATEGY: normal
  GIT_DEPTH: "1"
  
stages:
    - build

SPEC7_REF_DESIGN build:
  tags:
    - vitis_vivado_2019.2
  stage: build
  script:
    - /entrypoint.sh
    - source ~/setup_vivado.sh
    - git checkout proposed_master
    - git submodule init && git submodule update
    - cd hdl/wr-cores && git submodule init && git submodule update
    - cd ../../hdl/syn/spec7_ref_design
    - source /opt/Xilinx/Vivado/2019.2/settings64.sh
    - vivado -mode tcl -source ../../../sw/scripts/viv_do_all.tcl
  artifacts:
    when: always
    paths:
      - hdl/syn/spec7_ref_design/work/spec7_wr_ref_top.runs/impl_1/*.bit
      - hdl/syn/spec7_ref_design/work/spec7_wr_ref_top.runs/impl_1/*.rpt
      - hdl/syn/spec7_ref_design/work/spec7_wr_ref_top.runs/impl_1/*.csv
      - hdl/syn/spec7_ref_design/work/spec7_wr_ref_top.runs/synth_1/*.rpt
      - hdl/syn/spec7_ref_design/work/spec7_wr_ref_top.runs/processing_system_pcie_xdma_0_0_synth_1/*.rpt
      - hdl/syn/spec7_ref_design/work/spec7_wr_ref_top.runs/processing_system_pcie_processing_system7_0_0_synth_1/*.rpt
      - hdl/syn/spec7_ref_design/work/spec7_wr_ref_top.runs/processing_system_pcie_smartconnect_0_0_synth_1/*.rpt
      - hdl/syn/spec7_ref_design/work/*.bit
      - hdl/syn/spec7_ref_design/work/*.mmi
      - hdl/syn/spec7_ref_design/work/*.log
      - hdl/syn/spec7_ref_design/work/*.xsa

