set Simulation TRUE

if {$Simulation} {
    puts "Note: Simulation"
	  set g_simulation 1
	} else {
    puts "Note: Synthesis"
	  set g_simulation 0
	}

source VSim_Current_Revision.tcl

puts "elf file used for lm32 in WRPC: [set elf_file_lm32_wrpc "..\\..\\..\\sw\\embedded\\precompiled\\wrps-sw_v4_2_KPx5\\wrc.elf"]"
puts "Processor: [set lm32_wrpc_instpath "lm32_wrpc_memory"]"

# !!! Note !!!: Don't forget to compile the software (elf file) for simulation (avoid printf etc. to speed up simulation time)
# !!! Note !!!: The double \\ are there since the DOS command below needs backslashes and a single backslash is seen as a switch in tcl

# Generate a "lm32_memory.mem" file from the "elf" file content
# Note that ISE 12.4 data2mem produces wrong results; use an older version:
#exec cmd.exe /c ..\\Software\\data2mem_ise10_1\\data2mem.exe -bd $elf_file_lm32_wrpc -d -o m xil_coregen_ahbrom.mem
#exec cmd.exe /c data2mem.exe -bd $elf_file_lm32_wrpc -d -o m lm32_wrpc_memory.mem
exec cmd.exe /c updatemem -data $elf_file_lm32_wrpc -meminfo top1.smi -proc $lm32_wrpc_instpath -out lm32_wrpc_memory.mem -force

# Convert the "mem" to a "bram" (a format used by the White Rabbit "memory_loader_pkg.vhd")
do mem2bram.tcl lm32_wrpc_memory
# Now a fresh "lm32_wrpc_memory.bram" is in place for simulation and is loaded into xwb_dpram

# Note that -novopt causes No Optimization (some internal signals might get non-vivible by optimization)
# Note that "-L unisim" is needed to find the primitive "BSCANE2" thta is instantiated in "$LM32_Sources/platform/kintex7/jtag_tap.v "
#suppress warning Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value <> is not in bounds of NATURAL.
#suppress warning Warning: (vsim-8684) No drivers exist on out port <blabla>
#vsim -G/spec7_write_top/g_simulation=$g_simulation -G/spec7_write_top/g_dpram_initf=lm32_wrpc_memory.bram -t ps -L unisim -lib work work.spec7_write_top

#vsim -voptargs="+acc" -novopt \
# Note that -novopt can cause errors like:
# "Error: (vsim-8346) .../blabla.vhd(516): VHDL component port was not found because Verilog port 'D_ACK_I' was mapped to the extended identifier '\D_ACK_I\'."
# "Error: (vsim-3935) .../blabla.vhd(177): Port 'I_CYC_O' not found in the connected module."

vsim -voptargs="+acc" \
  -G/spec7_write_top/g_simulation=$g_simulation \
  -G/spec7_write_top/g_dpram_initf=lm32_wrpc_memory.bram \
  -t ps -L unisim -lib work work.spec7_write_top

do wave.tcl

do test.tcl

view signals

run 100 us

#stop

#wave zoom full

#
# End
#
