This repository contains a customized u-boot that provides support for the SPEC7 board.
The SPEC7 board is powered by a Xilinx Zynq-7000 SoC, so that it's able to operate in two different modes:
Standalone: The dual ARM Cortex-A9 in the Processing System are in charge of running an embedded Linux that acts as the host O.S.
PCIe Slave: The PCIe in the Programmable Logic acts as a bridge with the host O.S. running in the host FEC (Front End Computer).
When running in PCIe Slave, the Processing System is in charge of bringing up the SPEC7 from the on-board QSPI memory and it remains unused after startup with the only exception of future potential QSPI contents update (the QSPI can only be accessed by the Processing System).
The main mode in use at CERN is the PCIe Slave, and the main associated challenge is to be able of cold-booting different FEC computers while performing a proper enumeration of the SPEC7 card as a PCIe slave. In order to this, the PCIe root complex in the Zynq-7000 Programmable Logic needs to be properly configured in less than 100 milliseconds after power-on.
In order to fulfill this requirement, the Zynq-7000 devices PCIe IP includes a Tandem PROM mode at the time of loading a new gateware in the Programmable Logic that works in two differentiated steps:
First, the configuration for the PCIe complex is loaded so that the 100 milliseconds rule is granted.
Second, the rest of the gateware is loaded into the Programmable Logic as this can take a lot of time for big parts.
In the reference designs for the SPEC7 provided by Nikhef, the PCIe complex in the Programmable Logic is part of a more complex XDMA core that doesn't support the Tandem PROM mode. In this way, the 100 milliseconds rule for PCIe is not granted and some of the supported FECs fail to enumerate the SPEC7 board at start-up.
In order to solve this and to allow more flexibility in potential management tasks, this customized u-Boot has been created to perform a secure dual-gateware loading approach:
First, the FSBL loads a golden gateware that replicates the PCIe configuration in the XDMA based reference designs but using the Tandem PROM mode to fulfill the 100 milliseconds rule.
Second, the U-Boot binary is loaded and executed by the FSBL.
Finally, the U-Boot loads the intended reference gateware from a given location at the QSPI memory.
Clone sources from https://ohwr.org/project/spec7-ps-sw and checkout the spec7_custom branch.
Export Vitis tools so that the required cross-compilers are available in the path:
Once done, clean (just in case), load the default configuration for SPEC7 and build the u-boot.elf:
make distcleanmake zynq_spec7_defconfigmake
These are additional wiki pages containing advanced information and procedures:
Load gateware by using UBoot: how to use UBoot to update a new gateware and configure the boot procedure to implement the secure dual-gateware loading approach.
UBoot Environment in QSPI: information on how the UBoot environment is stored in QSPI, the modifications introduced to support the SPEC7 proposed QSPI layout and how to reuse a customized environment in several boards.