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Simple PCIe FMC carrier SPEC
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  • Review11052011

Review11052011

Last edited by Projects May 12, 2011
Page history

Review11052011

Review material

link

Change log (V1.1 -> V2)

  • DS18B20Z+ (IC19) footprint fixed.
  • CP2102 (IC21) footprint fixed.
  • Resetable fuses removed.
  • Fuses (the real ones that blows) added on P12V and P3V3_FMC. This implies quite some changes in the 12V routing.
  • Si570 mounted by default.
  • Si2315BDS-T1-E3 (T8) replaced by symbol from CERN lib.
  • Pull-up added on I2C bus for Si570.
  • FPGA pin P8 connected to VREF_DDR.
  • Schottky diode added in series with external 12V input, to avoid damage if an external supply is plugged when the board is in a PCIe slot.
  • Reverse polarity protection diode (D1) replaced by type SS34 (same type as series diode).
  • Number of resistor types reduced. From 23 types in V1.1 to 10 types in V2. Mostly changed regulators feedback resistors.
  • Schematics cleaned up.
  • DS18B20 package changed to uMAX, link

Comments from review

  • Fix the page numbering in the schematics.
  • Add more decoupling capacitors under the FMC connector.
  • Add text to indicate pin 1 of connectors.
  • Add all designers names
  • Fix tipo in comments (FMC connector page).
  • Connect front panel directly to GND.
  • Add more details about default boot method.
  • Verify that there's no plane under x4 PCIe lanes (should be able to cut the PCB to make a x1).
  • Add dash line to indicate the cutting point.
  • Make the FMC mounting holes all the same.
  • Fix the PCIe connector, PRSNT pads should be shorter.
  • Check VCCINT decoupling under the FPGA.
  • Consider using a smaller package for the 2.5V reference in new designs (currently SOIC8).
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