SPEC's clock test
The main idea underlying this test is comparing two free running clock domains against the expected values. If the duple of clocks falls in the validity range, the test is considered successful.
For achieving this goal two parts are needed:
VHDL core: wb_2clock_counter
This is a VHDL core which chains to counter so that the first counter can stop the count of the second one. Interfacing with the rest of the FPGA is done via wishbone. The main issue that has been tackled is focused on the interface between two different clock domains.
Python program
The python program configures the values of the chained wishbone counters and checks out the values received. Different approaches can be carried out to test the validity of the results. From a testing viewpoint, the values that can be studied are:
- Clock A nominal frequency and stability parameters
- Clock B nomimal frequency and stability parameters
- Number of clock A cycles from a starting point
- Number of clock B cycles from a starting point
- ASSERTION: Threshold test
> In this test the stability parameters are set to a known value.
- INFERENCE: Obtaining an estimation of the stability parameters
> The aim of this second type of test is infering the stability params of both clocks. To do this a least squares adjustment is done thanks to different tests carried out. The tests work by sweeping the nominal frequency of both clocks but fixing the test time. Depending whether the clock A or clock B cycles are fixed we can infere the stability parameters of the other clock.