.. SPDX-License-Identifier: CC0-1.0 SPDX-FileCopyrightText: 2019 CERN ========= Changelog ========= 2.1.4 - 2020-11-23 ================== Fixed ----- - sw: SPEC driver detects the correct FLASH only on drivers reload 2.1.3 - 2020-11-16 ================== Added ----- - sw,drv: module parameter to ignore bitstream version check (for development or debug) - sw: the spec-firmware-version tool can dump build-info Fixed ----- - hdl: DMA failures fixed with thight timing constraints 2.1.2 - 2020-11-09 ================== Fixed ----- - sw: automatize version validation 2.1.1 - 2020-11-09 ================== Fixed ----- - hdl: report the correct version in spec-golden design 2.1.0 - 2020-11-09 ================== Fixed ----- - hdl: cross-page DMA failure - sw: DMA pool memory leak - sw: fix concurrent DMA tasklet Changed ------- - tst: keep the DMA interface open while testing to avoid continuos memory re-allocation Added ----- - sw: tool to firmware version inspection - sw: FLASH partitions 2.0.2 - 2020-09-29 ================== Fixed ----- - hdl: L2P DMA issues reported with slower hosts 2.0.1 - 2020-08-20 ================== Fixed ----- - sw: program 2 or more SPEC FPGAs in parallel. There is a bug in the GN412x chip that we fixed in software by serializing any attempt of parallel programming 2.0.0 - 2020-07-30 ================== Added ----- - hdl: new testbench to test the DMA feature (read/write to DDR memory) in the new golden. - sw: basic Python module to handle DMA and FPGA programming - sw: user-space DMA interface in debugfs (read/write) - tst: add integration tests for DMA transfers Changed ------- - hdl: Switch to 125MHz (from 62.5MHz before) clock for DMA transfers. - hdl: Cleanup of top-levels, addition of DMA to the golden. Fixed ----- - hdl: DMA misalignment issue due to loss of 32-bit words, caused in turn by inadequate flow control. - hdl: typo in synthesis constraints. 1.4.15 - 2020-06-03 =================== Added ----- - hdl: ignore autogenerated files to build metadata (otherwise the repository is always marked as dirty) 1.4.14 - 2020-05-28 =================== Added ----- - hdl: export DDMTD clock output 1.4.13 - 2020-05-12 =================== Fixed ----- - hdl: report correct version in spec-base metadata 1.4.12 - 2020-05-12 =================== Added ----- - hdl: metadata source-id automatic assignment Changed ------- - sw: do not double remap memory 1.4.11 - 2020-05-04 =================== Added ----- - sw: added DMA engine channel for application to the list of resources Changed ------- - sw: little code improvements 1.4.10 - 2020-04-24 =================== Changed ------- - bld: assign dependencies path based on REPO_PARENT - bld: check for missing dependencies Fixed ----- - sw: fix kernel crash when programming new bitstream 1.4.9 - 2020-03-10 ================== Added ----- - sw: support for kernel version more recent than 3.10 (RedHat) Fixed ----- - sw: reduce allocation on stack 1.4.8 - 2020-02-12 ================== Fixed ----- - sw: fix kernel crash when programming new bitstream 1.4.7 - 2020-01-15 ================== Fixed ------- - doc: sysfs paths were wrong - doc: incomplete driver loading list of commands 1.4.6 - 2020-01-13 ================== Changed ------- - doc: improve documentation - sw: better error reporting on I2C errors 1.4.5 - 2019-12-17 ================== Something happened while synchronizing different branches and version 1.4.4 could be inconsistent on different repositories. This release increment realign all repositories 1.4.4 - 2019-12-17 ================== Changed ------- - sw: better integration in coht, rename environment variable to FPGA_MGR Fixed ----- - sw: suggested fixed reported by checkpatch and coccicheck - hdl: restore lost references to git submodules 1.4.3 - 2019-10-17 ================== Fixed ----- - sw: fix SPEC GPIO get_direction 1.4.2 - 2019-10-15 ================== Fixed ----- - sw: fix SPEC driver dependency with I2C OCores 1.4.1 - 2019-09-23 ================== Changed ------- - sw: do not used devm_* operations (it seems to solve problems) Removed ------- - sw: Removed IRQ line assignment to FCL (not used) Fixed ----- - sw: kcalloc usage - sw: memcpy(), memset() usage - sw: checkpatch style fixes 1.4.0 2019-09-11 ================ Added ----- - hdl: spec-base IP-core to support SPEC based designs - sw: Driver for GN4124 FCL using Linux FPGA manager - sw: Driver for GN4124 GPIO using Linux GPIOlib - sw: Driver for gn412x-core DMA using Linux DMA engine - sw: Support for spec-base IP-core - sw: Support for FMC 0.0.0 ===== Start the development of a new SPEC driver and SPEC HDL support layer