Simple PCIe FMC carrier SPEC issueshttps://ohwr.org/project/spec/issues2019-12-09T10:59:36Zhttps://ohwr.org/project/spec/issues/105V4 - Exposed pads IC5 and IC17 (TPS51200DRCT) not connected2019-12-09T10:59:36ZErik van der BijV4 - Exposed pads IC5 and IC17 (TPS51200DRCT) not connectedThere are four exposed pads that are there for thermal reasons, that are not foreseen to be soldered in V4. They actually should be soldered, which would need a revision of the board.
As the design has been fully functional, this change has no priority and should only be made when other PCB changes are needed.
![Before](/uploads/190482e94696c42752568659235e095e/Before.png)
**V4 design**
![After](/uploads/223f76cc9a8c9b97840e80567f69490b/After.png)
**How it should be (2 additional pads on left and right of IC17**https://ohwr.org/project/spec/issues/101Take into account simplification hints from Gennum Field Application Engineer2019-02-12T09:18:41ZErik van der BijTake into account simplification hints from Gennum Field Application EngineerTim, Applications Engineer from Gennum wrote an e-mail with several
hints that may simplify the design or make it more robust. These points
have to be taken into account for a new version of the design. See
attached mail.
### Files
* [RE_PCIe_carrier_schematics_review.txt](/uploads/8b24cccb261bbbbbf883d95ca2343665/RE_PCIe_carrier_schematics_review.txt)https://ohwr.org/project/spec/issues/67MAC address and storage2020-04-06T12:48:13ZErik van der BijMAC address and storageAs most boards will become a (WhiteRabbit) network card, it is necessary
to store at fabrication time a MAC address for each board.
\- Define where to store the MAC address (in Gennum PROM?, location?).
\- Which MAC address to use (CERN, fabricator?)
\- Where are those numbers stored and their relation to the unique ID,
barcode and others?
CERN MTF, seperate database?
\- Extend production test program to take care of the programming of the
MAC addresshttps://ohwr.org/project/spec/issues/57V4 - PCB Via annular ring size too small for IPC Class 32019-02-12T09:18:08ZErik van der BijV4 - PCB Via annular ring size too small for IPC Class 3The smallest vias have a pad size of 0.45mm and a hole size of 0.20mm.
This is outside IPC-A-600H class 3 (which is used in the PCB
specification) as it may leave a too small annular ring.
-----
According to IPC-A-600H, section 2.10.3 a minimum external annular ring
must be 0.050mm. The same can be found in IPC-2221A, section 9.1.3.
More formally, according to IPC-2221A, section 9.1.1:
Land size, minimum = a + 2b + c
- a: max diam hole;
- b: min annular ring;
- c: fabrication allowance (for c: Level C (the best one) =0.2mm)
Land size, min = 0.20 + 2\*0.05 + 0.2mm = 0.5mm. So indeed the 0.45mm we
specify is too small.
With the pad size of 0.45mm and hole size of 0.20mm, a centrally drilled
hole would leave an annular ring of 0.125mm, allowing for a 0.075mm
offset of the drill in any direction. This may be enough for the
drilling machine for small panels, but is dependent on the manufacturer
and in any case out of IPC Class 3.
-----
The design **cannot** enlarge the via pad sizes from 0.45 mm to 0.50 mm.
The clearance to other tracks would become too low.
We **cannot** reduce the hole size to 0.15mm as with the circuit of
1.6mm thickness we would approach a 1:10 aspect ratio which is too much.
Therefore we have to accept allowing Class 2 level for the annular ring
requirement for the vias with a 0.2mm hole size.
Section 9.1.2 of IPC-2221A reads:
“An annular ring shall be required for all plated-through holes in Class
3 designs. The performance specification for Class 1 and Class 2
products may allow partial hole breakouts.”
-----
\*So CERN would accept Class 2 for the annular ring requirement for the
vias with a 0.2mm hole size.
The via pad sizes cannot be enlarged, nor can the drill size be
reduced.\*
\_The acceptance of Class 2 for this feature should be specified in the
production documentation.
It would need a major redesign to allow expanding the via pad size to
0.50 mm.\_
-----https://ohwr.org/project/spec/issues/56V4 - Typo in schematic2019-02-12T09:18:08ZErik van der BijV4 - Typo in schematicPage 4: Straigth -\> Straight (near SATA connector J1)https://ohwr.org/project/spec/issues/55V4 - Still OHL 1.0 in a production doc2019-02-12T09:18:07ZErik van der BijV4 - Still OHL 1.0 in a production dochttps://edms.cern.ch/file/1158536/1/EDA-02189-V4_mfg.pdf
Drillings page marks in text OHL 1.0 instead of 1.1
Check if in other similar files too.https://ohwr.org/project/spec/issues/51V4 - Annular ring PTH for capacitors may be made larger?2019-02-12T09:18:06ZErik van der BijV4 - Annular ring PTH for capacitors may be made larger?The pin-through-holes of the OSCON capacitors (C215, C171, C193, etc),
have only a small annular ring (pad) to solder on. This pad may be too
small to be reliable.
- check if is according IPC norms
- enlarge the pad if useful.https://ohwr.org/project/spec/issues/49V4 - Move capacitor to cooler area to improve reliability2019-02-12T09:18:05ZErik van der BijV4 - Move capacitor to cooler area to improve reliabilityC193, a 150uF/16V OSCON capacitor for the +12V (on the primary side of
the 3V3, 2V5, 1V8 and 1V2 DC/DC converters), is very close to the
inductor L13 that gets relatively hot. L13 is used together with T5 to
generate 2.5V.
As temperature can affect the lifetime of this capacitor, it should be
moved further to the edge of the board where it is cooler. This will
improve the long-term reliability. Note that all DC/DC converters have
already a 10uF ceramic capacitor nearby on the primary side that is in
parallel to C193.
- Move C193 away from L13 and other inductors to increase reliability.
See attached file
### Files
* [C193onRight.GIF](/uploads/335d907aa8d4b3aa18f52d21af8f2bbd/C193onRight.GIF)https://ohwr.org/project/spec/issues/48V4 - update data for Si5702019-02-12T09:18:04ZErik van der BijV4 - update data for Si570In the BOM the Silicon Labs 570BBC000121DG is described as a generic
component without the specific startup frequency of 100 MHz mentioned.
- Replace symbol by the new one with the right data. The symbol has
already been updated in the library.
\>Part Description 10-280MHz 3.3V ±20ppm LVDS Any-Rate I2C Programmable
XO Oscillator Si570 Serie
\>Library Name ICs And Semiconductors.DbLib
\>Table Name Crystals & Oscillators
\>Part Name OSC\_10-280MHZ\_SILICON-LAB\_Si570BBC000121DGhttps://ohwr.org/project/spec/issues/45V4 - Order number of PCIe bracket not clear2019-02-12T09:18:02ZErik van der BijV4 - Order number of PCIe bracket not clearIn the [mechanical
BOM](http://edms.cern.ch/file/1158537/1/EDA-02189-V4-0_arrangement-mat.pdf)
the ordering reference of the three different elements of the bracket
are mentioned. It does not include the screws to assemble these pieces
either.
Actually one should order a single, assembled piece from [Gompf
brackets](http://www.bracket.com/) with reference \# 3200‐0479
See also [CERN's
order](https://edh.cern.ch/Document/SupplyChain/DAI/4468499) (CERN only)
- Correct EDA-02189-V4-0\_arrangement-mat filehttps://ohwr.org/project/spec/issues/43V4 - Decoupling done different than Xilinx AN2019-02-12T09:18:02ZErik van der BijV4 - Decoupling done different than Xilinx ANThe decoupling of the Xilinx is done differently than specified in the
relevant Application Note of Xilinx. Find a discussion in the attached
files.
See http://lists.ohwr.org/sympa/arc/spec/2012-05/msg00000.html and
attached file.
- Verify and confirm that decoupling is appropriate and should not be
changed.
### Files
* [Vccint_bypass.png](/uploads/412159a9a0774aa9c759867079718ebe/Vccint_bypass.png)https://ohwr.org/project/spec/issues/42V4 - Line impedances should be verified2019-02-12T09:18:01ZErik van der BijV4 - Line impedances should be verifiedINCAA made an extensive review of the impedances of the PCIe, FMC and
other lines. It seems that some impedances are out of spec. See attached
file.
- Verify the impedance of the different lines described.https://ohwr.org/project/spec/issues/38V4 - DDR3 pending End-of-life2019-02-12T09:17:59ZErik van der BijV4 - DDR3 pending End-of-lifeThe DDR3 chosen on the SPEC (same type as on the SVEC) is approaching
End-of-life.
On the Micron site MT41J128M16HA-15E has EOL
pending.
http://www.micron.com/products/dram/ddr3-sdram\#fullPart&236=1&173=2&192=1
However, the faster versions are fully in production
- MT41J128M16JT-125 (800MHz)
- MT41J128M16JT-107 (933MHz)
According to the datasheet (pages 76-77), both references are backward
compatible to the
-15E.
http://www.micron.com/~/media/Documents/Products/Data%20Sheet/DRAM/2Gb_DDR3_SDRAM.pdf
The only difference is that the package is 1mm less wide on the faster
versions.
*Recommendation**
- Replace MT41J128M16HA-15E by MT41J128M16JT-125https://ohwr.org/project/spec/issues/36V4 - 3V3 regulator resistor values wrong2019-02-12T09:17:58ZErik van der BijV4 - 3V3 regulator resistor values wrongRB wrote:
Issue with the *3.3V PSU: R242* R200 should have a resistance of
10kOhm(min) according to point 6 on page 21 of the TPS53126 datasheet.
Currently is 5K1 + 1K.
- Verify
- Correcthttps://ohwr.org/project/spec/issues/35V4 - Add LED on FPGA DONE pin2019-02-12T09:17:58ZProjectsV4 - Add LED on FPGA DONE pinAdd a LED to indicate that the FPGA is programmed.https://ohwr.org/project/spec/issues/32V4-0 - enlarge via size 450um to 550um2019-02-12T09:17:57ZErik van der BijV4-0 - enlarge via size 450um to 550umOne of the PCB manufacturers would have preferred to see the via sizes
enlarged from 450um to 550um.
It is surely possible to fabricate with 450um (they can go down to
400um), but going by 0.1mm larger would make things easier.https://ohwr.org/project/spec/issues/31V4 - Consider adding connector to supply a fan2019-02-12T09:17:57ZErik van der BijV4 - Consider adding connector to supply a fanTo allow the possibility to add a fan to cool the FMC cards, consider
adding a (standard?) connector supplying 12V or even a PWM controlled
voltage.https://ohwr.org/project/spec/issues/29V4 - Reset timing of CDCM610042019-02-12T09:17:56ZTomasz WlostowskiV4 - Reset timing of CDCM61004The CDCM61004 PLL is quite sensitive to the timing between startup of
the reference oscillator (in our case, VM53S) and the moment its VCO is
calibrated. In Issues with output incorrect PLL output frequency have
been reported by GSI (using the same PLL).
We checked our startup waveforms (see attachment), it looks like there
is about 300 us of headroom between the stabilization of reference clock
and PLL start up, so the SPEC design is likely not affected (no
incorrect PLL freq has ever been observed)
For future releases, consider changing R245 (pulldown for CDCM61004's
\\RST pin, not mounted) to a 100 nF capacitor, increasing PLL startup
lag to ~10 ms.
### Files
* [meas_spec.pdf](/uploads/9ae61547ffc512133ae435e838397118/meas_spec.pdf)https://ohwr.org/project/spec/issues/26V4 - Manage T8 from P3V3_PCIE2019-02-12T09:17:55ZProjectsV4 - Manage T8 from P3V3_PCIEComment from xavier
serra:
If the 12V power comes from J6, the net USE_EXT_12V produces a short between P3V3_PCIE and P3V3.
The short could produce a fight between the 3V3 supply from PCIe connector and the FPGA 3V3 supply,
maybe the power supplies are protected against reverse voltatge (I haven't checked yet),
but maybe is more interesting if the control of T8 MOSFET is managed from P3V3_PCIE net.
If there is 3V3 volts in P3V3_PCIE, the T8 is open. If there is no 3V3 volts,
T8 is closed(shorted) with the help of a pull down resitor on P3V3_PCIE net.
This issue has been raised when trying to use the SPEC board with
miniPCIe (that doesn't supply 12V).https://ohwr.org/project/spec/issues/25V4 - Automatic 1x PCIe2019-02-12T09:17:55ZProjectsV4 - Automatic 1x PCIeComment from xavier
serra:
According to SPEC schematics page 13. To use 1x PCIe should be at 3V3 volts.
I propose to connect R149 not directly to GND, but at pin b32 of J2 and
mount R139 (values of resistors should be recalculated). In this way if there
is no GND on b32 the GN4124 is automatically configured as 1x. In the same way
it should generated automatic a short in connector J2 between pins b17 and a1 (for card detection).