Simple PCIe FMC carrier SPEC issueshttps://ohwr.org/project/spec/issues2019-12-09T10:59:36Zhttps://ohwr.org/project/spec/issues/105V4 - Exposed pads IC5 and IC17 (TPS51200DRCT) not connected2019-12-09T10:59:36ZErik van der BijV4 - Exposed pads IC5 and IC17 (TPS51200DRCT) not connectedThere are four exposed pads that are there for thermal reasons, that are not foreseen to be soldered in V4. They actually should be soldered, which would need a revision of the board.
As the design has been fully functional, this change has no priority and should only be made when other PCB changes are needed.
![Before](/uploads/190482e94696c42752568659235e095e/Before.png)
**V4 design**
![After](/uploads/223f76cc9a8c9b97840e80567f69490b/After.png)
**How it should be (2 additional pads on left and right of IC17**https://ohwr.org/project/spec/issues/1V4 - SFP cage type is obsolete, EOL2019-02-12T09:17:46ZErik van der BijV4 - SFP cage type is obsolete, EOLThe two-piece SFP Cage from Tyco Electronics
([6367034-1](http://www.te.com/usa-en/search.html?q=6367034-1) and
[6367035-1](http://www.te.com/usa-en/search.html?q=6367035-1)) is at
End-of-Life (EOL).
The supplier suggests the use of the one-piece solution
[2227303-3](http://www.te.com/usa-en/product-2227303-3.html).
-----
This solution will be used (with agreement from CERN) for new
productions of the SVEC by JanzTec from January 2018 on.
*Reported by JanzTec on 22/1/18.*https://ohwr.org/project/spec/issues/2Panel fiducials have offset2022-11-08T17:07:26ZErik van der BijPanel fiducials have offsetISD found the issue that the fiducials on the PCB and soldermask have an
offset.
The provided gerber file for the PCB panel (here attached) has 3 diamond
shaped fiducials on each side of the panel. The issue is that the XY
coordinates of the fiducials does not match the dimensions written on
the panel:
- Fiducial 1 : X 7.5 Y 25.0
- Fiducial 2 : X 7.5 Y 218.9
- Fiducial 3 : X 198.2 Y 25.0
In cooperation with our PCB manufacturer the correct alignment has been
achieved by following the written dimensions and not the gerber data for
the fiducials; otherwise an offset is introduced. The PCB panel has been
manufactured by following the written dimensions.
-----
See also attached file.
### Files
* [EDA-02189-V4_fiducials.jpg](/uploads/3f7c4226acf9d335fceb1ec790a5e214/EDA-02189-V4_fiducials.jpg)https://ohwr.org/project/spec/issues/4V4 - Package type D1,D2 wrongly mentioned in BOM. Partnumber OK.2022-11-09T13:11:50ZErik van der BijV4 - Package type D1,D2 wrongly mentioned in BOM. Partnumber OK.The following component has in the BOM a wrong package type in the
column "Case".
- Reference: D1, D2
- 40V 3A Surface Mount Schottky Barrier Rectifier
- FAIRCHILD SEMICONDUCTOR SS34
The package type mentioned in the BOM is DO-214AC.
Actually, the footprint is a DO-214AB, as it the footprint of the actual
SS34 component.
This issue has been signalled to the CERN design office who have
corrected the field in the library (but not in the BOM of the SPEC).
[Datasheet of
SS34](http://www.onsemi.com/PowerSolutions/product.do?id=SS34)
-----
Issue found by ISD.
Verified by Erik.
-----
Reply from design office when signalled:
C’est une erreur dans le champ « Case » de la base de donnée Access.
Cette information n’a aucune conséquence sur l’empreinte PCB, elle est
donnée à titre indicatif. L’empreinte réelle est bien celle d’une
DO-214AB et non DO-214AC. J’ai donc juste corrigé ce champ.https://ohwr.org/project/spec/issues/11V4 - front-panel drawing does not show licenced under CERN OHL.2023-01-19T13:30:42ZErik van der BijV4 - front-panel drawing does not show licenced under CERN OHL.See
https://www.ohwr.org/project/spec/wikis/FAQ\#Q-can-I-use-the-front-panel-drawings-for-other-purposeshttps://ohwr.org/project/spec/issues/15V4 - Note on DAC output range wrong2019-02-15T15:47:22ZErik van der BijV4 - Note on DAC output range wrongPage 2 of the schematics shows a note stating "DAC output range: 0V to
2.5V".
It should read: "DAC output range: 0V to 2.27V".
The DACs use a reference voltage Vref created by the LM336M-2.5/NOPB
(IC10). The DAC output maximum is the same as Vref.
As the ADJ pin of the LM336M is connected to ground, the output voltage
is typically 120mV lower than nominal (datasheet, Fig.1). The "Reverse
Breakdown Voltage" (the output level) can be as low as 2.39V when coming
out of the factory. Combined with the adjustment input set to 0V, the
final output level may be as low as 2.39-0.12=2.27V, which gives the
maximum level of the DAC output.
Actually it is a design error (Vadj should have been left open). We do
not want to change this anymore as there are so many designs based on
this design (SVEC, SPEXI, WR reference schematics etc.) and we don't
want to have any different versions around. The White Rabbit core can
handle this limited range, if taken correctly care (i.e. to set the base
frequency of the VCXO behind it so that the DAC voltage is around in the
middle of the range 0-2.27V). Notably at a high temperature (\>50C), the
DAC voltage was reaching the high level of this range, resulting that it
could not follow the WR clock and unlocked. This will be taken care of
in the WR core from V3.0 on.
Thanks INCAA for having found this\!
### Files
* [DAC.png](/uploads/a01541c88cec8aae2cd53d5deb67728f/DAC.png)
* [lm336-2.5-n.pdf](/uploads/1f3da8c0eae3f3791108f78eb0b7dcf3/lm336-2.5-n.pdf)https://ohwr.org/project/spec/issues/18V4 - consider adding a header with power and user-defined FPGA pins.2023-07-24T06:45:18ZTomasz WlostowskiV4 - consider adding a header with power and user-defined FPGA pins.If there ever is going to be an update of the Spec board it would be
nice if it had a connector (say right angle 20 pins 2.54mm dual row)
with the 12V power supply, ground and some FPGA pins. This would allow
the Spec board to be integrated into stand alone products more easely
(and connect a fan without soldering to the board).https://ohwr.org/project/spec/issues/19PTS: timing violation in DAC signal.2023-08-24T15:22:37ZErik van der BijPTS: timing violation in DAC signal.A timing problem has been discovered in the PTS of the SVEC.
Likely this problem exists also in the PTS of the SPEC.
*"The PTS test used for the SVEC/SPEC board changes DAC DIN signal at
exactly the falling SCLK edge. Therefore, it violates the timing
conditions indicated in the datasheet (setup time=5ns and hold
time=4.5ns)"*
Problem not urgent as the PTS basically only has to check if every
solder connection is correctly done, even with the problem present, it
will detect if the DAC would not be correctly connected.
See [SPEC Feature \#992](https://www.ohwr.org/issue/992) for details.https://ohwr.org/project/spec/issues/20V4 - consider placing fan instead of the cutout under FMC2023-10-13T07:29:45ZTomasz WlostowskiV4 - consider placing fan instead of the cutout under FMCThe cutout under the FMC is in many cases insufficient to cool the
mezzanine. We designed a custom fan for the SPEC (see
https://www.ohwr.org/project/fmc-delay-1ns-8cha/wikis/Heatsinks). A
future version of the SPEC could support mounting an off-the-shelf fan
instead of additional PCB under the FMC.https://ohwr.org/project/spec/issues/22V4 - Make hardwired PLL settings configurable2024-03-22T16:09:47ZErik van der BijV4 - Make hardwired PLL settings configurableFor certain applications it would be good if the hardwired PLL
parameters can be set differently. It is fixed to x5 (output 125 MHz).
Some applications (e.g CERN BE/BI) may need other settings, like x4
(output 100 MHz).
This currently can be done by adding or removing some 0 Ohm resistors
\[1\], but this needs hardware changes and may give problems with stock
management.
It is suggested to make the PLL settings configurable under program
control.
It would be nice if this could be backwards compatible (e.g. power-on
setting the same as current design).
\[1\]
[Schematics](https://edms.cern.ch/file/1158532/1/EDA-02189-V4-0_sch.pdf)
page 2 top-right, resistors connected to IC6.
-----
Additional info:
Q: Why not use the Si571 to make the 100 MHz?
A: Unfortunately the SI571 does not drive a GTP ref clk input. There is
a way to source the GTP ref clk via a GCLK net, but this does not work
well at 2.5Gbps due to the increased jitter. We were seeing ~1 PRBS
error per day when using the GCLK routing.
The only choice for the SFP GTP is to use the VCXO as the ref clk and to
support our non standard 1.0Gbps and 2.0Gbps line rates from 125MHz is
not possible.https://ohwr.org/project/spec/issues/25V4 - Automatic 1x PCIe2019-02-12T09:17:55ZProjectsV4 - Automatic 1x PCIeComment from xavier
serra:
According to SPEC schematics page 13. To use 1x PCIe should be at 3V3 volts.
I propose to connect R149 not directly to GND, but at pin b32 of J2 and
mount R139 (values of resistors should be recalculated). In this way if there
is no GND on b32 the GN4124 is automatically configured as 1x. In the same way
it should generated automatic a short in connector J2 between pins b17 and a1 (for card detection).https://ohwr.org/project/spec/issues/26V4 - Manage T8 from P3V3_PCIE2019-02-12T09:17:55ZProjectsV4 - Manage T8 from P3V3_PCIEComment from xavier
serra:
If the 12V power comes from J6, the net USE_EXT_12V produces a short between P3V3_PCIE and P3V3.
The short could produce a fight between the 3V3 supply from PCIe connector and the FPGA 3V3 supply,
maybe the power supplies are protected against reverse voltatge (I haven't checked yet),
but maybe is more interesting if the control of T8 MOSFET is managed from P3V3_PCIE net.
If there is 3V3 volts in P3V3_PCIE, the T8 is open. If there is no 3V3 volts,
T8 is closed(shorted) with the help of a pull down resitor on P3V3_PCIE net.
This issue has been raised when trying to use the SPEC board with
miniPCIe (that doesn't supply 12V).https://ohwr.org/project/spec/issues/29V4 - Reset timing of CDCM610042019-02-12T09:17:56ZTomasz WlostowskiV4 - Reset timing of CDCM61004The CDCM61004 PLL is quite sensitive to the timing between startup of
the reference oscillator (in our case, VM53S) and the moment its VCO is
calibrated. In Issues with output incorrect PLL output frequency have
been reported by GSI (using the same PLL).
We checked our startup waveforms (see attachment), it looks like there
is about 300 us of headroom between the stabilization of reference clock
and PLL start up, so the SPEC design is likely not affected (no
incorrect PLL freq has ever been observed)
For future releases, consider changing R245 (pulldown for CDCM61004's
\\RST pin, not mounted) to a 100 nF capacitor, increasing PLL startup
lag to ~10 ms.
### Files
* [meas_spec.pdf](/uploads/9ae61547ffc512133ae435e838397118/meas_spec.pdf)https://ohwr.org/project/spec/issues/31V4 - Consider adding connector to supply a fan2019-02-12T09:17:57ZErik van der BijV4 - Consider adding connector to supply a fanTo allow the possibility to add a fan to cool the FMC cards, consider
adding a (standard?) connector supplying 12V or even a PWM controlled
voltage.https://ohwr.org/project/spec/issues/32V4-0 - enlarge via size 450um to 550um2019-02-12T09:17:57ZErik van der BijV4-0 - enlarge via size 450um to 550umOne of the PCB manufacturers would have preferred to see the via sizes
enlarged from 450um to 550um.
It is surely possible to fabricate with 450um (they can go down to
400um), but going by 0.1mm larger would make things easier.https://ohwr.org/project/spec/issues/35V4 - Add LED on FPGA DONE pin2019-02-12T09:17:58ZProjectsV4 - Add LED on FPGA DONE pinAdd a LED to indicate that the FPGA is programmed.https://ohwr.org/project/spec/issues/36V4 - 3V3 regulator resistor values wrong2019-02-12T09:17:58ZErik van der BijV4 - 3V3 regulator resistor values wrongRB wrote:
Issue with the *3.3V PSU: R242* R200 should have a resistance of
10kOhm(min) according to point 6 on page 21 of the TPS53126 datasheet.
Currently is 5K1 + 1K.
- Verify
- Correcthttps://ohwr.org/project/spec/issues/38V4 - DDR3 pending End-of-life2019-02-12T09:17:59ZErik van der BijV4 - DDR3 pending End-of-lifeThe DDR3 chosen on the SPEC (same type as on the SVEC) is approaching
End-of-life.
On the Micron site MT41J128M16HA-15E has EOL
pending.
http://www.micron.com/products/dram/ddr3-sdram\#fullPart&236=1&173=2&192=1
However, the faster versions are fully in production
- MT41J128M16JT-125 (800MHz)
- MT41J128M16JT-107 (933MHz)
According to the datasheet (pages 76-77), both references are backward
compatible to the
-15E.
http://www.micron.com/~/media/Documents/Products/Data%20Sheet/DRAM/2Gb_DDR3_SDRAM.pdf
The only difference is that the package is 1mm less wide on the faster
versions.
*Recommendation**
- Replace MT41J128M16HA-15E by MT41J128M16JT-125https://ohwr.org/project/spec/issues/42V4 - Line impedances should be verified2019-02-12T09:18:01ZErik van der BijV4 - Line impedances should be verifiedINCAA made an extensive review of the impedances of the PCIe, FMC and
other lines. It seems that some impedances are out of spec. See attached
file.
- Verify the impedance of the different lines described.https://ohwr.org/project/spec/issues/43V4 - Decoupling done different than Xilinx AN2019-02-12T09:18:02ZErik van der BijV4 - Decoupling done different than Xilinx ANThe decoupling of the Xilinx is done differently than specified in the
relevant Application Note of Xilinx. Find a discussion in the attached
files.
See http://lists.ohwr.org/sympa/arc/spec/2012-05/msg00000.html and
attached file.
- Verify and confirm that decoupling is appropriate and should not be
changed.
### Files
* [Vccint_bypass.png](/uploads/412159a9a0774aa9c759867079718ebe/Vccint_bypass.png)