Simple PCIe FMC carrier SPEC issueshttps://ohwr.org/project/spec/issues2024-03-22T16:09:47Zhttps://ohwr.org/project/spec/issues/22V4 - Make hardwired PLL settings configurable2024-03-22T16:09:47ZErik van der BijV4 - Make hardwired PLL settings configurableFor certain applications it would be good if the hardwired PLL
parameters can be set differently. It is fixed to x5 (output 125 MHz).
Some applications (e.g CERN BE/BI) may need other settings, like x4
(output 100 MHz).
This currently can be done by adding or removing some 0 Ohm resistors
\[1\], but this needs hardware changes and may give problems with stock
management.
It is suggested to make the PLL settings configurable under program
control.
It would be nice if this could be backwards compatible (e.g. power-on
setting the same as current design).
\[1\]
[Schematics](https://edms.cern.ch/file/1158532/1/EDA-02189-V4-0_sch.pdf)
page 2 top-right, resistors connected to IC6.
-----
Additional info:
Q: Why not use the Si571 to make the 100 MHz?
A: Unfortunately the SI571 does not drive a GTP ref clk input. There is
a way to source the GTP ref clk via a GCLK net, but this does not work
well at 2.5Gbps due to the increased jitter. We were seeing ~1 PRBS
error per day when using the GCLK routing.
The only choice for the SFP GTP is to use the VCXO as the ref clk and to
support our non standard 1.0Gbps and 2.0Gbps line rates from 125MHz is
not possible.https://ohwr.org/project/spec/issues/20V4 - consider placing fan instead of the cutout under FMC2023-10-13T07:29:45ZTomasz WlostowskiV4 - consider placing fan instead of the cutout under FMCThe cutout under the FMC is in many cases insufficient to cool the
mezzanine. We designed a custom fan for the SPEC (see
https://www.ohwr.org/project/fmc-delay-1ns-8cha/wikis/Heatsinks). A
future version of the SPEC could support mounting an off-the-shelf fan
instead of additional PCB under the FMC.https://ohwr.org/project/spec/issues/19PTS: timing violation in DAC signal.2023-08-24T15:22:37ZErik van der BijPTS: timing violation in DAC signal.A timing problem has been discovered in the PTS of the SVEC.
Likely this problem exists also in the PTS of the SPEC.
*"The PTS test used for the SVEC/SPEC board changes DAC DIN signal at
exactly the falling SCLK edge. Therefore, it violates the timing
conditions indicated in the datasheet (setup time=5ns and hold
time=4.5ns)"*
Problem not urgent as the PTS basically only has to check if every
solder connection is correctly done, even with the problem present, it
will detect if the DAC would not be correctly connected.
See [SPEC Feature \#992](https://www.ohwr.org/issue/992) for details.https://ohwr.org/project/spec/issues/18V4 - consider adding a header with power and user-defined FPGA pins.2023-07-24T06:45:18ZTomasz WlostowskiV4 - consider adding a header with power and user-defined FPGA pins.If there ever is going to be an update of the Spec board it would be
nice if it had a connector (say right angle 20 pins 2.54mm dual row)
with the 12V power supply, ground and some FPGA pins. This would allow
the Spec board to be integrated into stand alone products more easely
(and connect a fan without soldering to the board).https://ohwr.org/project/spec/issues/15V4 - Note on DAC output range wrong2019-02-15T15:47:22ZErik van der BijV4 - Note on DAC output range wrongPage 2 of the schematics shows a note stating "DAC output range: 0V to
2.5V".
It should read: "DAC output range: 0V to 2.27V".
The DACs use a reference voltage Vref created by the LM336M-2.5/NOPB
(IC10). The DAC output maximum is the same as Vref.
As the ADJ pin of the LM336M is connected to ground, the output voltage
is typically 120mV lower than nominal (datasheet, Fig.1). The "Reverse
Breakdown Voltage" (the output level) can be as low as 2.39V when coming
out of the factory. Combined with the adjustment input set to 0V, the
final output level may be as low as 2.39-0.12=2.27V, which gives the
maximum level of the DAC output.
Actually it is a design error (Vadj should have been left open). We do
not want to change this anymore as there are so many designs based on
this design (SVEC, SPEXI, WR reference schematics etc.) and we don't
want to have any different versions around. The White Rabbit core can
handle this limited range, if taken correctly care (i.e. to set the base
frequency of the VCXO behind it so that the DAC voltage is around in the
middle of the range 0-2.27V). Notably at a high temperature (\>50C), the
DAC voltage was reaching the high level of this range, resulting that it
could not follow the WR clock and unlocked. This will be taken care of
in the WR core from V3.0 on.
Thanks INCAA for having found this\!
### Files
* [DAC.png](/uploads/a01541c88cec8aae2cd53d5deb67728f/DAC.png)
* [lm336-2.5-n.pdf](/uploads/1f3da8c0eae3f3791108f78eb0b7dcf3/lm336-2.5-n.pdf)https://ohwr.org/project/spec/issues/11V4 - front-panel drawing does not show licenced under CERN OHL.2023-01-19T13:30:42ZErik van der BijV4 - front-panel drawing does not show licenced under CERN OHL.See
https://www.ohwr.org/project/spec/wikis/FAQ\#Q-can-I-use-the-front-panel-drawings-for-other-purposeshttps://ohwr.org/project/spec/issues/4V4 - Package type D1,D2 wrongly mentioned in BOM. Partnumber OK.2022-11-09T13:11:50ZErik van der BijV4 - Package type D1,D2 wrongly mentioned in BOM. Partnumber OK.The following component has in the BOM a wrong package type in the
column "Case".
- Reference: D1, D2
- 40V 3A Surface Mount Schottky Barrier Rectifier
- FAIRCHILD SEMICONDUCTOR SS34
The package type mentioned in the BOM is DO-214AC.
Actually, the footprint is a DO-214AB, as it the footprint of the actual
SS34 component.
This issue has been signalled to the CERN design office who have
corrected the field in the library (but not in the BOM of the SPEC).
[Datasheet of
SS34](http://www.onsemi.com/PowerSolutions/product.do?id=SS34)
-----
Issue found by ISD.
Verified by Erik.
-----
Reply from design office when signalled:
C’est une erreur dans le champ « Case » de la base de donnée Access.
Cette information n’a aucune conséquence sur l’empreinte PCB, elle est
donnée à titre indicatif. L’empreinte réelle est bien celle d’une
DO-214AB et non DO-214AC. J’ai donc juste corrigé ce champ.https://ohwr.org/project/spec/issues/2Panel fiducials have offset2022-11-08T17:07:26ZErik van der BijPanel fiducials have offsetISD found the issue that the fiducials on the PCB and soldermask have an
offset.
The provided gerber file for the PCB panel (here attached) has 3 diamond
shaped fiducials on each side of the panel. The issue is that the XY
coordinates of the fiducials does not match the dimensions written on
the panel:
- Fiducial 1 : X 7.5 Y 25.0
- Fiducial 2 : X 7.5 Y 218.9
- Fiducial 3 : X 198.2 Y 25.0
In cooperation with our PCB manufacturer the correct alignment has been
achieved by following the written dimensions and not the gerber data for
the fiducials; otherwise an offset is introduced. The PCB panel has been
manufactured by following the written dimensions.
-----
See also attached file.
### Files
* [EDA-02189-V4_fiducials.jpg](/uploads/3f7c4226acf9d335fceb1ec790a5e214/EDA-02189-V4_fiducials.jpg)https://ohwr.org/project/spec/issues/1V4 - SFP cage type is obsolete, EOL2019-02-12T09:17:46ZErik van der BijV4 - SFP cage type is obsolete, EOLThe two-piece SFP Cage from Tyco Electronics
([6367034-1](http://www.te.com/usa-en/search.html?q=6367034-1) and
[6367035-1](http://www.te.com/usa-en/search.html?q=6367035-1)) is at
End-of-Life (EOL).
The supplier suggests the use of the one-piece solution
[2227303-3](http://www.te.com/usa-en/product-2227303-3.html).
-----
This solution will be used (with agreement from CERN) for new
productions of the SVEC by JanzTec from January 2018 on.
*Reported by JanzTec on 22/1/18.*