Commits · master · Projects / Simple PCIe FMC carrier SPEC

29 Sep, 2020 2 commits
- hdl: update version info in metadata · d61a87e8
  Dimitris Lampridis authored Sep 29, 2020
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Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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  d61a87e8
- hdl: import L2P DMA bugfix from gn4124 · 44042300
  Dimitris Lampridis authored Sep 29, 2020
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Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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  44042300
30 Jul, 2020 1 commit
- hdl|sw: update spec-base version for next release · 94bf3e4e
  Federico Vaga authored Jul 30, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  94bf3e4e
28 Jul, 2020 9 commits
- hdl: introduce golden-100T and golden-150T · 9288616d
  Dimitris Lampridis authored Jul 28, 2020
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Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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  9288616d
- hdl: remove golden_wr-150T, not used anymore. · a399b0fc
  Dimitris Lampridis authored Jul 28, 2020
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Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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  a399b0fc
- hdl: rename golden_wr top to spec_base_wr_example and clean-up. · 907cc696
  Dimitris Lampridis authored Jul 28, 2020
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Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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  907cc696
- hdl: rename dma_test testbench to golden. · 398dc356
  Dimitris Lampridis authored Jul 28, 2020
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Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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  398dc356
- hdl: rename golden to golden-45T. · cb256101
  Dimitris Lampridis authored Jul 28, 2020
  
  cb256101
- hdl: remove "full" top-level, not used anymore. · 659f3d8f
  Dimitris Lampridis authored Jul 28, 2020
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Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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  659f3d8f
- hdl: make dma_test testbench use the golden top-level. · bddf0f2c
  Dimitris Lampridis authored Jul 28, 2020
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Also remove the dma_test top-level, not used anymore.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
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  bddf0f2c
- hdl: re-define and clean-up golden to also include DDR3. · 7051bce9
  Dimitris Lampridis authored Jul 28, 2020
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Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
```
  7051bce9
- hdl: add default value to app_wb_i port when not connected. · 13368245
  Dimitris Lampridis authored Jul 28, 2020
  
  13368245
27 Jul, 2020 2 commits
- hdl: fix DMA clock to 125MHz · f2dfe5de
  Dimitris Lampridis authored Jul 24, 2020
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Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
```
  f2dfe5de
- hdl: bump submodules to get latest releases · 682da324
  Dimitris Lampridis authored Jul 24, 2020
  
  682da324
24 Jul, 2020 4 commits
- hdl: Fix correct location for gen_sourceid.py script. · 15e93834
  Dimitris Lampridis authored Jul 13, 2020
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Depending on whether spec is a submodule of another project or a standalone project.
```
  15e93834
- hdl: introduce simplified top-level for DMA testing and update testbench · 8fbf7438
  Dimitris Lampridis authored Jun 29, 2020
  
  8fbf7438
- syn: constraints path correction · 90be31a5
  Evangelia Gousiou authored Jun 15, 2020
  
  90be31a5
- hdl: introduce DDR DMA testbench · 025c2a5d
  Dimitris Lampridis authored Jun 25, 2020
  
  025c2a5d
03 Jun, 2020 1 commit
- Add .gitignore in hdl/rtl · ceea4f72
  Tristan Gingold authored Jun 03, 2020
  
  ceea4f72
28 May, 2020 3 commits
- syn: updated common constraints file for conditional compilation of gn4124_core · e79126f1
  Tomasz Wlostowski authored May 25, 2020
  
  e79126f1
- hdl/spec_base_wr: tie sim_wb_i to 0s when not used · 5861d188
  Tomasz Wlostowski authored May 19, 2020
  
  5861d188
- hdl: add generic to bypass gennum core in simulations · 8bbdf20f
  Tomasz Wlostowski authored May 13, 2020
  
  8bbdf20f
13 May, 2020 1 commit
- spec_base_wr: added DDMTD clock output · 6289836d
  Tomasz Wlostowski authored Oct 22, 2019
  
  6289836d
12 May, 2020 3 commits
- hdl: fix version (hex format) · fafa7335
  Federico Vaga authored May 12, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  fafa7335
- hdl: update version in spec-base IP-core · 4a9afbe5
  Federico Vaga authored May 12, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  4a9afbe5
- Bump spec_base version to 1.4.11 in metadata. · 403bd9af
  Tristan Gingold authored May 12, 2020
  
  403bd9af
11 May, 2020 1 commit
- Add source id generation. · 66afdd28
  Tristan Gingold authored May 11, 2020
  
  66afdd28
04 Mar, 2020 2 commits

[hdl] remove self-refresh timing constraint from DDR, feature not enabled · 266a209c
Dimitris Lampridis authored Mar 04, 2020
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Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
```
266a209c

[hdl] fix DDR controller string "TRUE"/"FALSE" settings · 94946d75

Dimitris Lampridis authored Mar 04, 2020

The issue comes from the fact that boolean'image() returns lowercase "true"/"false" strings, which
are then not properly matched by the DDR controller core. To fix this, we pull the to_upper()
function from general-cores and use it to convert the output of bolean'image() to uppercase before
passing it to the DDR controller.
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

94946d75

25 Oct, 2019 1 commit
- [hdl] restore lost references to git submodules · 08df32bd
  Dimitris Lampridis authored Oct 25, 2019
  
  08df32bd
23 Sep, 2019 1 commit
- spec_base_wr: automatically set the g_BANK_PORT_SELECT generic. · d5576038
  Tristan Gingold authored Sep 18, 2019
  
  d5576038
06 Sep, 2019 2 commits
- Remove unused spec_full.ucf · 1b48d764
  Tristan Gingold authored Sep 06, 2019
  
  1b48d764
- spec_base: add g_DDR_DATA_SIZE. · 1e8eacfe
  Tristan Gingold authored Sep 06, 2019
  
  1e8eacfe
04 Sep, 2019 4 commits
- Adjust full design. · a347c6df
  Tristan Gingold authored Sep 04, 2019
  
  a347c6df
- Rename template to base. · 818b4c37
  Tristan Gingold authored Sep 04, 2019
  
  818b4c37
- adjust ucf and goldens. · 798a6866
  Tristan Gingold authored Sep 04, 2019
  
  798a6866
- spec template: support aux clocks, rename clock signals · 41d53adb
  Tristan Gingold authored Sep 04, 2019
```
Also change g_simulation type.
```
  41d53adb
26 Aug, 2019 1 commit
- update golden: use common ucfs. · 778af94f
  Tristan Gingold authored Aug 26, 2019
  
  778af94f
06 Aug, 2019 1 commit
- repo: move hdl code to top level directory · cd150b30
  Federico Vaga authored Aug 06, 2019
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
```
  cd150b30
02 Aug, 2019 1 commit
- [hdl] rework synthesis constraints · 7ebae5ae
  Dimitris Lampridis authored Aug 02, 2019
  
  7ebae5ae