- 30 Jul, 2020 1 commit
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Dimitris Lampridis authored
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- 28 Jul, 2020 9 commits
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Dimitris Lampridis authored
Signed-off-by:
Dimitris Lampridis <dimitris.lampridis@cern.ch>
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Dimitris Lampridis authored
Signed-off-by:
Dimitris Lampridis <dimitris.lampridis@cern.ch>
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Dimitris Lampridis authored
Signed-off-by:
Dimitris Lampridis <dimitris.lampridis@cern.ch>
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Dimitris Lampridis authored
Signed-off-by:
Dimitris Lampridis <dimitris.lampridis@cern.ch>
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Dimitris Lampridis authored
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Dimitris Lampridis authored
Signed-off-by:
Dimitris Lampridis <dimitris.lampridis@cern.ch>
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Dimitris Lampridis authored
Also remove the dma_test top-level, not used anymore. Signed-off-by:
Dimitris Lampridis <dimitris.lampridis@cern.ch>
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Dimitris Lampridis authored
Signed-off-by:
Dimitris Lampridis <dimitris.lampridis@cern.ch>
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Dimitris Lampridis authored
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- 27 Jul, 2020 3 commits
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Dimitris Lampridis authored
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Dimitris Lampridis authored
Signed-off-by:
Dimitris Lampridis <dimitris.lampridis@cern.ch>
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Dimitris Lampridis authored
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- 24 Jul, 2020 4 commits
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Dimitris Lampridis authored
Depending on whether spec is a submodule of another project or a standalone project.
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Dimitris Lampridis authored
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Evangelia Gousiou authored
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Dimitris Lampridis authored
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- 13 Jul, 2020 1 commit
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Federico Vaga authored
Signed-off-by:
Federico Vaga <federico.vaga@cern.ch>
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- 08 Jul, 2020 4 commits
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Federico Vaga authored
Signed-off-by:
Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by:
Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by:
Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by:
Federico Vaga <federico.vaga@cern.ch>
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- 06 Jul, 2020 5 commits
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Federico Vaga authored
Signed-off-by:
Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by:
Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by:
Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by:
Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
The HDL asserts the IRQ line before the end of a write to DDR transfer. We can't fix the problem on HDL due to lack of resources, so we add a 5us (empirical tests) delay in software. Signed-off-by:
Federico Vaga <federico.vaga@cern.ch>
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- 02 Jul, 2020 8 commits
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Federico Vaga authored
Signed-off-by:
Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
No limites for read, but the implementation is not symmetric. For DMA_MEM_TO_DEV the transfer size limitation is 4096. Signed-off-by:
Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
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Federico Vaga authored
Signed-off-by:
Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
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Federico Vaga authored
Signed-off-by:
Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Problem: sometimes a 4Byte transfers corrupt the gennum chip Signed-off-by:
Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Problem: after Xbytes the DMA read returns only zeros. This happens at a power-of-two offset, typically below 1024 Signed-off-by:
Federico Vaga <federico.vaga@cern.ch>
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- 01 Jul, 2020 2 commits
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Federico Vaga authored
Signed-off-by:
Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by:
Federico Vaga <federico.vaga@cern.ch>
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- 30 Jun, 2020 3 commits
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Federico Vaga authored
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Federico Vaga authored
Signed-off-by:
Federico Vaga <federico.vaga@cern.ch>
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Federico Vaga authored
Signed-off-by:
Federico Vaga <federico.vaga@cern.ch>
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