Commit fffa8b42 authored by Federico Vaga's avatar Federico Vaga

Merge branch 'release/v2.1.5'

parents fd485c8b ee786de1
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
*.o
*.ko
*.mod.c
......@@ -16,3 +20,4 @@ GPATH
GRTAGS
Makefile.specific
compile_commands.json
.clangd
\ No newline at end of file
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
[submodule "hdl/ip_cores/wr-cores"]
path = hdl/ip_cores/wr-cores
url = https://ohwr.org/project/wr-cores.git
......
# .readthedocs.yml
# Read the Docs configuration file
# See https://docs.readthedocs.io/en/stable/config-file/v2.html for details
# Required
version: 2
# Build documentation in the docs/ directory with Sphinx
sphinx:
configuration: doc/conf.py
# Build documentation with MkDocs
#mkdocs:
# configuration: mkdocs.yml
# Optionally build your docs in additional formats such as PDF and ePub
formats:
- pdf
# Optionally set the version of Python and requirements required to build your docs
python:
version: 3.7
install:
- requirements: doc/requirements.txt
# Exclude all submodules, they are not needed for documentation
submodules:
exclude: all
Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/
Upstream-Name: SPEC
Upstream-Contact: Federico Vaga <federico.vaga@cern.ch>
Source: https://ohwr.org/project/spec/
Files: doc/requirements.txt
Copyright: 2020 CERN (home.cern)
License: CC0-1.0
......@@ -6,6 +6,13 @@
Changelog
=========
2.1.5 - 2021-05-18
==================
Fixed
-----
- sw: check if FPGA is programmed before loading FPGA devices
- doc: improve documentation
2.1.4 - 2020-11-23
==================
Fixed
......
CERN-OHL-W-2.0.txt
\ No newline at end of file
CERN Open Hardware Licence Version 2 - Weakly Reciprocal
Preamble
CERN has developed this licence to promote collaboration among
hardware designers and to provide a legal tool which supports the
freedom to use, study, modify, share and distribute hardware designs
and products based on those designs. Version 2 of the CERN Open
Hardware Licence comes in three variants: CERN-OHL-P (permissive); and
two reciprocal licences: this licence, CERN-OHL-W (weakly reciprocal)
and CERN-OHL-S (strongly reciprocal).
The CERN-OHL-W is copyright CERN 2020. Anyone is welcome to use it, in
unmodified form only.
Use of this Licence does not imply any endorsement by CERN of any
Licensor or their designs nor does it imply any involvement by CERN in
their development.
1 Definitions
1.1 'Licence' means this CERN-OHL-W.
1.2 'Compatible Licence' means
a) any earlier version of the CERN Open Hardware licence, or
b) any version of the CERN-OHL-S or the CERN-OHL-W, or
c) any licence which permits You to treat the Source to which
it applies as licensed under CERN-OHL-S or CERN-OHL-W
provided that on Conveyance of any such Source, or any
associated Product You treat the Source in question as being
licensed under CERN-OHL-S or CERN-OHL-W as appropriate.
1.3 'Source' means information such as design materials or digital
code which can be applied to Make or test a Product or to
prepare a Product for use, Conveyance or sale, regardless of its
medium or how it is expressed. It may include Notices.
1.4 'Covered Source' means Source that is explicitly made available
under this Licence.
1.5 'Product' means any device, component, work or physical object,
whether in finished or intermediate form, arising from the use,
application or processing of Covered Source.
1.6 'Make' means to create or configure something, whether by
manufacture, assembly, compiling, loading or applying Covered
Source or another Product or otherwise.
1.7 'Available Component' means any part, sub-assembly, library or
code which:
a) is licensed to You as Complete Source under a Compatible
Licence; or
b) is available, at the time a Product or the Source containing
it is first Conveyed, to You and any other prospective
licensees
i) with sufficient rights and information (including any
configuration and programming files and information
about its characteristics and interfaces) to enable it
either to be Made itself, or to be sourced and used to
Make the Product; or
ii) as part of the normal distribution of a tool used to
design or Make the Product.
1.8 'External Material' means anything (including Source) which:
a) is only combined with Covered Source in such a way that it
interfaces with the Covered Source using a documented
interface which is described in the Covered Source; and
b) is not a derivative of or contains Covered Source, or, if it
is, it is solely to the extent necessary to facilitate such
interfacing.
1.9 'Complete Source' means the set of all Source necessary to Make
a Product, in the preferred form for making modifications,
including necessary installation and interfacing information
both for the Product, and for any included Available Components.
If the format is proprietary, it must also be made available in
a format (if the proprietary tool can create it) which is
viewable with a tool available to potential licensees and
licensed under a licence approved by the Free Software
Foundation or the Open Source Initiative. Complete Source need
not include the Source of any Available Component, provided that
You include in the Complete Source sufficient information to
enable a recipient to Make or source and use the Available
Component to Make the Product.
1.10 'Source Location' means a location where a Licensor has placed
Covered Source, and which that Licensor reasonably believes will
remain easily accessible for at least three years for anyone to
obtain a digital copy.
1.11 'Notice' means copyright, acknowledgement and trademark notices,
Source Location references, modification notices (subsection
3.3(b)) and all notices that refer to this Licence and to the
disclaimer of warranties that are included in the Covered
Source.
1.12 'Licensee' or 'You' means any person exercising rights under
this Licence.
1.13 'Licensor' means a natural or legal person who creates or
modifies Covered Source. A person may be a Licensee and a
Licensor at the same time.
1.14 'Convey' means to communicate to the public or distribute.
2 Applicability
2.1 This Licence governs the use, copying, modification, Conveying
of Covered Source and Products, and the Making of Products. By
exercising any right granted under this Licence, You irrevocably
accept these terms and conditions.
2.2 This Licence is granted by the Licensor directly to You, and
shall apply worldwide and without limitation in time.
2.3 You shall not attempt to restrict by contract or otherwise the
rights granted under this Licence to other Licensees.
2.4 This Licence is not intended to restrict fair use, fair dealing,
or any other similar right.
3 Copying, Modifying and Conveying Covered Source
3.1 You may copy and Convey verbatim copies of Covered Source, in
any medium, provided You retain all Notices.
3.2 You may modify Covered Source, other than Notices, provided that
You irrevocably undertake to make that modified Covered Source
available from a Source Location should You Convey a Product in
circumstances where the recipient does not otherwise receive a
copy of the modified Covered Source. In each case subsection 3.3
shall apply.
You may only delete Notices if they are no longer applicable to
the corresponding Covered Source as modified by You and You may
add additional Notices applicable to Your modifications.
3.3 You may Convey modified Covered Source (with the effect that You
shall also become a Licensor) provided that You:
a) retain Notices as required in subsection 3.2;
b) add a Notice to the modified Covered Source stating that You
have modified it, with the date and brief description of how
You have modified it;
c) add a Source Location Notice for the modified Covered Source
if You Convey in circumstances where the recipient does not
otherwise receive a copy of the modified Covered Source; and
d) license the modified Covered Source under the terms and
conditions of this Licence (or, as set out in subsection
8.3, a later version, if permitted by the licence of the
original Covered Source). Such modified Covered Source must
be licensed as a whole, but excluding Available Components
contained in it or External Material to which it is
interfaced, which remain licensed under their own applicable
licences.
4 Making and Conveying Products
4.1 You may Make Products, and/or Convey them, provided that You
either provide each recipient with a copy of the Complete Source
or ensure that each recipient is notified of the Source Location
of the Complete Source. That Complete Source includes Covered
Source and You must accordingly satisfy Your obligations set out
in subsection 3.3. If specified in a Notice, the Product must
visibly and securely display the Source Location on it or its
packaging or documentation in the manner specified in that
Notice.
4.2 Where You Convey a Product which incorporates External Material,
the Complete Source for that Product which You are required to
provide under subsection 4.1 need not include any Source for the
External Material.
4.3 You may license Products under terms of Your choice, provided
that such terms do not restrict or attempt to restrict any
recipients' rights under this Licence to the Covered Source.
5 Research and Development
You may Convey Covered Source, modified Covered Source or Products to
a legal entity carrying out development, testing or quality assurance
work on Your behalf provided that the work is performed on terms which
prevent the entity from both using the Source or Products for its own
internal purposes and Conveying the Source or Products or any
modifications to them to any person other than You. Any modifications
made by the entity shall be deemed to be made by You pursuant to
subsection 3.2.
6 DISCLAIMER AND LIABILITY
6.1 DISCLAIMER OF WARRANTY -- The Covered Source and any Products
are provided 'as is' and any express or implied warranties,
including, but not limited to, implied warranties of
merchantability, of satisfactory quality, non-infringement of
third party rights, and fitness for a particular purpose or use
are disclaimed in respect of any Source or Product to the
maximum extent permitted by law. The Licensor makes no
representation that any Source or Product does not or will not
infringe any patent, copyright, trade secret or other
proprietary right. The entire risk as to the use, quality, and
performance of any Source or Product shall be with You and not
the Licensor. This disclaimer of warranty is an essential part
of this Licence and a condition for the grant of any rights
granted under this Licence.
6.2 EXCLUSION AND LIMITATION OF LIABILITY -- The Licensor shall, to
the maximum extent permitted by law, have no liability for
direct, indirect, special, incidental, consequential, exemplary,
punitive or other damages of any character including, without
limitation, procurement of substitute goods or services, loss of
use, data or profits, or business interruption, however caused
and on any theory of contract, warranty, tort (including
negligence), product liability or otherwise, arising in any way
in relation to the Covered Source, modified Covered Source
and/or the Making or Conveyance of a Product, even if advised of
the possibility of such damages, and You shall hold the
Licensor(s) free and harmless from any liability, costs,
damages, fees and expenses, including claims by third parties,
in relation to such use.
7 Patents
7.1 Subject to the terms and conditions of this Licence, each
Licensor hereby grants to You a perpetual, worldwide,
non-exclusive, no-charge, royalty-free, irrevocable (except as
stated in subsections 7.2 and 8.4) patent license to Make, have
Made, use, offer to sell, sell, import, and otherwise transfer
the Covered Source and Products, where such licence applies only
to those patent claims licensable by such Licensor that are
necessarily infringed by exercising rights under the Covered
Source as Conveyed by that Licensor.
7.2 If You institute patent litigation against any entity (including
a cross-claim or counterclaim in a lawsuit) alleging that the
Covered Source or a Product constitutes direct or contributory
patent infringement, or You seek any declaration that a patent
licensed to You under this Licence is invalid or unenforceable
then any rights granted to You under this Licence shall
terminate as of the date such process is initiated.
8 General
8.1 If any provisions of this Licence are or subsequently become
invalid or unenforceable for any reason, the remaining
provisions shall remain effective.
8.2 You shall not use any of the name (including acronyms and
abbreviations), image, or logo by which the Licensor or CERN is
known, except where needed to comply with section 3, or where
the use is otherwise allowed by law. Any such permitted use
shall be factual and shall not be made so as to suggest any kind
of endorsement or implication of involvement by the Licensor or
its personnel.
8.3 CERN may publish updated versions and variants of this Licence
which it considers to be in the spirit of this version, but may
differ in detail to address new problems or concerns. New
versions will be published with a unique version number and a
variant identifier specifying the variant. If the Licensor has
specified that a given variant applies to the Covered Source
without specifying a version, You may treat that Covered Source
as being released under any version of the CERN-OHL with that
variant. If no variant is specified, the Covered Source shall be
treated as being released under CERN-OHL-S. The Licensor may
also specify that the Covered Source is subject to a specific
version of the CERN-OHL or any later version in which case You
may apply this or any later version of CERN-OHL with the same
variant identifier published by CERN.
You may treat Covered Source licensed under CERN-OHL-W as
licensed under CERN-OHL-S if and only if all Available
Components referenced in the Covered Source comply with the
corresponding definition of Available Component for CERN-OHL-S.
8.4 This Licence shall terminate with immediate effect if You fail
to comply with any of its terms and conditions.
8.5 However, if You cease all breaches of this Licence, then Your
Licence from any Licensor is reinstated unless such Licensor has
terminated this Licence by giving You, while You remain in
breach, a notice specifying the breach and requiring You to cure
it within 30 days, and You have failed to come into compliance
in all material respects by the end of the 30 day period. Should
You repeat the breach after receipt of a cure notice and
subsequent reinstatement, this Licence will terminate
immediately and permanently. Section 6 shall continue to apply
after any termination.
8.6 This Licence shall not be enforceable except by a Licensor
acting as such, and third party beneficiary rights are
specifically excluded.
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
modules = { "local" : [ "hdl/rtl" ] }
if action == "synthesis":
......
..
SPDX-FileCopyrightText: 2020 CERN (home.cern)
SPDX-License-Identifier: CC0-1.0
==============================
Simple PCIe FMC Carrier - SPEC
==============================
......
build
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
build
rpmbuild
sources
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
TOP_DIR ?= $(shell pwd)/../
HDL_DIR ?= $(TOP_DIR)/hdl
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
PACKAGE_NAME="@PKGNAME@"
PACKAGE_VERSION="@PKGVER@"
CLEAN="make KVERSION=$kernelver DKMSTREE=$dkms_tree DKMS=1 clean"
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
_build/
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
# Minimal makefile for Sphinx documentation
#
# You can set these variables from the command line.
SPHINXOPTS =
SPHINXOPTS = -Drelease=$(shell git describe) -Dversion=$(shell git describe | cut -d "-" -f 1 | tr -d "v")
SPHINXBUILD = sphinx-build
SOURCEDIR = .
BUILDDIR = _build
......
# SPDX-FileCopyrightText: 2020
#
# SPDX-License-Identifier: CC0-1.0
# -*- coding: utf-8 -*-
#
# Configuration file for the Sphinx documentation builder.
......@@ -23,12 +27,6 @@ project = 'SPEC'
copyright = '2019-2020, Federico Vaga <federico.vaga@cern.ch>, Tristan Gingold <tristan.gingold@cern.ch>, Dimitris Lampridis <dimitrios.lampridis@cern.ch>'
author = 'Federico Vaga <federico.vaga@cern.ch>, Tristan Gingold <tristan.gingold@cern.ch>, Dimitris Lampridis <dimitrios.lampridis@cern.ch>'
# The short X.Y version
version = '1.4'
# The full version, including alpha/beta/rc tags
release = 'v1.4'
# -- General configuration ---------------------------------------------------
# If your documentation needs a minimal Sphinx version, state it here.
......@@ -75,7 +73,12 @@ pygments_style = None
# The theme to use for HTML and HTML Help pages. See the documentation for
# a list of builtin themes.
#
html_theme = 'alabaster'
try:
import sphinx_rtd_theme
html_theme = 'sphinx_rtd_theme'
html_theme_path = [sphinx_rtd_theme.get_html_theme_path()]
except ImportError:
sys.stderr.write('Warning: The Sphinx \'sphinx_rtd_theme\' HTML theme was not found. Make sure you have the theme installed to produce pretty HTML output. Falling back to the default theme.\n')
# Theme options are theme-specific and customize the look and feel of a theme
# further. For a list of options available for each theme, see the
......
......@@ -99,28 +99,13 @@ Remember that the Linux driver expects the ``SPEC base`` at offset
Meta-Data ROM
-------------
Fixed Part
~~~~~~~~~~
These are the fixed fields in the current (|version|) release.
========== ========== ================== ============
Offset Size (bit) Name Default (LE)
0x00000000 32 Vendor ID 0x000010DC
0x00000004 32 Device ID 0x53504543
0x00000008 32 Version <variable>
0x0000000C 32 Byte Order Mark 0xFFFE0000
0x00000010 128 Source ID <variable>
0x00000020 32 Capability Mask <variable>
0x00000030 128 Vendor UUID 0x00000000
========== ========== ================== ============
Version 1.4
~~~~~~~~~~~
========== ========== ================== ============
Offset Size (bit) Name Default (LE)
0x00000000 32 Vendor ID 0x000010DC
0x00000004 32 Device ID 0x53504543
0x00000008 32 Version 0x0104xxxx
0x00000008 32 Version 0x0201xxxx
0x0000000C 32 Byte Order Mark 0xFFFE0000
0x00000010 128 Source ID <variable>
0x00000020 32 Capability Mask 0x0000000x
......
alabaster==0.7.12
appdirs==1.4.3
Babel==2.8.0
CacheControl==0.12.6
certifi==2019.11.28
chardet==3.0.4
colorama==0.4.3
contextlib2==0.6.0
distlib==0.3.0
distro==1.4.0
docutils==0.16
html5lib==1.0.1
idna==2.8
imagesize==1.2.0
Jinja2==2.11.2
lockfile==0.12.2
MarkupSafe==1.1.1
msgpack==0.6.2
packaging==20.3
pep517==0.8.2
pkg-resources==0.0.0
progress==1.5
Pygments==2.6.1
pyparsing==2.4.6
pytoml==0.1.21
pytz==2020.1
requests==2.23.0
retrying==1.3.3
six==1.14.0
snowballstemmer==2.0.0
Sphinx==3.1.2
sphinx-rtd-theme==0.5.0
sphinxcontrib-applehelp==1.0.2
sphinxcontrib-devhelp==1.0.2
sphinxcontrib-htmlhelp==1.0.3
sphinxcontrib-jsmath==1.0.1
sphinxcontrib-qthelp==1.0.3
sphinxcontrib-serializinghtml==1.1.4
urllib3==1.25.8
webencodings==0.5.1
......@@ -36,6 +36,10 @@ GN4124 FCL
This driver provides support for the GN4124 FCL (FPGA Configuration Loader).
It uses the `FPGA manager interface`_ to program the FPGA at run-time.
.. note::
At CERN we use CentOS 7 and its kernel does not provide the FPGA manager. To
solve the problem we provide an `FPGA manager backport`_
If the SPEC based application is using the :ref:`SPEC
base<spec_hdl_spec_base>` component then it can profit from the
following driver. They are not all mandatory, it depends on the
......@@ -72,6 +76,7 @@ VIC
.. _`FMC`: https://www.ohwr.org/projects/fmc-sw
.. _`GPIO interface`: https://www.kernel.org/doc/html/latest/driver-api/gpio/index.html
.. _`FPGA manager interface`: https://www.kernel.org/doc/html/latest/driver-api/fpga/index.html
.. _`FPGA manager backport`: https://gitlab.cern.ch/coht/fpga-manager
.. _`DMA Engine`: https://www.kernel.org/doc/html/latest/driver-api/dmaengine/index.html
.. _`general cores`: https://www.ohwr.org/projects/general-cores
......@@ -90,11 +95,25 @@ variable ``CHEBY``. Following an example on how to build the driver(s).::
# define CHEBY only if it is not installed
export CHEBY=/path/to/cheby/proto/cheby.py
export FMC=/path/to/fmc-sw
export FPGA_MGR=/path/to/fpga-mgr
export SPI=/path/to/general-cores/software/spi-ocores
export I2C=/path/to/general-cores/software/i2c-ocores
cd /path/to/spec/
make -C software/kernel modules
make -C software/kernel modules_install
If sources have been cloned all in the same directory you could you the
following commands.::
# define CHEBY only if it is not installed
export CHEBY=/path/to/cheby/proto/cheby.py
export REPO_PARENT=/path/to/directory/where/all/dependencies/are/
cd /path/to/spec/
make -C software/kernel modules
make -C software/kernel modules_install
This will build and install 4 drivers:
This will build and install 4 drivers:
- :ref:`spec-fmc-carrier.ko<spec_fmc_carrier>`,
- :ref:`gn412x-gpio.ko<gn4124_gpio>`,
......@@ -109,10 +128,10 @@ This will build and install 4 drivers:
software/kernel/spec-fmc-carrier.ko
software/kernel/spec-gn412x-dma.ko
Please note that this will not install all soft dependencies which are
Please note that this will not install the dependencies which are
distributed separately (:ref:`I2C OpenCore<i2c_ocore>`,
:ref:`SPI OpenCore<spi_ocore>`, :ref:`HT Vector Interrupt Controller<vic>`,
`FMC`_).
`FMC`_, `FPGA manager backport`_).
.. _`cheby`: https://gitlab.cern.ch/cohtdrivers/cheby
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
sourceid_spec_base_pkg.vhd
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
files = [
"spec_base_regs.vhd",
"spec_base_wr.vhd",
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC-BY-SA-4.0 OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
memory-map:
name: spec_base_regs
bus: wb-32-be
......
-- SPDX-FileCopyrightText: 2020 CERN (home.cern)
--
-- SPDX-License-Identifier: CC-BY-SA-4.0 OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
-- Do not edit; this file was generated by Cheby using these options:
-- --gen-hdl=spec_base_regs.vhd -i spec_base_regs.cheby
......
--------------------------------------------------------------------------------
-- SPDX-FileCopyrightText: 2020 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
--
-- CERN BE-CO-HT
-- SPEC
-- https://ohwr.org/projects/spec
......@@ -9,18 +13,6 @@
-- description: SPEC carrier base.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2019
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
files = ["spec_base_common.ucf"]
ucf_dict = {'wr': "spec_base_wr.ucf",
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
#===============================================================================
# IO Constraints
#===============================================================================
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
## DDR-3
NET "ddr_rzq_b" LOC = K7;
NET "ddr_we_n_o" LOC = H2;
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
###########################################################################
## Onewire interface -> thermometer
###########################################################################
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
###########################################################################
## Flash memory SPI interface
###########################################################################
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
#===============================================================================
# IO Location Constraints
#===============================================================================
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
*
!.gitignore
!Manifest.py
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
target = "xilinx"
action = "synthesis"
board = "spec"
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
*
!.gitignore
!Manifest.py
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
target = "xilinx"
action = "synthesis"
board = "spec"
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
*
!.gitignore
!Manifest.py
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
target = "xilinx"
action = "synthesis"
board = "spec"
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
*
!.gitignore
!Manifest.py
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
target = "xilinx"
action = "synthesis"
board = "spec"
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
Makefile
work/
transcript
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
board = "spec"
sim_tool = "modelsim"
sim_top = "main"
......
// SPDX-FileCopyrightText: 2020 CERN (home.cern)
//
// SPDX-License-Identifier: CC0-1.0
`timescale 1ns/1ps
`include "gn4124_bfm.svh"
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
vsim -quiet -t 10fs -L unisim work.main -suppress 1270,8617,8683,8684,8822 -voptargs="+acc" -sv_seed random
set StdArithNoWarnings 1
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
vsim -quiet -t 10fs -L unisim work.main -suppress 1270,8617,8683,8684,8822 -sv_seed random
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -group {App DDR port} -color Coral /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/rst_n_i
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
......
--------------------------------------------------------------------------------
-- SPDX-FileCopyrightText: 2020 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
--
-- CERN BE-CO-HT
-- SPEC
-- https://ohwr.org/projects/spec
......@@ -9,18 +13,6 @@
-- description: SPEC golden design, without WR.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2019-2020
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
files = ["spec_base_wr_example.vhd"]
modules = {'local': ["../../rtl"]}
--------------------------------------------------------------------------------
-- SPDX-FileCopyrightText: 2020 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
--
-- CERN BE-CO-HT
-- SPEC
-- https://ohwr.org/projects/spec
......@@ -9,18 +13,6 @@
-- description: Example instantiation of SPEC base with White Rabbit.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2019-2020
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
-include Makefile.specific
-include $(REPO_PARENT)/parent_common.mk
......
/*
* Copyright (C) 2020 CERN (www.cern.ch)
* Author: Federico Vaga <federico.vaga@cern.ch>
*/
// Copyright (C) 2020 CERN (www.cern.ch)
// SPDX-FileCopyrightText: 2020 CERN (home.cern)
//
// SPDX-License-Identifier: GPL-2.0-or-later
// Author: Federico Vaga <federico.vaga@cern.ch>
#ifndef __LINUX_UAPI_SPEC_H
#define __LINUX_UAPI_SPEC_H
......
# SPDX-FileCopyrightText: Linux
#
# SPDX-License-Identifier: GPL-2.0-or-later
#
# clang-format configuration file. Intended for clang-format >= 4.
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
spec-core-fpga.h
\ No newline at end of file
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
# add versions of supermodule. It is useful when spec is included as sub-module
# of a bigger project that we want to track
ifdef CONFIG_SUPER_REPO
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
-include Makefile.specific
-include $(REPO_PARENT)/parent_common.mk
......
......@@ -14,33 +14,6 @@
#include "spec-compat.h"
#include "gn412x.h"
#define FCL_CTRL_START_FSM BIT(0)
#define FCL_CTRL_SPRI_EN BIT(1)
#define FCL_CTRL_FSM_EN BIT(2)
#define FCL_CTRL_SEND_CFG_DATA BIT(3)
#define FCL_CTRL_LAST_BYTE_CNT_1 (0x3 << 4)
#define FCL_CTRL_LAST_BYTE_CNT_2 (0x2 << 4)
#define FCL_CTRL_LAST_BYTE_CNT_3 (0x1 << 4)
#define FCL_CTRL_LAST_BYTE_CNT_4 (0x0 << 4)
#define FCL_CTRL_RESET BIT(6)
#define FCL_CTRL_DATA_PUSH_COMP BIT(7)
#define FCL_CTRL_SPRI_CLK_STOP_EN BIT(8)
#define FCL_SPRI_CLKOUT BIT(0)
#define FCL_SPRI_DATAOUT BIT(1)
#define FCL_SPRI_CONFIG BIT(2)
#define FCL_SPRI_DONE BIT(3)
#define FCL_SPRI_XI_SWAP BIT(4)
#define FCL_SPRI_STATUS BIT(5)
#define FCL_IRQ_SPRI_STATUS BIT(0)
#define FCL_IRQ_TIMER BIT(1)
#define FCL_IRQ_CONFIG_ERROR BIT(2)
#define FCL_IRQ_CONFIG_DONE BIT(3)
#define FCL_IRQ_FIFO_UNDRFL BIT(4)
#define FCL_IRQ_FIFO_HALFFULL BIT(5)
/* Compatibility layer */
static int gn412x_fcl_write_init(struct fpga_manager *mgr,
struct fpga_image_info *info,
......
......@@ -85,4 +85,30 @@ enum {
PCI_SYS_CFG_SYSTEM = 0x800
};
#define FCL_CTRL_START_FSM BIT(0)
#define FCL_CTRL_SPRI_EN BIT(1)
#define FCL_CTRL_FSM_EN BIT(2)
#define FCL_CTRL_SEND_CFG_DATA BIT(3)
#define FCL_CTRL_LAST_BYTE_CNT_1 (0x3 << 4)
#define FCL_CTRL_LAST_BYTE_CNT_2 (0x2 << 4)
#define FCL_CTRL_LAST_BYTE_CNT_3 (0x1 << 4)
#define FCL_CTRL_LAST_BYTE_CNT_4 (0x0 << 4)
#define FCL_CTRL_RESET BIT(6)
#define FCL_CTRL_DATA_PUSH_COMP BIT(7)
#define FCL_CTRL_SPRI_CLK_STOP_EN BIT(8)
#define FCL_SPRI_CLKOUT BIT(0)
#define FCL_SPRI_DATAOUT BIT(1)
#define FCL_SPRI_CONFIG BIT(2)
#define FCL_SPRI_DONE BIT(3)
#define FCL_SPRI_XI_SWAP BIT(4)
#define FCL_SPRI_STATUS BIT(5)
#define FCL_IRQ_SPRI_STATUS BIT(0)
#define FCL_IRQ_TIMER BIT(1)
#define FCL_IRQ_CONFIG_ERROR BIT(2)
#define FCL_IRQ_CONFIG_DONE BIT(3)
#define FCL_IRQ_FIFO_UNDRFL BIT(4)
#define FCL_IRQ_FIFO_HALFFULL BIT(5)
#endif
......@@ -25,6 +25,7 @@
#include "linux/printk.h"
#include "spec.h"
#include "spec-compat.h"
#include "gn412x.h"
static int version_ignore = 0;
module_param(version_ignore, int, 0644);
......@@ -1194,6 +1195,22 @@ static const struct device_type spec_fpga_type = {
.groups = spec_groups,
};
/**
* Checks if the FPGA has been programmed
*/
static bool spec_fpga_is_programmed(struct spec_gn412x *spec_gn412x)
{
struct resource *r4 = &spec_gn412x->pdev->resource[4];
void *mem;
bool done;
mem = ioremap(r4->start, resource_size(r4));
done = ioread32(mem + FCL_STATUS) & FCL_SPRI_DONE;
iounmap(mem);
dev_err(&spec_gn412x->pdev->dev, "SPRI_DONE %d\n", done);
return done;
}
/**
* Initialize carrier devices on FPGA
*/
......@@ -1203,6 +1220,11 @@ int spec_fpga_init(struct spec_gn412x *spec_gn412x)
struct resource *r0 = &spec_gn412x->pdev->resource[0];
int err;
if (!spec_fpga_is_programmed(spec_gn412x)) {
dev_err(&spec_gn412x->pdev->dev, "FPGA is not programmed\n");
return -ENODEV;
}
spec_fpga = kzalloc(sizeof(*spec_fpga), GFP_KERNEL);
if (!spec_fpga)
return -ENOMEM;
......
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
spec-firmware-version
#!/usr/bin/python3
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: GPL-3.0-or-later
import os
import re
import argparse
......
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