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Simple PCIe FMC carrier SPEC
Commit fffa8b42 authored by Federico Vaga's avatar Federico Vaga
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Merge branch 'release/v2.1.5'

parents fd485c8b ee786de1
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.gitignore
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# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
*.o
*.ko
*.mod.c
......@@ -16,3 +20,4 @@ GPATH
GRTAGS
Makefile.specific
compile_commands.json
.clangd
\ No newline at end of file
.gitmodules
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# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
[submodule "hdl/ip_cores/wr-cores"]
path = hdl/ip_cores/wr-cores
url = https://ohwr.org/project/wr-cores.git
......
.readthedocs.yaml 0 → 100644
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# .readthedocs.yml
# Read the Docs configuration file
# See https://docs.readthedocs.io/en/stable/config-file/v2.html for details
# Required
version: 2
# Build documentation in the docs/ directory with Sphinx
sphinx:
configuration: doc/conf.py
# Build documentation with MkDocs
#mkdocs:
# configuration: mkdocs.yml
# Optionally build your docs in additional formats such as PDF and ePub
formats:
- pdf
# Optionally set the version of Python and requirements required to build your docs
python:
version: 3.7
install:
- requirements: doc/requirements.txt
# Exclude all submodules, they are not needed for documentation
submodules:
exclude: all
.reuse/dep5 0 → 100644
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Format: https://www.debian.org/doc/packaging-manuals/copyright-format/1.0/
Upstream-Name: SPEC
Upstream-Contact: Federico Vaga <federico.vaga@cern.ch>
Source: https://ohwr.org/project/spec/
Files: doc/requirements.txt
Copyright: 2020 CERN (home.cern)
License: CC0-1.0
CHANGELOG.rst
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......@@ -6,6 +6,13 @@
Changelog
=========
2.1.5 - 2021-05-18
==================
Fixed
-----
- sw: check if FPGA is programmed before loading FPGA devices
- doc: improve documentation
2.1.4 - 2020-11-23
==================
Fixed
......
LICENSES/CERN-OHL-W-2.0+.txt 0 → 120000
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CERN-OHL-W-2.0.txt
\ No newline at end of file
LICENSES/CERN-OHL-W-2.0.txt 0 → 100644
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Manifest.py
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# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
modules = { "local" : [ "hdl/rtl" ] }
if action == "synthesis":
......
README.rst
View file @ fffa8b42
..
SPDX-FileCopyrightText: 2020 CERN (home.cern)
SPDX-License-Identifier: CC0-1.0
==============================
Simple PCIe FMC Carrier - SPEC
==============================
......
distribution/.gitignore
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build
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
build
rpmbuild
sources
distribution/Makefile
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# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
TOP_DIR ?= $(shell pwd)/../
HDL_DIR ?= $(TOP_DIR)/hdl
......
distribution/dkms.conf
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# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
PACKAGE_NAME="@PKGNAME@"
PACKAGE_VERSION="@PKGVER@"
CLEAN="make KVERSION=$kernelver DKMSTREE=$dkms_tree DKMS=1 clean"
......
doc/.gitignore
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# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
_build/
doc/Makefile
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# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
# Minimal makefile for Sphinx documentation
#
# You can set these variables from the command line.
SPHINXOPTS =
SPHINXOPTS = -Drelease=$(shell git describe) -Dversion=$(shell git describe | cut -d "-" -f 1 | tr -d "v")
SPHINXBUILD = sphinx-build
SOURCEDIR = .
BUILDDIR = _build
......
doc/conf.py
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# SPDX-FileCopyrightText: 2020
#
# SPDX-License-Identifier: CC0-1.0
# -*- coding: utf-8 -*-
#
# Configuration file for the Sphinx documentation builder.
......@@ -23,12 +27,6 @@ project = 'SPEC'
copyright = '2019-2020, Federico Vaga <federico.vaga@cern.ch>, Tristan Gingold <tristan.gingold@cern.ch>, Dimitris Lampridis <dimitrios.lampridis@cern.ch>'
author = 'Federico Vaga <federico.vaga@cern.ch>, Tristan Gingold <tristan.gingold@cern.ch>, Dimitris Lampridis <dimitrios.lampridis@cern.ch>'
# The short X.Y version
version = '1.4'
# The full version, including alpha/beta/rc tags
release = 'v1.4'
# -- General configuration ---------------------------------------------------
# If your documentation needs a minimal Sphinx version, state it here.
......@@ -75,7 +73,12 @@ pygments_style = None
# The theme to use for HTML and HTML Help pages. See the documentation for
# a list of builtin themes.
#
html_theme = 'alabaster'
try:
import sphinx_rtd_theme
html_theme = 'sphinx_rtd_theme'
html_theme_path = [sphinx_rtd_theme.get_html_theme_path()]
except ImportError:
sys.stderr.write('Warning: The Sphinx \'sphinx_rtd_theme\' HTML theme was not found. Make sure you have the theme installed to produce pretty HTML output. Falling back to the default theme.\n')
# Theme options are theme-specific and customize the look and feel of a theme
# further. For a list of options available for each theme, see the
......
doc/hdl-spec-base.rst
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......@@ -99,28 +99,13 @@ Remember that the Linux driver expects the ``SPEC base`` at offset
Meta-Data ROM
-------------
Fixed Part
~~~~~~~~~~
These are the fixed fields in the current (|version|) release.
========== ========== ================== ============
Offset Size (bit) Name Default (LE)
0x00000000 32 Vendor ID 0x000010DC
0x00000004 32 Device ID 0x53504543
0x00000008 32 Version <variable>
0x0000000C 32 Byte Order Mark 0xFFFE0000
0x00000010 128 Source ID <variable>
0x00000020 32 Capability Mask <variable>
0x00000030 128 Vendor UUID 0x00000000
========== ========== ================== ============
Version 1.4
~~~~~~~~~~~
========== ========== ================== ============
Offset Size (bit) Name Default (LE)
0x00000000 32 Vendor ID 0x000010DC
0x00000004 32 Device ID 0x53504543
0x00000008 32 Version 0x0104xxxx
0x00000008 32 Version 0x0201xxxx
0x0000000C 32 Byte Order Mark 0xFFFE0000
0x00000010 128 Source ID <variable>
0x00000020 32 Capability Mask 0x0000000x
......
doc/requirements.txt 0 → 100644
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alabaster==0.7.12
appdirs==1.4.3
Babel==2.8.0
CacheControl==0.12.6
certifi==2019.11.28
chardet==3.0.4
colorama==0.4.3
contextlib2==0.6.0
distlib==0.3.0
distro==1.4.0
docutils==0.16
html5lib==1.0.1
idna==2.8
imagesize==1.2.0
Jinja2==2.11.2
lockfile==0.12.2
MarkupSafe==1.1.1
msgpack==0.6.2
packaging==20.3
pep517==0.8.2
pkg-resources==0.0.0
progress==1.5
Pygments==2.6.1
pyparsing==2.4.6
pytoml==0.1.21
pytz==2020.1
requests==2.23.0
retrying==1.3.3
six==1.14.0
snowballstemmer==2.0.0
Sphinx==3.1.2
sphinx-rtd-theme==0.5.0
sphinxcontrib-applehelp==1.0.2
sphinxcontrib-devhelp==1.0.2
sphinxcontrib-htmlhelp==1.0.3
sphinxcontrib-jsmath==1.0.1
sphinxcontrib-qthelp==1.0.3
sphinxcontrib-serializinghtml==1.1.4
urllib3==1.25.8
webencodings==0.5.1
doc/sw-driver.rst
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......@@ -36,6 +36,10 @@ GN4124 FCL
This driver provides support for the GN4124 FCL (FPGA Configuration Loader).
It uses the `FPGA manager interface`_ to program the FPGA at run-time.
.. note::
At CERN we use CentOS 7 and its kernel does not provide the FPGA manager. To
solve the problem we provide an `FPGA manager backport`_
If the SPEC based application is using the :ref:`SPEC
base<spec_hdl_spec_base>` component then it can profit from the
following driver. They are not all mandatory, it depends on the
......@@ -72,6 +76,7 @@ VIC
.. _`FMC`: https://www.ohwr.org/projects/fmc-sw
.. _`GPIO interface`: https://www.kernel.org/doc/html/latest/driver-api/gpio/index.html
.. _`FPGA manager interface`: https://www.kernel.org/doc/html/latest/driver-api/fpga/index.html
.. _`FPGA manager backport`: https://gitlab.cern.ch/coht/fpga-manager
.. _`DMA Engine`: https://www.kernel.org/doc/html/latest/driver-api/dmaengine/index.html
.. _`general cores`: https://www.ohwr.org/projects/general-cores
......@@ -90,11 +95,25 @@ variable ``CHEBY``. Following an example on how to build the driver(s).::
# define CHEBY only if it is not installed
export CHEBY=/path/to/cheby/proto/cheby.py
export FMC=/path/to/fmc-sw
export FPGA_MGR=/path/to/fpga-mgr
export SPI=/path/to/general-cores/software/spi-ocores
export I2C=/path/to/general-cores/software/i2c-ocores
cd /path/to/spec/
make -C software/kernel modules
make -C software/kernel modules_install
If sources have been cloned all in the same directory you could you the
following commands.::
# define CHEBY only if it is not installed
export CHEBY=/path/to/cheby/proto/cheby.py
export REPO_PARENT=/path/to/directory/where/all/dependencies/are/
cd /path/to/spec/
make -C software/kernel modules
make -C software/kernel modules_install
This will build and install 4 drivers:
This will build and install 4 drivers:
- :ref:`spec-fmc-carrier.ko<spec_fmc_carrier>`,
- :ref:`gn412x-gpio.ko<gn4124_gpio>`,
......@@ -109,10 +128,10 @@ This will build and install 4 drivers:
software/kernel/spec-fmc-carrier.ko
software/kernel/spec-gn412x-dma.ko
Please note that this will not install all soft dependencies which are
Please note that this will not install the dependencies which are
distributed separately (:ref:`I2C OpenCore<i2c_ocore>`,
:ref:`SPI OpenCore<spi_ocore>`, :ref:`HT Vector Interrupt Controller<vic>`,
`FMC`_).
`FMC`_, `FPGA manager backport`_).
.. _`cheby`: https://gitlab.cern.ch/cohtdrivers/cheby
......
hdl/rtl/.gitignore
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# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
sourceid_spec_base_pkg.vhd
hdl/rtl/Manifest.py
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# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
files = [
"spec_base_regs.vhd",
"spec_base_wr.vhd",
......
hdl/rtl/spec_base_regs.cheby
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# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC-BY-SA-4.0 OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
memory-map:
name: spec_base_regs
bus: wb-32-be
......
hdl/rtl/spec_base_regs.vhd
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-- SPDX-FileCopyrightText: 2020 CERN (home.cern)
--
-- SPDX-License-Identifier: CC-BY-SA-4.0 OR CERN-OHL-W-2.0+ OR GPL-2.0-or-later
-- Do not edit; this file was generated by Cheby using these options:
-- --gen-hdl=spec_base_regs.vhd -i spec_base_regs.cheby
......
hdl/rtl/spec_base_wr.vhd
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--------------------------------------------------------------------------------
-- SPDX-FileCopyrightText: 2020 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
--
-- CERN BE-CO-HT
-- SPEC
-- https://ohwr.org/projects/spec
......@@ -9,18 +13,6 @@
-- description: SPEC carrier base.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2019
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
......
hdl/syn/common/Manifest.py
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# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
files = ["spec_base_common.ucf"]
ucf_dict = {'wr': "spec_base_wr.ucf",
......
hdl/syn/common/spec_base_common.ucf
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# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
#===============================================================================
# IO Constraints
#===============================================================================
......
hdl/syn/common/spec_base_ddr3.ucf
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# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
## DDR-3
NET "ddr_rzq_b" LOC = K7;
NET "ddr_we_n_o" LOC = H2;
......
hdl/syn/common/spec_base_onewire.ucf
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# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
###########################################################################
## Onewire interface -> thermometer
###########################################################################
......
hdl/syn/common/spec_base_spi.ucf
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# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
###########################################################################
## Flash memory SPI interface
###########################################################################
......
hdl/syn/common/spec_base_wr.ucf
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# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
#===============================================================================
# IO Location Constraints
#===============================================================================
......
hdl/syn/golden-100T/.gitignore
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# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
*
!.gitignore
!Manifest.py
......
hdl/syn/golden-100T/Manifest.py
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# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
target = "xilinx"
action = "synthesis"
board = "spec"
......
hdl/syn/golden-100T/syn_extra_steps.tcl
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# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
......
hdl/syn/golden-150T/.gitignore
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# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
*
!.gitignore
!Manifest.py
......
hdl/syn/golden-150T/Manifest.py
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# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
target = "xilinx"
action = "synthesis"
board = "spec"
......
hdl/syn/golden-150T/syn_extra_steps.tcl
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# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
......
hdl/syn/golden-45T/.gitignore
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# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
*
!.gitignore
!Manifest.py
......
hdl/syn/golden-45T/Manifest.py
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# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
target = "xilinx"
action = "synthesis"
board = "spec"
......
hdl/syn/golden-45T/syn_extra_steps.tcl
View file @ fffa8b42
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
......
hdl/syn/wr_example/.gitignore
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# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
*
!.gitignore
!Manifest.py
......
hdl/syn/wr_example/Manifest.py
View file @ fffa8b42
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
target = "xilinx"
action = "synthesis"
board = "spec"
......
hdl/syn/wr_example/syn_extra_steps.tcl
View file @ fffa8b42
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
......
hdl/testbench/golden/.gitignore
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# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
Makefile
work/
transcript
......
hdl/testbench/golden/Manifest.py
View file @ fffa8b42
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
board = "spec"
sim_tool = "modelsim"
sim_top = "main"
......
hdl/testbench/golden/main.sv
View file @ fffa8b42
// SPDX-FileCopyrightText: 2020 CERN (home.cern)
//
// SPDX-License-Identifier: CC0-1.0
`timescale 1ns/1ps
`include "gn4124_bfm.svh"
......
hdl/testbench/golden/run.do
View file @ fffa8b42
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
vsim -quiet -t 10fs -L unisim work.main -suppress 1270,8617,8683,8684,8822 -voptargs="+acc" -sv_seed random
set StdArithNoWarnings 1
......
hdl/testbench/golden/run_ci.do
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# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
vsim -quiet -t 10fs -L unisim work.main -suppress 1270,8617,8683,8684,8822 -sv_seed random
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
......
hdl/testbench/golden/wave.do
View file @ fffa8b42
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -group {App DDR port} -color Coral /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_0/rst_n_i
......
hdl/top/golden/Manifest.py
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# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
......
hdl/top/golden/spec_golden.vhd
View file @ fffa8b42
--------------------------------------------------------------------------------
-- SPDX-FileCopyrightText: 2020 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
--
-- CERN BE-CO-HT
-- SPEC
-- https://ohwr.org/projects/spec
......@@ -9,18 +13,6 @@
-- description: SPEC golden design, without WR.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2019-2020
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
......
hdl/top/wr_example/Manifest.py
View file @ fffa8b42
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
files = ["spec_base_wr_example.vhd"]
modules = {'local': ["../../rtl"]}
hdl/top/wr_example/spec_base_wr_example.vhd
View file @ fffa8b42
--------------------------------------------------------------------------------
-- SPDX-FileCopyrightText: 2020 CERN (home.cern)
--
-- SPDX-License-Identifier: CERN-OHL-W-2.0+
--
-- CERN BE-CO-HT
-- SPEC
-- https://ohwr.org/projects/spec
......@@ -9,18 +13,6 @@
-- description: Example instantiation of SPEC base with White Rabbit.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2019-2020
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
......
software/Makefile
View file @ fffa8b42
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
-include Makefile.specific
-include $(REPO_PARENT)/parent_common.mk
......
software/include/uapi/linux/spec.h
View file @ fffa8b42
/*
* Copyright (C) 2020 CERN (www.cern.ch)
* Author: Federico Vaga <federico.vaga@cern.ch>
*/
// Copyright (C) 2020 CERN (www.cern.ch)
// SPDX-FileCopyrightText: 2020 CERN (home.cern)
//
// SPDX-License-Identifier: GPL-2.0-or-later
// Author: Federico Vaga <federico.vaga@cern.ch>
#ifndef __LINUX_UAPI_SPEC_H
#define __LINUX_UAPI_SPEC_H
......
software/kernel/.clang-format
View file @ fffa8b42
# SPDX-FileCopyrightText: Linux
#
# SPDX-License-Identifier: GPL-2.0-or-later
#
# clang-format configuration file. Intended for clang-format >= 4.
......
software/kernel/.gitignore
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# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
spec-core-fpga.h
\ No newline at end of file
software/kernel/Kbuild
View file @ fffa8b42
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
# add versions of supermodule. It is useful when spec is included as sub-module
# of a bigger project that we want to track
ifdef CONFIG_SUPER_REPO
......
software/kernel/Makefile
View file @ fffa8b42
# SPDX-FileCopyrightText: 2020 CERN (home.cern)
#
# SPDX-License-Identifier: CC0-1.0
-include Makefile.specific
-include $(REPO_PARENT)/parent_common.mk
......
software/kernel/gn412x-fcl.c
View file @ fffa8b42
......@@ -14,33 +14,6 @@
#include "spec-compat.h"
#include "gn412x.h"
#define FCL_CTRL_START_FSM BIT(0)
#define FCL_CTRL_SPRI_EN BIT(1)
#define FCL_CTRL_FSM_EN BIT(2)
#define FCL_CTRL_SEND_CFG_DATA BIT(3)
#define FCL_CTRL_LAST_BYTE_CNT_1 (0x3 << 4)
#define FCL_CTRL_LAST_BYTE_CNT_2 (0x2 << 4)
#define FCL_CTRL_LAST_BYTE_CNT_3 (0x1 << 4)
#define FCL_CTRL_LAST_BYTE_CNT_4 (0x0 << 4)
#define FCL_CTRL_RESET BIT(6)
#define FCL_CTRL_DATA_PUSH_COMP BIT(7)
#define FCL_CTRL_SPRI_CLK_STOP_EN BIT(8)
#define FCL_SPRI_CLKOUT BIT(0)
#define FCL_SPRI_DATAOUT BIT(1)
#define FCL_SPRI_CONFIG BIT(2)
#define FCL_SPRI_DONE BIT(3)
#define FCL_SPRI_XI_SWAP BIT(4)
#define FCL_SPRI_STATUS BIT(5)
#define FCL_IRQ_SPRI_STATUS BIT(0)
#define FCL_IRQ_TIMER BIT(1)
#define FCL_IRQ_CONFIG_ERROR BIT(2)
#define FCL_IRQ_CONFIG_DONE BIT(3)
#define FCL_IRQ_FIFO_UNDRFL BIT(4)
#define FCL_IRQ_FIFO_HALFFULL BIT(5)
/* Compatibility layer */
static int gn412x_fcl_write_init(struct fpga_manager *mgr,
struct fpga_image_info *info,
......
software/kernel/gn412x.h
View file @ fffa8b42
......@@ -85,4 +85,30 @@ enum {
PCI_SYS_CFG_SYSTEM = 0x800
};
#define FCL_CTRL_START_FSM BIT(0)
#define FCL_CTRL_SPRI_EN BIT(1)
#define FCL_CTRL_FSM_EN BIT(2)
#define FCL_CTRL_SEND_CFG_DATA BIT(3)
#define FCL_CTRL_LAST_BYTE_CNT_1 (0x3 << 4)
#define FCL_CTRL_LAST_BYTE_CNT_2 (0x2 << 4)
#define FCL_CTRL_LAST_BYTE_CNT_3 (0x1 << 4)
#define FCL_CTRL_LAST_BYTE_CNT_4 (0x0 << 4)
#define FCL_CTRL_RESET BIT(6)