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Simple PCIe FMC carrier SPEC
Commit ff41468d authored by Tristan Gingold's avatar Tristan Gingold
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spec golden: use xwb_split; fix vic polarity; reorder capabilities.

parent c3067e82
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Showing with 23 additions and 66 deletions
hdl/rtl/spec_template_wr.vhd
View file @ ff41468d
...@@ -481,66 +481,21 @@ begin -- architecture top ...@@ -481,66 +481,21 @@ begin -- architecture top
); );
-- Mini-crossbar from gennum to carrier and application bus. -- Mini-crossbar from gennum to carrier and application bus.
carrier_app_xb: process (clk_sys_62m5) inst_split: entity work.xwb_split
is generic map (
type t_ca_state is (S_IDLE, S_APP, S_CARRIER); g_mask => x"ffff_e000"
variable ca_state : t_ca_state; )
variable can_stall : std_logic; port map (
constant c_IDLE_WB_MASTER_IN : t_wishbone_master_in := clk_sys_i => clk_sys_62m5,
(ack => '0', err => '0', rty => '0', stall => '0', dat => c_DUMMY_WB_DATA); rst_n_i => rst_sys_62m5_n,
begin slave_i => gn_wb_out,
if rising_edge(clk_sys_62m5) then slave_o => gn_wb_in,
if rst_sys_62m5_n = '0' then master_i (0) => carrier_wb_out,
ca_state := S_IDLE; master_i (1) => app_wb_i,
gn_wb_in <= c_IDLE_WB_MASTER_IN; master_o (0) => carrier_wb_in,
app_wb_o <= c_DUMMY_WB_MASTER_OUT; master_o (1) => app_wb_o
carrier_wb_in <= c_DUMMY_WB_MASTER_OUT; );
else
case ca_state is
when S_IDLE =>
gn_wb_in <= c_IDLE_WB_MASTER_IN;
app_wb_o <= c_DUMMY_WB_MASTER_OUT;
carrier_wb_in <= c_DUMMY_WB_MASTER_OUT;
if gn_wb_out.cyc = '1'
and gn_wb_out.stb = '1'
then
-- New transaction.
-- Stall so that there is no new requests from the master.
gn_wb_in.stall <= '1';
can_stall := '1';
if gn_wb_out.adr (31 downto 13) = (31 downto 13 => '0') then
ca_state := S_CARRIER;
-- Pass to carrier
carrier_wb_in <= gn_wb_out;
else
ca_state := S_APP;
app_wb_o <= gn_wb_out;
end if;
end if;
when S_CARRIER =>
-- Pass from carrier.
-- Maintain stb as long as the carrier stalls.
carrier_wb_in.stb <= carrier_wb_out.stall and can_stall;
can_stall := can_stall and carrier_wb_out.stall;
gn_wb_in <= carrier_wb_out;
gn_wb_in.stall <= '1';
if carrier_wb_out.ack = '1' then
ca_state := S_IDLE;
end if;
when S_APP =>
-- Pass from application
app_wb_o.stb <= app_wb_i.stall and can_stall;
can_stall := can_stall and app_wb_i.stall;
gn_wb_in <= app_wb_i;
gn_wb_in.stall <= '1';
if app_wb_i.ack = '1' or app_wb_i.err = '1' then
ca_state := S_IDLE;
end if;
end case;
end if;
end if;
end process carrier_app_xb;
inst_devs: entity work.spec_template_regs inst_devs: entity work.spec_template_regs
port map ( port map (
rst_n_i => rst_sys_62m5_n, rst_n_i => rst_sys_62m5_n,
...@@ -642,11 +597,11 @@ begin -- architecture top ...@@ -642,11 +597,11 @@ begin -- architecture top
if g_WITH_WR then if g_WITH_WR then
metadata_data(3) <= '1'; metadata_data(3) <= '1';
end if; end if;
-- Buildinfo
metadata_data(4) <= '1';
if g_WITH_DDR then if g_WITH_DDR then
metadata_data(4) <= '1'; metadata_data(5) <= '1';
end if; end if;
-- Buildinfo
metadata_data(5) <= '1';
when others => when others =>
metadata_data <= x"00000000"; metadata_data <= x"00000000";
end case; end case;
...@@ -727,7 +682,9 @@ begin -- architecture top ...@@ -727,7 +682,9 @@ begin -- architecture top
inst_vic: entity work.xwb_vic inst_vic: entity work.xwb_vic
generic map ( generic map (
g_address_granularity => BYTE, g_address_granularity => BYTE,
g_num_interrupts => num_interrupts g_num_interrupts => num_interrupts,
g_FIXED_POLARITY => True,
g_POLARITY => '1'
) )
port map ( port map (
clk_sys_i => clk_sys_62m5, clk_sys_i => clk_sys_62m5,
......
hdl/top/golden_wr/spec_golden_wr.ucf
View file @ ff41468d
...@@ -264,8 +264,8 @@ TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%; ...@@ -264,8 +264,8 @@ TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
# refclock is 62.5MHz and we don't use g_divide_input_by_2. # refclock is 62.5MHz and we don't use g_divide_input_by_2.
#PIN "WRC_PLATFORM/cmp_pllrefclk_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE; #PIN "WRC_PLATFORM/cmp_pllrefclk_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2017/02/20 #Created by Constraints Editor (xc6slx45t-fgg484-3) - 2017/02/20
NET "inst_template/g_wr.cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = inst_template/g_wr.cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>; NET "inst_template/gen_wr.cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = inst_template/gen_wr.cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>;
TIMESPEC TS_cmp_xwrc_board_spec_cmp_xwrc_platform_gen_phy_spartan6_cmp_gtp_ch1_gtp_clkout_int_1_ = PERIOD "inst_template/cmp_xwrc_board_spec/g_wr.cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%; TIMESPEC TS_cmp_xwrc_board_spec_cmp_xwrc_platform_gen_phy_spartan6_cmp_gtp_ch1_gtp_clkout_int_1_ = PERIOD "inst_template/cmp_xwrc_board_spec/gen_wr.cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
# PIN "cmp_clk_dmtd_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; # PIN "cmp_clk_dmtd_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
##Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/08/07 ##Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/08/07
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit; INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
......
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