Commit de80bdd9 authored by Dimitris Lampridis's avatar Dimitris Lampridis

Merge branch 'feature/hdl/top_level_cleanup' into develop

parents 903f594d 9288616d
......@@ -301,7 +301,7 @@ entity spec_base_wr is
-- Addresses 0-0x1fff are not available (used by the carrier).
-- This is a pipelined wishbone with byte granularity.
app_wb_o : out t_wishbone_master_out;
app_wb_i : in t_wishbone_master_in;
app_wb_i : in t_wishbone_master_in := c_DUMMY_WB_MASTER_IN;
sim_wb_i : in t_wishbone_slave_in := cc_dummy_slave_in;
sim_wb_o : out t_wishbone_slave_out
......
target = "xilinx"
action = "synthesis"
board = "spec"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_device = "xc6slx100t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_dma_test.xise"
syn_tool = "ise"
syn_top = "spec_dma_test"
syn_project = "spec_golden-100T.xise"
syn_tool = "ise"
syn_top = "spec_golden"
spec_base_ucf = ['onewire', 'spi', 'ddr3']
board = "spec"
spec_base_ucf = ['ddr3']
ctrls = ["bank3_32b_32b" ]
files = [ "buildinfo_pkg.vhd" ]
files = [
"buildinfo_pkg.vhd",
]
modules = {
"local" : [
"../../top/dma_test", "../../syn/common"
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
"../../top/golden",
"../../syn/common",
],
}
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
# Do not fail during hdlmake fetch
try:
......
target = "xilinx"
action = "synthesis"
board = "spec"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_golden.xise"
syn_tool = "ise"
syn_top = "spec_golden"
syn_project = "spec_golden-150T.xise"
syn_tool = "ise"
syn_top = "spec_golden"
spec_base_ucf = ['onewire', 'spi', 'ddr3']
spec_base_ucf = ['onewire', 'spi']
board = "spec"
ctrls = ["bank3_64b_32b" ]
ctrls = ["bank3_32b_32b" ]
files = [ "buildinfo_pkg.vhd" ]
files = [
"buildinfo_pkg.vhd",
]
modules = {
"local" : [
"../../top/golden", "../../syn/common"
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
"../../top/golden",
"../../syn/common",
],
}
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
......
target = "xilinx"
action = "synthesis"
board = "spec"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_golden_wr.xise"
syn_tool = "ise"
syn_top = "spec_golden_wr"
syn_project = "spec_golden-45T.xise"
syn_tool = "ise"
syn_top = "spec_golden"
spec_base_ucf = ['onewire', 'spi', 'ddr3']
spec_base_ucf = ['wr', 'onewire', 'spi']
board = "spec"
ctrls = ["bank3_64b_32b" ]
ctrls = ["bank3_32b_32b" ]
files = [ "buildinfo_pkg.vhd" ]
files = [
"buildinfo_pkg.vhd",
]
modules = {
"local" : [
"../../top/golden_wr", "../../syn/common"
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
"../../top/golden",
"../../syn/common",
],
}
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
......
target = "xilinx"
action = "synthesis"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_golden_wr.xise"
syn_tool = "ise"
syn_top = "spec_golden_wr"
spec_base_ucf = ['wr', 'onewire', 'spi']
board = "spec"
ctrls = ["bank3_64b_32b" ]
files = [ "buildinfo_pkg.vhd" ]
modules = {
"local" : [
"../../top/golden_wr", "../../syn/common"
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
target = "xilinx"
action = "synthesis"
board = "spec"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_full.xise"
syn_tool = "ise"
syn_top = "spec_full"
syn_project = "spec_base_wr_example.xise"
syn_tool = "ise"
syn_top = "spec_base_wr_example"
spec_base_ucf = ['wr', 'onewire', 'spi', 'ddr3']
board = "spec"
ctrls = ["bank3_64b_32b" ]
ctrls = ["bank3_32b_32b" ]
files = [ "buildinfo_pkg.vhd" ]
modules = {
"local" : [
"../../top/full", "../../syn/common"
],
"../../top/wr_example",
"../../syn/common",
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
......@@ -31,6 +28,10 @@ modules = {
],
}
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
# Do not fail during hdlmake fetch
try:
......
......@@ -25,14 +25,8 @@ files = [
modules = {
"local" : [
"../../top/dma_test",
"../../top/golden",
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
# Do not fail during hdlmake fetch
......
......@@ -32,7 +32,7 @@ module main;
// 125Mhz
always #4ns clk_125m_pllref <= ~clk_125m_pllref;
spec_dma_test
spec_golden
#(
.g_SIMULATION(1)
)
......@@ -167,32 +167,6 @@ module main;
typedef virtual IGN4124PCIMaster vIGN4124PCIMaster;
task dma_read_pattern(vIGN4124PCIMaster i_gn4124);
int i;
uint64_t val, expected;
CBusAccessor acc;
acc = i_gn4124.get_accessor();
acc.set_default_xfer_size(4);
// Read pattern from device memory
dma_xfer(acc, 'h20000000, 'h0, 4 * 'h20, RD);
// Verify pattern
for (i = 'h00; i < 'h20; i++)
begin
expected = i+1;
expected |= (i+1) << 8;
expected |= (i+1) << 16;
expected |= (i+1) << 24;
i_gn4124.host_mem_read(i*4, val);
if (val != expected)
$fatal(1, "<%t> READ-BACK ERROR at host address 0x%x: expected 0x%8x, got 0x%8x",
$realtime, i*4, expected, val);
end
endtask // dma_read_pattern
task dma_test(vIGN4124PCIMaster i_gn4124,
input uint32_t word_count);
......@@ -272,8 +246,6 @@ module main;
#10us;
dma_read_pattern(vi_gn4124);
for (i = 2; i < 13; i++)
begin
#1us;
......
files = ["spec_full.vhd"]
modules = {'local': ["../../rtl"]}
This diff is collapsed.
files = ["spec_golden.vhd"]
modules = {'local': ["../../rtl"]}
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
files = [
"spec_golden.vhd",
]
modules = {
"local" : [
"../../rtl",
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
This diff is collapsed.
files = ["spec_golden_wr.vhd"]
modules = {'local': ["../../rtl"]}
This diff is collapsed.
files = ["spec_dma_test.vhd"]
files = ["spec_base_wr_example.vhd"]
modules = {'local': ["../../rtl"]}
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