Commit d5576038 authored by Tristan Gingold's avatar Tristan Gingold Committed by Federico Vaga

spec_base_wr: automatically set the g_BANK_PORT_SELECT generic.

parent 57fbbf01
...@@ -1011,10 +1011,21 @@ begin -- architecture top ...@@ -1011,10 +1011,21 @@ begin -- architecture top
-- DDR3 controller -- DDR3 controller
gen_with_ddr: if g_WITH_DDR generate gen_with_ddr: if g_WITH_DDR generate
function get_ddr3_bank_port_select return string is
begin
case g_DDR_DATA_SIZE is
when 32 => return "SPEC_BANK3_32B_32B";
when 64 => return "SPEC_BANK3_64B_32B";
when others =>
assert false report "Invalid g_DDR_DATA_SIZE" severity error;
return "error";
end case;
end get_ddr3_bank_port_select;
begin
cmp_ddr_ctrl_bank3 : entity work.ddr3_ctrl cmp_ddr_ctrl_bank3 : entity work.ddr3_ctrl
generic map( generic map(
g_RST_ACT_LOW => 0, -- active high reset (simpler internal logic) g_RST_ACT_LOW => 0, -- active high reset (simpler internal logic)
g_BANK_PORT_SELECT => "SPEC_BANK3_64B_32B", g_BANK_PORT_SELECT => get_ddr3_bank_port_select,
g_MEMCLK_PERIOD => 3000, g_MEMCLK_PERIOD => 3000,
g_SIMULATION => boolean'image(g_SIMULATION), g_SIMULATION => boolean'image(g_SIMULATION),
g_CALIB_SOFT_IP => "TRUE", g_CALIB_SOFT_IP => "TRUE",
......
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