Commit cbe5c7ee authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

spec_base_wr: disable DDR3 controller g_CALIB_SOFT_IP when running a simulation.…

spec_base_wr: disable DDR3 controller g_CALIB_SOFT_IP when running a simulation. Greatly speeds up DDR initialization process
parent c95da978
......@@ -410,6 +410,16 @@ architecture top of spec_base_wr is
attribute keep of ddr_rst : signal is "TRUE";
signal ddr_rst_n : std_logic;
impure function f_ddr3_calib_soft_ip return string is
begin
if g_SIMULATION then
return "FALSE";
else
return "TRUE";
end if;
end f_ddr3_calib_soft_ip;
begin -- architecture top
......@@ -1032,7 +1042,7 @@ begin -- architecture top
g_BANK_PORT_SELECT => get_ddr3_bank_port_select,
g_MEMCLK_PERIOD => 3000,
g_SIMULATION => boolean'image(g_SIMULATION),
g_CALIB_SOFT_IP => "TRUE",
g_CALIB_SOFT_IP => f_ddr3_calib_soft_ip,
g_P0_MASK_SIZE => g_DDR_DATA_SIZE / 8,
g_P0_DATA_PORT_SIZE => g_DDR_DATA_SIZE,
g_P0_BYTE_ADDR_WIDTH => 30,
......
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