Commit c95da978 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski

fixed DDR reset polarity

parent b3d2bfc2
......@@ -409,6 +409,8 @@ architecture top of spec_base_wr is
attribute keep of clk_333m_ddr : signal is "TRUE";
attribute keep of ddr_rst : signal is "TRUE";
signal ddr_rst_n : std_logic;
begin -- architecture top
------------------------------------------------------------------------------
......@@ -1022,6 +1024,8 @@ begin -- architecture top
end case;
end get_ddr3_bank_port_select;
begin
ddr_rst_n <= not ddr_rst;
cmp_ddr_ctrl_bank3 : entity work.ddr3_ctrl
generic map(
g_RST_ACT_LOW => 0, -- active high reset (simpler internal logic)
......@@ -1037,7 +1041,7 @@ begin -- architecture top
g_P1_BYTE_ADDR_WIDTH => 30)
port map (
clk_i => clk_333m_ddr,
rst_n_i => ddr_rst,
rst_n_i => ddr_rst_n,
status_o => ddr_status,
......
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