Commit c1b531f1 authored by Federico Vaga's avatar Federico Vaga

Merge remote-tracking branch 'origin/proposed_master' into develop

parents 18c22b53 1b48d764
...@@ -48,6 +48,8 @@ entity spec_base_wr is ...@@ -48,6 +48,8 @@ entity spec_base_wr is
g_WITH_SPI : boolean := True; g_WITH_SPI : boolean := True;
g_WITH_WR : boolean := True; g_WITH_WR : boolean := True;
g_WITH_DDR : boolean := True; g_WITH_DDR : boolean := True;
-- Size of the DDR data port in bits (32 or 64)
g_DDR_DATA_SIZE : natural := 64;
-- Address of the application meta-data. 0 if none. -- Address of the application meta-data. 0 if none.
g_APP_OFFSET : std_logic_vector(31 downto 0) := x"0000_0000"; g_APP_OFFSET : std_logic_vector(31 downto 0) := x"0000_0000";
-- Number of user interrupts -- Number of user interrupts
...@@ -225,10 +227,17 @@ entity spec_base_wr is ...@@ -225,10 +227,17 @@ entity spec_base_wr is
-- Direct access to the DDR-3 -- Direct access to the DDR-3
-- Classic wishbone -- Classic wishbone
ddr_dma_clk_i : in std_logic; ddr_dma_clk_i : in std_logic := '0';
ddr_dma_rst_n_i : in std_logic; ddr_dma_rst_n_i : in std_logic := '0';
ddr_dma_wb_i : in t_wishbone_slave_data64_in; ddr_dma_wb_cyc_i : in std_logic := '0';
ddr_dma_wb_o : out t_wishbone_slave_data64_out; ddr_dma_wb_stb_i : in std_logic := '0';
ddr_dma_wb_adr_i : in std_logic_vector(31 downto 0) := (others => '0');
ddr_dma_wb_sel_i : in std_logic_vector((g_DDR_DATA_SIZE / 8) - 1 downto 0) := (others => '0');
ddr_dma_wb_we_i : in std_logic := '0';
ddr_dma_wb_dat_i : in std_logic_vector(g_DDR_DATA_SIZE - 1 downto 0) := (others => '0');
ddr_dma_wb_ack_o : out std_logic;
ddr_dma_wb_stall_o : out std_logic;
ddr_dma_wb_dat_o : out std_logic_vector(g_DDR_DATA_SIZE - 1 downto 0);
-- DDR FIFO empty flag -- DDR FIFO empty flag
ddr_wr_fifo_empty_o : out std_logic; ddr_wr_fifo_empty_o : out std_logic;
...@@ -1009,8 +1018,8 @@ begin -- architecture top ...@@ -1009,8 +1018,8 @@ begin -- architecture top
g_MEMCLK_PERIOD => 3000, g_MEMCLK_PERIOD => 3000,
g_SIMULATION => boolean'image(g_SIMULATION), g_SIMULATION => boolean'image(g_SIMULATION),
g_CALIB_SOFT_IP => "TRUE", g_CALIB_SOFT_IP => "TRUE",
g_P0_MASK_SIZE => 8, g_P0_MASK_SIZE => g_DDR_DATA_SIZE / 8,
g_P0_DATA_PORT_SIZE => 64, g_P0_DATA_PORT_SIZE => g_DDR_DATA_SIZE,
g_P0_BYTE_ADDR_WIDTH => 30, g_P0_BYTE_ADDR_WIDTH => 30,
g_P1_MASK_SIZE => 4, g_P1_MASK_SIZE => 4,
g_P1_DATA_PORT_SIZE => 32, g_P1_DATA_PORT_SIZE => 32,
...@@ -1042,15 +1051,15 @@ begin -- architecture top ...@@ -1042,15 +1051,15 @@ begin -- architecture top
wb0_rst_n_i => ddr_dma_rst_n_i, wb0_rst_n_i => ddr_dma_rst_n_i,
wb0_clk_i => ddr_dma_clk_i, wb0_clk_i => ddr_dma_clk_i,
wb0_sel_i => ddr_dma_wb_i.sel, wb0_sel_i => ddr_dma_wb_sel_i,
wb0_cyc_i => ddr_dma_wb_i.cyc, wb0_cyc_i => ddr_dma_wb_cyc_i,
wb0_stb_i => ddr_dma_wb_i.stb, wb0_stb_i => ddr_dma_wb_stb_i,
wb0_we_i => ddr_dma_wb_i.we, wb0_we_i => ddr_dma_wb_we_i,
wb0_addr_i => ddr_dma_wb_i.adr, wb0_addr_i => ddr_dma_wb_adr_i,
wb0_data_i => ddr_dma_wb_i.dat, wb0_data_i => ddr_dma_wb_dat_i,
wb0_data_o => ddr_dma_wb_o.dat, wb0_data_o => ddr_dma_wb_dat_o,
wb0_ack_o => ddr_dma_wb_o.ack, wb0_ack_o => ddr_dma_wb_ack_o,
wb0_stall_o => ddr_dma_wb_o.stall, wb0_stall_o => ddr_dma_wb_stall_o,
p0_cmd_empty_o => open, p0_cmd_empty_o => open,
p0_cmd_full_o => open, p0_cmd_full_o => open,
...@@ -1119,12 +1128,9 @@ begin -- architecture top ...@@ -1119,12 +1128,9 @@ begin -- architecture top
ddr_reset_n_o <= '0'; ddr_reset_n_o <= '0';
ddr_we_n_o <= '0'; ddr_we_n_o <= '0';
ddr_rzq_b <= 'Z'; ddr_rzq_b <= 'Z';
ddr_dma_wb_o.dat <= (others => '0'); ddr_dma_wb_dat_o <= (others => '0');
ddr_dma_wb_o.ack <= '1'; ddr_dma_wb_ack_o <= '1';
ddr_dma_wb_o.stall <= '0'; ddr_dma_wb_stall_o <= '0';
ddr_wr_fifo_empty_o <= '0'; ddr_wr_fifo_empty_o <= '0';
end generate gen_without_ddr; end generate gen_without_ddr;
ddr_dma_wb_o.err <= '0';
ddr_dma_wb_o.rty <= '0';
end architecture top; end architecture top;
...@@ -3,8 +3,7 @@ files = ["spec_base_common.ucf"] ...@@ -3,8 +3,7 @@ files = ["spec_base_common.ucf"]
ucf_dict = {'wr': "spec_base_wr.ucf", ucf_dict = {'wr': "spec_base_wr.ucf",
'onewire': "spec_base_onewire.ucf", 'onewire': "spec_base_onewire.ucf",
'spi': "spec_base_spi.ucf", 'spi': "spec_base_spi.ucf",
'ddr3': "spec_base_ddr3.ucf", 'ddr3': "spec_base_ddr3.ucf"}
'dma': "spec_base_dma.ucf"}
for p in spec_base_ucf: for p in spec_base_ucf:
f = ucf_dict.get(p, None) f = ucf_dict.get(p, None)
......
...@@ -94,7 +94,7 @@ TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG; ...@@ -94,7 +94,7 @@ TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
# Cross-clock domain sync # Cross-clock domain sync
#---------------------------------------- #----------------------------------------
NET "inst_spec_base/clk_ddr_333m" TNM_NET = ddr_clk; NET "inst_spec_base/clk_333m_ddr" TNM_NET = ddr_clk;
NET "inst_spec_base/*cmp_ddr_ctrl_bank3/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_clk; NET "inst_spec_base/*cmp_ddr_ctrl_bank3/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_clk;
NET "inst_spec_base/*cmp_ddr_ctrl_bank3/*/memc3_mcb_raw_wrapper_inst/ioi_drp_clk" TNM_NET = ddr_clk; NET "inst_spec_base/*cmp_ddr_ctrl_bank3/*/memc3_mcb_raw_wrapper_inst/ioi_drp_clk" TNM_NET = ddr_clk;
...@@ -110,3 +110,20 @@ NET "inst_spec_base/*cmp_ddr_ctrl_bank3/*/memc3_mcb_raw_wrapper_inst/ioi_drp_clk ...@@ -110,3 +110,20 @@ NET "inst_spec_base/*cmp_ddr_ctrl_bank3/*/memc3_mcb_raw_wrapper_inst/ioi_drp_clk
#TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr_sync_reg" 3ns DATAPATHONLY; #TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr_sync_reg" 3ns DATAPATHONLY;
#TIMESPEC TS_ddr_sync_word = FROM sync_word TO ddr_clk 9ns DATAPATHONLY; #TIMESPEC TS_ddr_sync_word = FROM sync_word TO ddr_clk 9ns DATAPATHONLY;
#---------------------------------------
# DMA
#---------------------------------------
NET "inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma.cmp_dma_controller/dma_async_*" TNM = FFS "dma_ffs";
TIMESPEC TS_dma_async_ffs = FROM dma_ffs TO pci_clk 15ns DATAPATHONLY;
# Exceptions for crossings via gc_sync_word_* (3x multicycle)
NET "*/gc_sync_word_data[*]" TNM = FFS "sync_word";
TIMESPEC TS_sys_sync_word = FROM sync_word TO sys_clk 48ns DATAPATHONLY;
TIMESPEC TS_ref_sync_word = FROM sync_word TO ref_clk 24ns DATAPATHONLY;
# no gc_sync_word used in GN4124
#TIMESPEC TS_pci_sync_word = FROM sync_word TO pci_clk 15ns DATAPATHONLY;
...@@ -13,6 +13,7 @@ syn_project = "spec_full.xise" ...@@ -13,6 +13,7 @@ syn_project = "spec_full.xise"
syn_tool = "ise" syn_tool = "ise"
syn_top = "spec_full" syn_top = "spec_full"
spec_base_ucf = ['wr', 'onewire', 'spi', 'ddr3']
board = "spec" board = "spec"
ctrls = ["bank3_64b_32b" ] ctrls = ["bank3_64b_32b" ]
...@@ -20,7 +21,7 @@ files = [ "buildinfo_pkg.vhd" ] ...@@ -20,7 +21,7 @@ files = [ "buildinfo_pkg.vhd" ]
modules = { modules = {
"local" : [ "local" : [
"../../top/full", "../../top/full", "../../syn/common"
], ],
"git" : [ "git" : [
"https://ohwr.org/project/wr-cores.git", "https://ohwr.org/project/wr-cores.git",
......
...@@ -13,6 +13,7 @@ syn_project = "spec_golden_wr.xise" ...@@ -13,6 +13,7 @@ syn_project = "spec_golden_wr.xise"
syn_tool = "ise" syn_tool = "ise"
syn_top = "spec_golden_wr" syn_top = "spec_golden_wr"
spec_base_ucf = ['wr', 'onewire', 'spi']
board = "spec" board = "spec"
ctrls = ["bank3_64b_32b" ] ctrls = ["bank3_64b_32b" ]
...@@ -20,7 +21,7 @@ files = [ "buildinfo_pkg.vhd" ] ...@@ -20,7 +21,7 @@ files = [ "buildinfo_pkg.vhd" ]
modules = { modules = {
"local" : [ "local" : [
"../../top/golden_wr", "../../top/golden_wr", "../../syn/common"
], ],
"git" : [ "git" : [
"https://ohwr.org/project/wr-cores.git", "https://ohwr.org/project/wr-cores.git",
......
files = ["spec_full.vhd", "spec_full.ucf"] files = ["spec_full.vhd"]
modules = {'local': ["../../rtl"]} modules = {'local': ["../../rtl"]}
This diff is collapsed.
...@@ -34,7 +34,7 @@ entity spec_full is ...@@ -34,7 +34,7 @@ entity spec_full is
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and -- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench. -- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations. -- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_SIMULATION : integer := 0 g_SIMULATION : boolean := False
); );
port ( port (
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
...@@ -48,34 +48,34 @@ entity spec_full is ...@@ -48,34 +48,34 @@ entity spec_full is
-- GN4124 PCIe bridge signals -- GN4124 PCIe bridge signals
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
-- From GN4124 Local bus -- From GN4124 Local bus
gn_rst_n : in std_logic; -- Reset from GN4124 (RSTOUT18_N) gn_rst_n_i : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- PCIe to Local [Inbound Data] - RX -- PCIe to Local [Inbound Data] - RX
gn_p2l_clk_n : in std_logic; -- Receiver Source Synchronous Clock- gn_p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
gn_p2l_clk_p : in std_logic; -- Receiver Source Synchronous Clock+ gn_p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
gn_p2l_rdy : out std_logic; -- Rx Buffer Full Flag gn_p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
gn_p2l_dframe : in std_logic; -- Receive Frame gn_p2l_dframe_i : in std_logic; -- Receive Frame
gn_p2l_valid : in std_logic; -- Receive Data Valid gn_p2l_valid_i : in std_logic; -- Receive Data Valid
gn_p2l_data : in std_logic_vector(15 downto 0); -- Parallel receive data gn_p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
-- Inbound Buffer Request/Status -- Inbound Buffer Request/Status
gn_p_wr_req : in std_logic_vector(1 downto 0); -- PCIe Write Request gn_p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
gn_p_wr_rdy : out std_logic_vector(1 downto 0); -- PCIe Write Ready gn_p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
gn_rx_error : out std_logic; -- Receive Error gn_rx_error_o : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX -- Local to Parallel [Outbound Data] - TX
gn_l2p_clk_n : out std_logic; -- Transmitter Source Synchronous Clock- gn_l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
gn_l2p_clk_p : out std_logic; -- Transmitter Source Synchronous Clock+ gn_l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
gn_l2p_dframe : out std_logic; -- Transmit Data Frame gn_l2p_dframe_o : out std_logic; -- Transmit Data Frame
gn_l2p_valid : out std_logic; -- Transmit Data Valid gn_l2p_valid_o : out std_logic; -- Transmit Data Valid
gn_l2p_edb : out std_logic; -- Packet termination and discard gn_l2p_edb_o : out std_logic; -- Packet termination and discard
gn_l2p_data : out std_logic_vector(15 downto 0); -- Parallel transmit data gn_l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
-- Outbound Buffer Status -- Outbound Buffer Status
gn_l2p_rdy : in std_logic; -- Tx Buffer Full Flag gn_l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
gn_l_wr_rdy : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write gn_l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
gn_p_rd_d_rdy : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready gn_p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
gn_tx_error : in std_logic; -- Transmit Error gn_tx_error_i : in std_logic; -- Transmit Error
gn_vc_rdy : in std_logic_vector(1 downto 0); -- Channel ready gn_vc_rdy_i : in std_logic_vector(1 downto 0); -- Channel ready
-- General Purpose Interface -- General Purpose Interface
gn_gpio : inout std_logic_vector(1 downto 0); -- gn_gpio[0] -> GN4124 GPIO8 gn_gpio_b : inout std_logic_vector(1 downto 0); -- gn_gpio[0] -> GN4124 GPIO8
-- gn_gpio[1] -> GN4124 GPIO9 -- gn_gpio[1] -> GN4124 GPIO9
-- I2C interface for accessing FMC EEPROM. -- I2C interface for accessing FMC EEPROM.
fmc0_scl_b : inout std_logic; fmc0_scl_b : inout std_logic;
...@@ -112,7 +112,7 @@ entity spec_full is ...@@ -112,7 +112,7 @@ entity spec_full is
-- Green LED next to the SFP: indicates if the link is up. -- Green LED next to the SFP: indicates if the link is up.
led_link_o : out std_logic; led_link_o : out std_logic;
button1_i : in std_logic; button1_n_i : in std_logic;
--------------------------------------------------------------------------- ---------------------------------------------------------------------------
-- UART -- UART
...@@ -181,7 +181,7 @@ architecture top of spec_full is ...@@ -181,7 +181,7 @@ architecture top of spec_full is
signal gn_wb_out : t_wishbone_master_out; signal gn_wb_out : t_wishbone_master_out;
signal gn_wb_in : t_wishbone_master_in; signal gn_wb_in : t_wishbone_master_in;
begin begin
inst_template: entity work.spec_template_wr inst_spec_base: entity work.spec_base_wr
generic map ( generic map (
g_with_vic => True, g_with_vic => True,
g_with_onewire => False, g_with_onewire => False,
...@@ -193,28 +193,28 @@ begin ...@@ -193,28 +193,28 @@ begin
port map ( port map (
clk_125m_pllref_p_i => clk_125m_pllref_p_i, clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i, clk_125m_pllref_n_i => clk_125m_pllref_n_i,
gn_rst_n_i => gn_rst_n, gn_rst_n_i => gn_rst_n_i,
gn_p2l_clk_n_i => gn_p2l_clk_n, gn_p2l_clk_n_i => gn_p2l_clk_n_i,
gn_p2l_clk_p_i => gn_p2l_clk_p, gn_p2l_clk_p_i => gn_p2l_clk_p_i,
gn_p2l_rdy_o => gn_p2l_rdy, gn_p2l_rdy_o => gn_p2l_rdy_o,
gn_p2l_dframe_i => gn_p2l_dframe, gn_p2l_dframe_i => gn_p2l_dframe_i,
gn_p2l_valid_i => gn_p2l_valid, gn_p2l_valid_i => gn_p2l_valid_i,
gn_p2l_data_i => gn_p2l_data, gn_p2l_data_i => gn_p2l_data_i,
gn_p_wr_req_i => gn_p_wr_req, gn_p_wr_req_i => gn_p_wr_req_i,
gn_p_wr_rdy_o => gn_p_wr_rdy, gn_p_wr_rdy_o => gn_p_wr_rdy_o,
gn_rx_error_o => gn_rx_error, gn_rx_error_o => gn_rx_error_o,
gn_l2p_clk_n_o => gn_l2p_clk_n, gn_l2p_clk_n_o => gn_l2p_clk_n_o,
gn_l2p_clk_p_o => gn_l2p_clk_p, gn_l2p_clk_p_o => gn_l2p_clk_p_o,
gn_l2p_dframe_o => gn_l2p_dframe, gn_l2p_dframe_o => gn_l2p_dframe_o,
gn_l2p_valid_o => gn_l2p_valid, gn_l2p_valid_o => gn_l2p_valid_o,
gn_l2p_edb_o => gn_l2p_edb, gn_l2p_edb_o => gn_l2p_edb_o,
gn_l2p_data_o => gn_l2p_data, gn_l2p_data_o => gn_l2p_data_o,
gn_l2p_rdy_i => gn_l2p_rdy, gn_l2p_rdy_i => gn_l2p_rdy_i,
gn_l_wr_rdy_i => gn_l_wr_rdy, gn_l_wr_rdy_i => gn_l_wr_rdy_i,
gn_p_rd_d_rdy_i => gn_p_rd_d_rdy, gn_p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
gn_tx_error_i => gn_tx_error, gn_tx_error_i => gn_tx_error_i,
gn_vc_rdy_i => gn_vc_rdy, gn_vc_rdy_i => gn_vc_rdy_i,
gn_gpio_b => gn_gpio, gn_gpio_b => gn_gpio_b,
fmc0_scl_b => fmc0_scl_b, fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b, fmc0_sda_b => fmc0_sda_b,
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i, fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
...@@ -226,7 +226,7 @@ begin ...@@ -226,7 +226,7 @@ begin
pcbrev_i => pcbrev_i, pcbrev_i => pcbrev_i,
led_act_o => led_act_o, led_act_o => led_act_o,
led_link_o => led_link_o, led_link_o => led_link_o,
button1_i => button1_i, button1_n_i => button1_n_i,
uart_rxd_i => uart_rxd_i, uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o, uart_txd_o => uart_txd_o,
clk_20m_vcxo_i => clk_20m_vcxo_i, clk_20m_vcxo_i => clk_20m_vcxo_i,
...@@ -268,16 +268,9 @@ begin ...@@ -268,16 +268,9 @@ begin
ddr_dma_clk_i => clk_sys_62m5, ddr_dma_clk_i => clk_sys_62m5,
ddr_dma_rst_n_i => rst_sys_62m5_n, ddr_dma_rst_n_i => rst_sys_62m5_n,
ddr_dma_wb_i.cyc => '0',
ddr_dma_wb_i.stb => '0',
ddr_dma_wb_i.adr => x"0000_0000",
ddr_dma_wb_i.sel => x"00",
ddr_dma_wb_i.we => '0',
ddr_dma_wb_i.dat => x"0000_0000_0000_0000",
ddr_dma_wb_o => open,
clk_sys_62m5_o => clk_sys_62m5, clk_62m5_sys_o => clk_sys_62m5,
rst_sys_62m5_n_o => rst_sys_62m5_n, rst_62m5_sys_n_o => rst_sys_62m5_n,
-- Everything is handled by the carrier. -- Everything is handled by the carrier.
app_wb_o => gn_wb_out, app_wb_o => gn_wb_out,
......
...@@ -143,13 +143,6 @@ begin ...@@ -143,13 +143,6 @@ begin
ddr_dma_clk_i => clk_sys_62m5, ddr_dma_clk_i => clk_sys_62m5,
ddr_dma_rst_n_i => rst_sys_62m5_n, ddr_dma_rst_n_i => rst_sys_62m5_n,
ddr_dma_wb_i.cyc => '0',
ddr_dma_wb_i.stb => '0',
ddr_dma_wb_i.adr => x"0000_0000",
ddr_dma_wb_i.sel => x"00",
ddr_dma_wb_i.we => '0',
ddr_dma_wb_i.dat => x"0000_0000_0000_0000",
ddr_dma_wb_o => open,
clk_62m5_sys_o => clk_sys_62m5, clk_62m5_sys_o => clk_sys_62m5,
rst_62m5_sys_n_o => rst_sys_62m5_n, rst_62m5_sys_n_o => rst_sys_62m5_n,
......
...@@ -230,13 +230,6 @@ begin ...@@ -230,13 +230,6 @@ begin
ddr_dma_clk_i => clk_sys_62m5, ddr_dma_clk_i => clk_sys_62m5,
ddr_dma_rst_n_i => rst_sys_62m5_n, ddr_dma_rst_n_i => rst_sys_62m5_n,
ddr_dma_wb_i.cyc => '0',
ddr_dma_wb_i.stb => '0',
ddr_dma_wb_i.adr => x"0000_0000",
ddr_dma_wb_i.sel => x"00",
ddr_dma_wb_i.we => '0',
ddr_dma_wb_i.dat => x"0000_0000_0000_0000",
ddr_dma_wb_o => open,
clk_62m5_sys_o => clk_sys_62m5, clk_62m5_sys_o => clk_sys_62m5,
rst_62m5_sys_n_o => rst_sys_62m5_n, rst_62m5_sys_n_o => rst_sys_62m5_n,
......
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