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Simple PCIe FMC carrier SPEC
Commits
c1b531f1
Commit
c1b531f1
authored
Sep 09, 2019
by
Federico Vaga
Browse files
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Merge remote-tracking branch 'origin/proposed_master' into develop
parents
18c22b53
1b48d764
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Showing
10 changed files
with
102 additions
and
474 deletions
+102
-474
spec_base_wr.vhd
hdl/rtl/spec_base_wr.vhd
+27
-21
Manifest.py
hdl/syn/common/Manifest.py
+1
-2
spec_base_ddr3.ucf
hdl/syn/common/spec_base_ddr3.ucf
+18
-1
Manifest.py
hdl/syn/full/Manifest.py
+2
-1
Manifest.py
hdl/syn/golden_wr-150T/Manifest.py
+2
-1
Manifest.py
hdl/top/full/Manifest.py
+1
-1
spec_full.ucf
hdl/top/full/spec_full.ucf
+0
-375
spec_full.vhd
hdl/top/full/spec_full.vhd
+51
-58
spec_golden.vhd
hdl/top/golden/spec_golden.vhd
+0
-7
spec_golden_wr.vhd
hdl/top/golden_wr/spec_golden_wr.vhd
+0
-7
No files found.
hdl/rtl/spec_base_wr.vhd
View file @
c1b531f1
...
...
@@ -48,6 +48,8 @@ entity spec_base_wr is
g_WITH_SPI
:
boolean
:
=
True
;
g_WITH_WR
:
boolean
:
=
True
;
g_WITH_DDR
:
boolean
:
=
True
;
-- Size of the DDR data port in bits (32 or 64)
g_DDR_DATA_SIZE
:
natural
:
=
64
;
-- Address of the application meta-data. 0 if none.
g_APP_OFFSET
:
std_logic_vector
(
31
downto
0
)
:
=
x"0000_0000"
;
-- Number of user interrupts
...
...
@@ -225,10 +227,17 @@ entity spec_base_wr is
-- Direct access to the DDR-3
-- Classic wishbone
ddr_dma_clk_i
:
in
std_logic
;
ddr_dma_rst_n_i
:
in
std_logic
;
ddr_dma_wb_i
:
in
t_wishbone_slave_data64_in
;
ddr_dma_wb_o
:
out
t_wishbone_slave_data64_out
;
ddr_dma_clk_i
:
in
std_logic
:
=
'0'
;
ddr_dma_rst_n_i
:
in
std_logic
:
=
'0'
;
ddr_dma_wb_cyc_i
:
in
std_logic
:
=
'0'
;
ddr_dma_wb_stb_i
:
in
std_logic
:
=
'0'
;
ddr_dma_wb_adr_i
:
in
std_logic_vector
(
31
downto
0
)
:
=
(
others
=>
'0'
);
ddr_dma_wb_sel_i
:
in
std_logic_vector
((
g_DDR_DATA_SIZE
/
8
)
-
1
downto
0
)
:
=
(
others
=>
'0'
);
ddr_dma_wb_we_i
:
in
std_logic
:
=
'0'
;
ddr_dma_wb_dat_i
:
in
std_logic_vector
(
g_DDR_DATA_SIZE
-
1
downto
0
)
:
=
(
others
=>
'0'
);
ddr_dma_wb_ack_o
:
out
std_logic
;
ddr_dma_wb_stall_o
:
out
std_logic
;
ddr_dma_wb_dat_o
:
out
std_logic_vector
(
g_DDR_DATA_SIZE
-
1
downto
0
);
-- DDR FIFO empty flag
ddr_wr_fifo_empty_o
:
out
std_logic
;
...
...
@@ -1009,8 +1018,8 @@ begin -- architecture top
g_MEMCLK_PERIOD
=>
3000
,
g_SIMULATION
=>
boolean
'image
(
g_SIMULATION
),
g_CALIB_SOFT_IP
=>
"TRUE"
,
g_P0_MASK_SIZE
=>
8
,
g_P0_DATA_PORT_SIZE
=>
64
,
g_P0_MASK_SIZE
=>
g_DDR_DATA_SIZE
/
8
,
g_P0_DATA_PORT_SIZE
=>
g_DDR_DATA_SIZE
,
g_P0_BYTE_ADDR_WIDTH
=>
30
,
g_P1_MASK_SIZE
=>
4
,
g_P1_DATA_PORT_SIZE
=>
32
,
...
...
@@ -1042,15 +1051,15 @@ begin -- architecture top
wb0_rst_n_i
=>
ddr_dma_rst_n_i
,
wb0_clk_i
=>
ddr_dma_clk_i
,
wb0_sel_i
=>
ddr_dma_wb_
i
.
sel
,
wb0_cyc_i
=>
ddr_dma_wb_
i
.
cyc
,
wb0_stb_i
=>
ddr_dma_wb_
i
.
stb
,
wb0_we_i
=>
ddr_dma_wb_
i
.
we
,
wb0_addr_i
=>
ddr_dma_wb_
i
.
adr
,
wb0_data_i
=>
ddr_dma_wb_
i
.
dat
,
wb0_data_o
=>
ddr_dma_wb_
o
.
dat
,
wb0_ack_o
=>
ddr_dma_wb_
o
.
ack
,
wb0_stall_o
=>
ddr_dma_wb_
o
.
stall
,
wb0_sel_i
=>
ddr_dma_wb_
sel_i
,
wb0_cyc_i
=>
ddr_dma_wb_
cyc_i
,
wb0_stb_i
=>
ddr_dma_wb_
stb_i
,
wb0_we_i
=>
ddr_dma_wb_
we_i
,
wb0_addr_i
=>
ddr_dma_wb_
adr_i
,
wb0_data_i
=>
ddr_dma_wb_
dat_i
,
wb0_data_o
=>
ddr_dma_wb_
dat_o
,
wb0_ack_o
=>
ddr_dma_wb_
ack_o
,
wb0_stall_o
=>
ddr_dma_wb_
stall_o
,
p0_cmd_empty_o
=>
open
,
p0_cmd_full_o
=>
open
,
...
...
@@ -1119,12 +1128,9 @@ begin -- architecture top
ddr_reset_n_o
<=
'0'
;
ddr_we_n_o
<=
'0'
;
ddr_rzq_b
<=
'Z'
;
ddr_dma_wb_
o
.
dat
<=
(
others
=>
'0'
);
ddr_dma_wb_
o
.
ack
<=
'1'
;
ddr_dma_wb_
o
.
stall
<=
'0'
;
ddr_dma_wb_
dat_o
<=
(
others
=>
'0'
);
ddr_dma_wb_
ack_o
<=
'1'
;
ddr_dma_wb_
stall_o
<=
'0'
;
ddr_wr_fifo_empty_o
<=
'0'
;
end
generate
gen_without_ddr
;
ddr_dma_wb_o
.
err
<=
'0'
;
ddr_dma_wb_o
.
rty
<=
'0'
;
end
architecture
top
;
hdl/syn/common/Manifest.py
View file @
c1b531f1
...
...
@@ -3,8 +3,7 @@ files = ["spec_base_common.ucf"]
ucf_dict
=
{
'wr'
:
"spec_base_wr.ucf"
,
'onewire'
:
"spec_base_onewire.ucf"
,
'spi'
:
"spec_base_spi.ucf"
,
'ddr3'
:
"spec_base_ddr3.ucf"
,
'dma'
:
"spec_base_dma.ucf"
}
'ddr3'
:
"spec_base_ddr3.ucf"
}
for
p
in
spec_base_ucf
:
f
=
ucf_dict
.
get
(
p
,
None
)
...
...
hdl/syn/common/spec_base_ddr3.ucf
View file @
c1b531f1
...
...
@@ -94,7 +94,7 @@ TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
# Cross-clock domain sync
#----------------------------------------
NET "inst_spec_base/clk_
ddr_333m
" TNM_NET = ddr_clk;
NET "inst_spec_base/clk_
333m_ddr
" TNM_NET = ddr_clk;
NET "inst_spec_base/*cmp_ddr_ctrl_bank3/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_clk;
NET "inst_spec_base/*cmp_ddr_ctrl_bank3/*/memc3_mcb_raw_wrapper_inst/ioi_drp_clk" TNM_NET = ddr_clk;
...
...
@@ -110,3 +110,20 @@ NET "inst_spec_base/*cmp_ddr_ctrl_bank3/*/memc3_mcb_raw_wrapper_inst/ioi_drp_clk
#TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr_sync_reg" 3ns DATAPATHONLY;
#TIMESPEC TS_ddr_sync_word = FROM sync_word TO ddr_clk 9ns DATAPATHONLY;
#---------------------------------------
# DMA
#---------------------------------------
NET "inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma.cmp_dma_controller/dma_async_*" TNM = FFS "dma_ffs";
TIMESPEC TS_dma_async_ffs = FROM dma_ffs TO pci_clk 15ns DATAPATHONLY;
# Exceptions for crossings via gc_sync_word_* (3x multicycle)
NET "*/gc_sync_word_data[*]" TNM = FFS "sync_word";
TIMESPEC TS_sys_sync_word = FROM sync_word TO sys_clk 48ns DATAPATHONLY;
TIMESPEC TS_ref_sync_word = FROM sync_word TO ref_clk 24ns DATAPATHONLY;
# no gc_sync_word used in GN4124
#TIMESPEC TS_pci_sync_word = FROM sync_word TO pci_clk 15ns DATAPATHONLY;
hdl/syn/full/Manifest.py
View file @
c1b531f1
...
...
@@ -13,6 +13,7 @@ syn_project = "spec_full.xise"
syn_tool
=
"ise"
syn_top
=
"spec_full"
spec_base_ucf
=
[
'wr'
,
'onewire'
,
'spi'
,
'ddr3'
]
board
=
"spec"
ctrls
=
[
"bank3_64b_32b"
]
...
...
@@ -20,7 +21,7 @@ files = [ "buildinfo_pkg.vhd" ]
modules
=
{
"local"
:
[
"../../top/full"
,
"../../top/full"
,
"../../syn/common"
],
"git"
:
[
"https://ohwr.org/project/wr-cores.git"
,
...
...
hdl/syn/golden_wr-150T/Manifest.py
View file @
c1b531f1
...
...
@@ -13,6 +13,7 @@ syn_project = "spec_golden_wr.xise"
syn_tool
=
"ise"
syn_top
=
"spec_golden_wr"
spec_base_ucf
=
[
'wr'
,
'onewire'
,
'spi'
]
board
=
"spec"
ctrls
=
[
"bank3_64b_32b"
]
...
...
@@ -20,7 +21,7 @@ files = [ "buildinfo_pkg.vhd" ]
modules
=
{
"local"
:
[
"../../top/golden_wr"
,
"../../top/golden_wr"
,
"../../syn/common"
],
"git"
:
[
"https://ohwr.org/project/wr-cores.git"
,
...
...
hdl/top/full/Manifest.py
View file @
c1b531f1
files
=
[
"spec_full.vhd"
,
"spec_full.ucf"
]
files
=
[
"spec_full.vhd"
]
modules
=
{
'local'
:
[
"../../rtl"
]}
hdl/top/full/spec_full.ucf
deleted
100644 → 0
View file @
18c22b53
This diff is collapsed.
Click to expand it.
hdl/top/full/spec_full.vhd
View file @
c1b531f1
...
...
@@ -34,7 +34,7 @@ entity spec_full is
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_SIMULATION
:
integer
:
=
0
g_SIMULATION
:
boolean
:
=
False
);
port
(
---------------------------------------------------------------------------
...
...
@@ -48,34 +48,34 @@ entity spec_full is
-- GN4124 PCIe bridge signals
---------------------------------------------------------------------------
-- From GN4124 Local bus
gn_rst_n
:
in
std_logic
;
-- Reset from GN4124 (RSTOUT18_N)
gn_rst_n
_i
:
in
std_logic
;
-- Reset from GN4124 (RSTOUT18_N)
-- PCIe to Local [Inbound Data] - RX
gn_p2l_clk_n
:
in
std_logic
;
-- Receiver Source Synchronous Clock-
gn_p2l_clk_p
:
in
std_logic
;
-- Receiver Source Synchronous Clock+
gn_p2l_rdy
:
out
std_logic
;
-- Rx Buffer Full Flag
gn_p2l_dframe
:
in
std_logic
;
-- Receive Frame
gn_p2l_valid
:
in
std_logic
;
-- Receive Data Valid
gn_p2l_data
:
in
std_logic_vector
(
15
downto
0
);
-- Parallel receive data
gn_p2l_clk_n
_i
:
in
std_logic
;
-- Receiver Source Synchronous Clock-
gn_p2l_clk_p
_i
:
in
std_logic
;
-- Receiver Source Synchronous Clock+
gn_p2l_rdy
_o
:
out
std_logic
;
-- Rx Buffer Full Flag
gn_p2l_dframe
_i
:
in
std_logic
;
-- Receive Frame
gn_p2l_valid
_i
:
in
std_logic
;
-- Receive Data Valid
gn_p2l_data
_i
:
in
std_logic_vector
(
15
downto
0
);
-- Parallel receive data
-- Inbound Buffer Request/Status
gn_p_wr_req
:
in
std_logic_vector
(
1
downto
0
);
-- PCIe Write Request
gn_p_wr_rdy
:
out
std_logic_vector
(
1
downto
0
);
-- PCIe Write Ready
gn_rx_error
:
out
std_logic
;
-- Receive Error
gn_p_wr_req
_i
:
in
std_logic_vector
(
1
downto
0
);
-- PCIe Write Request
gn_p_wr_rdy
_o
:
out
std_logic_vector
(
1
downto
0
);
-- PCIe Write Ready
gn_rx_error
_o
:
out
std_logic
;
-- Receive Error
-- Local to Parallel [Outbound Data] - TX
gn_l2p_clk_n
:
out
std_logic
;
-- Transmitter Source Synchronous Clock-
gn_l2p_clk_p
:
out
std_logic
;
-- Transmitter Source Synchronous Clock+
gn_l2p_dframe
:
out
std_logic
;
-- Transmit Data Frame
gn_l2p_valid
:
out
std_logic
;
-- Transmit Data Valid
gn_l2p_edb
:
out
std_logic
;
-- Packet termination and discard
gn_l2p_data
:
out
std_logic_vector
(
15
downto
0
);
-- Parallel transmit data
gn_l2p_clk_n
_o
:
out
std_logic
;
-- Transmitter Source Synchronous Clock-
gn_l2p_clk_p
_o
:
out
std_logic
;
-- Transmitter Source Synchronous Clock+
gn_l2p_dframe
_o
:
out
std_logic
;
-- Transmit Data Frame
gn_l2p_valid
_o
:
out
std_logic
;
-- Transmit Data Valid
gn_l2p_edb
_o
:
out
std_logic
;
-- Packet termination and discard
gn_l2p_data
_o
:
out
std_logic_vector
(
15
downto
0
);
-- Parallel transmit data
-- Outbound Buffer Status
gn_l2p_rdy
:
in
std_logic
;
-- Tx Buffer Full Flag
gn_l_wr_rdy
:
in
std_logic_vector
(
1
downto
0
);
-- Local-to-PCIe Write
gn_p_rd_d_rdy
:
in
std_logic_vector
(
1
downto
0
);
-- PCIe-to-Local Read Response Data Ready
gn_tx_error
:
in
std_logic
;
-- Transmit Error
gn_vc_rdy
:
in
std_logic_vector
(
1
downto
0
);
-- Channel ready
gn_l2p_rdy
_i
:
in
std_logic
;
-- Tx Buffer Full Flag
gn_l_wr_rdy
_i
:
in
std_logic_vector
(
1
downto
0
);
-- Local-to-PCIe Write
gn_p_rd_d_rdy
_i
:
in
std_logic_vector
(
1
downto
0
);
-- PCIe-to-Local Read Response Data Ready
gn_tx_error
_i
:
in
std_logic
;
-- Transmit Error
gn_vc_rdy
_i
:
in
std_logic_vector
(
1
downto
0
);
-- Channel ready
-- General Purpose Interface
gn_gpio
:
inout
std_logic_vector
(
1
downto
0
);
-- gn_gpio[0] -> GN4124 GPIO8
-- gn_gpio[1] -> GN4124 GPIO9
gn_gpio
_b
:
inout
std_logic_vector
(
1
downto
0
);
-- gn_gpio[0] -> GN4124 GPIO8
-- gn_gpio[1] -> GN4124 GPIO9
-- I2C interface for accessing FMC EEPROM.
fmc0_scl_b
:
inout
std_logic
;
...
...
@@ -112,7 +112,7 @@ entity spec_full is
-- Green LED next to the SFP: indicates if the link is up.
led_link_o
:
out
std_logic
;
button1_i
:
in
std_logic
;
button1_
n_
i
:
in
std_logic
;
---------------------------------------------------------------------------
-- UART
...
...
@@ -181,7 +181,7 @@ architecture top of spec_full is
signal
gn_wb_out
:
t_wishbone_master_out
;
signal
gn_wb_in
:
t_wishbone_master_in
;
begin
inst_
template
:
entity
work
.
spec_templat
e_wr
inst_
spec_base
:
entity
work
.
spec_bas
e_wr
generic
map
(
g_with_vic
=>
True
,
g_with_onewire
=>
False
,
...
...
@@ -193,28 +193,28 @@ begin
port
map
(
clk_125m_pllref_p_i
=>
clk_125m_pllref_p_i
,
clk_125m_pllref_n_i
=>
clk_125m_pllref_n_i
,
gn_rst_n_i
=>
gn_rst_n
,
gn_p2l_clk_n_i
=>
gn_p2l_clk_n
,
gn_p2l_clk_p_i
=>
gn_p2l_clk_p
,
gn_p2l_rdy_o
=>
gn_p2l_rdy
,
gn_p2l_dframe_i
=>
gn_p2l_dframe
,
gn_p2l_valid_i
=>
gn_p2l_valid
,
gn_p2l_data_i
=>
gn_p2l_data
,
gn_p_wr_req_i
=>
gn_p_wr_req
,
gn_p_wr_rdy_o
=>
gn_p_wr_rdy
,
gn_rx_error_o
=>
gn_rx_error
,
gn_l2p_clk_n_o
=>
gn_l2p_clk_n
,
gn_l2p_clk_p_o
=>
gn_l2p_clk_p
,
gn_l2p_dframe_o
=>
gn_l2p_dframe
,
gn_l2p_valid_o
=>
gn_l2p_valid
,
gn_l2p_edb_o
=>
gn_l2p_edb
,
gn_l2p_data_o
=>
gn_l2p_data
,
gn_l2p_rdy_i
=>
gn_l2p_rdy
,
gn_l_wr_rdy_i
=>
gn_l_wr_rdy
,
gn_p_rd_d_rdy_i
=>
gn_p_rd_d_rdy
,
gn_tx_error_i
=>
gn_tx_error
,
gn_vc_rdy_i
=>
gn_vc_rdy
,
gn_gpio_b
=>
gn_gpio
,
gn_rst_n_i
=>
gn_rst_n
_i
,
gn_p2l_clk_n_i
=>
gn_p2l_clk_n
_i
,
gn_p2l_clk_p_i
=>
gn_p2l_clk_p
_i
,
gn_p2l_rdy_o
=>
gn_p2l_rdy
_o
,
gn_p2l_dframe_i
=>
gn_p2l_dframe
_i
,
gn_p2l_valid_i
=>
gn_p2l_valid
_i
,
gn_p2l_data_i
=>
gn_p2l_data
_i
,
gn_p_wr_req_i
=>
gn_p_wr_req
_i
,
gn_p_wr_rdy_o
=>
gn_p_wr_rdy
_o
,
gn_rx_error_o
=>
gn_rx_error
_o
,
gn_l2p_clk_n_o
=>
gn_l2p_clk_n
_o
,
gn_l2p_clk_p_o
=>
gn_l2p_clk_p
_o
,
gn_l2p_dframe_o
=>
gn_l2p_dframe
_o
,
gn_l2p_valid_o
=>
gn_l2p_valid
_o
,
gn_l2p_edb_o
=>
gn_l2p_edb
_o
,
gn_l2p_data_o
=>
gn_l2p_data
_o
,
gn_l2p_rdy_i
=>
gn_l2p_rdy
_i
,
gn_l_wr_rdy_i
=>
gn_l_wr_rdy
_i
,
gn_p_rd_d_rdy_i
=>
gn_p_rd_d_rdy
_i
,
gn_tx_error_i
=>
gn_tx_error
_i
,
gn_vc_rdy_i
=>
gn_vc_rdy
_i
,
gn_gpio_b
=>
gn_gpio
_b
,
fmc0_scl_b
=>
fmc0_scl_b
,
fmc0_sda_b
=>
fmc0_sda_b
,
fmc0_prsnt_m2c_n_i
=>
fmc0_prsnt_m2c_n_i
,
...
...
@@ -226,7 +226,7 @@ begin
pcbrev_i
=>
pcbrev_i
,
led_act_o
=>
led_act_o
,
led_link_o
=>
led_link_o
,
button1_
i
=>
button1
_i
,
button1_
n_i
=>
button1_n
_i
,
uart_rxd_i
=>
uart_rxd_i
,
uart_txd_o
=>
uart_txd_o
,
clk_20m_vcxo_i
=>
clk_20m_vcxo_i
,
...
...
@@ -268,16 +268,9 @@ begin
ddr_dma_clk_i
=>
clk_sys_62m5
,
ddr_dma_rst_n_i
=>
rst_sys_62m5_n
,
ddr_dma_wb_i
.
cyc
=>
'0'
,
ddr_dma_wb_i
.
stb
=>
'0'
,
ddr_dma_wb_i
.
adr
=>
x"0000_0000"
,
ddr_dma_wb_i
.
sel
=>
x"00"
,
ddr_dma_wb_i
.
we
=>
'0'
,
ddr_dma_wb_i
.
dat
=>
x"0000_0000_0000_0000"
,
ddr_dma_wb_o
=>
open
,
clk_
sys_62m5
_o
=>
clk_sys_62m5
,
rst_
sys_62m5
_n_o
=>
rst_sys_62m5_n
,
clk_
62m5_sys
_o
=>
clk_sys_62m5
,
rst_
62m5_sys
_n_o
=>
rst_sys_62m5_n
,
-- Everything is handled by the carrier.
app_wb_o
=>
gn_wb_out
,
...
...
hdl/top/golden/spec_golden.vhd
View file @
c1b531f1
...
...
@@ -143,13 +143,6 @@ begin
ddr_dma_clk_i
=>
clk_sys_62m5
,
ddr_dma_rst_n_i
=>
rst_sys_62m5_n
,
ddr_dma_wb_i
.
cyc
=>
'0'
,
ddr_dma_wb_i
.
stb
=>
'0'
,
ddr_dma_wb_i
.
adr
=>
x"0000_0000"
,
ddr_dma_wb_i
.
sel
=>
x"00"
,
ddr_dma_wb_i
.
we
=>
'0'
,
ddr_dma_wb_i
.
dat
=>
x"0000_0000_0000_0000"
,
ddr_dma_wb_o
=>
open
,
clk_62m5_sys_o
=>
clk_sys_62m5
,
rst_62m5_sys_n_o
=>
rst_sys_62m5_n
,
...
...
hdl/top/golden_wr/spec_golden_wr.vhd
View file @
c1b531f1
...
...
@@ -230,13 +230,6 @@ begin
ddr_dma_clk_i
=>
clk_sys_62m5
,
ddr_dma_rst_n_i
=>
rst_sys_62m5_n
,
ddr_dma_wb_i
.
cyc
=>
'0'
,
ddr_dma_wb_i
.
stb
=>
'0'
,
ddr_dma_wb_i
.
adr
=>
x"0000_0000"
,
ddr_dma_wb_i
.
sel
=>
x"00"
,
ddr_dma_wb_i
.
we
=>
'0'
,
ddr_dma_wb_i
.
dat
=>
x"0000_0000_0000_0000"
,
ddr_dma_wb_o
=>
open
,
clk_62m5_sys_o
=>
clk_sys_62m5
,
rst_62m5_sys_n_o
=>
rst_sys_62m5_n
,
...
...
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