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Simple PCIe FMC carrier SPEC
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Simple PCIe FMC carrier SPEC
Commits
a399b0fc
Commit
a399b0fc
authored
Jul 28, 2020
by
Dimitris Lampridis
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hdl: remove golden_wr-150T, not used anymore.
Signed-off-by:
Dimitris Lampridis
<
dimitris.lampridis@cern.ch
>
parent
907cc696
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.gitignore
hdl/syn/golden_wr-150T/.gitignore
+0
-5
Manifest.py
hdl/syn/golden_wr-150T/Manifest.py
+0
-40
syn_extra_steps.tcl
hdl/syn/golden_wr-150T/syn_extra_steps.tcl
+0
-32
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hdl/syn/golden_wr-150T/.gitignore
deleted
100644 → 0
View file @
907cc696
*
!.gitignore
!Manifest.py
!*.ucf
!syn_extra_steps.tcl
hdl/syn/golden_wr-150T/Manifest.py
deleted
100644 → 0
View file @
907cc696
target
=
"xilinx"
action
=
"synthesis"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if
locals
()
.
get
(
'fetchto'
,
None
)
is
None
:
fetchto
=
"../../ip_cores"
syn_device
=
"xc6slx150t"
syn_grade
=
"-3"
syn_package
=
"fgg484"
syn_project
=
"spec_golden_wr.xise"
syn_tool
=
"ise"
syn_top
=
"spec_golden_wr"
spec_base_ucf
=
[
'wr'
,
'onewire'
,
'spi'
]
board
=
"spec"
ctrls
=
[
"bank3_64b_32b"
]
files
=
[
"buildinfo_pkg.vhd"
]
modules
=
{
"local"
:
[
"../../top/golden_wr"
,
"../../syn/common"
],
"git"
:
[
"https://ohwr.org/project/wr-cores.git"
,
"https://ohwr.org/project/general-cores.git"
,
"https://ohwr.org/project/gn4124-core.git"
,
"https://ohwr.org/project/ddr3-sp6-core.git"
,
],
}
# Do not fail during hdlmake fetch
try
:
exec
(
open
(
fetchto
+
"/general-cores/tools/gen_buildinfo.py"
)
.
read
())
except
:
pass
syn_post_project_cmd
=
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
hdl/syn/golden_wr-150T/syn_extra_steps.tcl
deleted
100644 → 0
View file @
907cc696
# get project file from 1st command-line argument
set
project_file
[
lindex
$argv
0
]
if
{
!
[
file
exists
$project
_file
]}
{
report ERROR
"Missing file
$project
_file, exiting."
exit -1
}
xilinx::project open
$project
_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set
"Enable Multi-Threading"
"2"
-process
"Map"
xilinx::project set
"Enable Multi-Threading"
"4"
-process
"Place & Route"
xilinx::project set
"Pack I/O Registers into IOBs"
"Yes"
xilinx::project set
"Pack I/O Registers/Latches into IOBs"
"For Inputs and Outputs"
xilinx::project set
"Register Balancing"
"Yes"
xilinx::project set
"Register Duplication Map"
"On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only
)
" "
Normal
"
xilinx::project save
xilinx::project close
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