Commit a10b838b authored by Tristan Gingold's avatar Tristan Gingold

spec template: support for non-WR config.

parent 06cb643f
......@@ -379,10 +379,6 @@ architecture top of spec_template_wr is
signal sfp_scl_in : std_logic;
signal sfp_scl_out : std_logic;
-- OneWire
signal onewire_data : std_logic;
signal onewire_oe : std_logic;
-- LEDs and GPIO
signal wrc_abscal_txts_out : std_logic;
signal wrc_abscal_rxts_out : std_logic;
......@@ -608,6 +604,9 @@ begin -- architecture top
wrc_regs_o => wrc_out
);
fmc_presence (0) <= not fmc0_prsnt_m2c_n_i;
fmc_presence (31 downto 1) <= (others => '0');
-- Metadata
p_metadata: process (clk_sys_62m5) is
begin
......@@ -673,9 +672,6 @@ begin -- architecture top
end if;
end process;
fmc_presence (0) <= not fmc0_prsnt_m2c_n_i;
fmc_presence (31 downto 1) <= (others => '0');
rst_gbl_n <= rst_sys_62m5_n and (not csr_rst_gbl);
-- reset for DDR including soft reset.
......@@ -748,11 +744,6 @@ begin -- architecture top
irq_master <= '0';
end generate;
therm_id_in <= (ack => '1', err => '0', rty => '0', stall => '0',
dat => (others => '0'));
flash_spi_in <= (ack => '1', err => '0', rty => '0', stall => '0',
dat => (others => '0'));
irqs(1) <= '0';
irqs(4) <= '0';
irqs(5) <= '0';
......@@ -760,6 +751,12 @@ begin -- architecture top
-- The WR PTP core board package (WB Slave + WB Master #2 (Etherbone))
-----------------------------------------------------------------------------
g_wr: if g_WITH_WR generate
-- OneWire
signal onewire_data : std_logic;
signal onewire_oe : std_logic;
begin
-- Remap WR registers.
wrc_out_sh <= (cyc => wrc_out.cyc, stb => wrc_out.stb,
adr => wrc_out.adr or x"00020000",
sel => wrc_out.sel, we => wrc_out.we, dat => wrc_out.dat);
......@@ -877,17 +874,158 @@ begin -- architecture top
onewire_b <= '0' when (onewire_oe = '1') else 'Z';
onewire_data <= onewire_b;
-- EEPROM I2C tri-states
g_eeprom: if true generate
fmc0_sda_b <= '0' when (eeprom_sda_out = '0') else 'Z';
fmc0_scl_b <= '0' when (eeprom_scl_out = '0') else 'Z';
eeprom_sda_in <= fmc0_sda_b;
eeprom_scl_in <= fmc0_scl_b;
-- WR means neither onewire nor spi.
assert not g_WITH_ONEWIRE report "WR is not yet compatible with ONEWIRE"
severity failure;
assert not g_WITH_SPI report "WR is not yet compatible with SPI"
severity failure;
therm_id_in <= (ack => '1', err => '0', rty => '0', stall => '0',
dat => (others => '0'));
flash_spi_in <= (ack => '1', err => '0', rty => '0', stall => '0',
dat => (others => '0'));
irqs(1) <= '0';
end generate;
gen_with_ddr: if g_WITH_DDR generate
g_no_wr: if not g_WITH_WR generate
signal clk_125m_pllref : std_logic;
signal pllout_clk_fb_pllref : std_logic;
signal pllout_clk_62m5 : std_logic;
signal pllout_clk_125m : std_logic;
signal pllout_clk_333m : std_logic;
signal pllout_locked : std_logic;
signal rstlogic_arst : std_logic;
begin
-- Input clock
cmp_pllrefclk_buf : IBUFGDS
generic map (
DIFF_TERM => true, -- Differential Termination
IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => clk_125m_pllref, -- Buffer output
I => clk_125m_pllref_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => clk_125m_pllref_n_i -- Diff_n buffer input (connect directly to top-level port)
);
cmp_sys_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 8,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 16, -- 62.5 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 8, -- 125 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 3, -- 333 MHz
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 8.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => pllout_clk_fb_pllref,
CLKOUT0 => pllout_clk_62m5,
CLKOUT1 => pllout_clk_125m,
CLKOUT2 => pllout_clk_333m,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => pllout_locked,
RST => '0',
CLKFBIN => pllout_clk_fb_pllref,
CLKIN => clk_125m_pllref);
cmp_clk_62m5_buf : BUFG
port map (
O => clk_sys_62m5,
I => pllout_clk_62m5);
cmp_clk_125m_buf : BUFG
port map (
O => clk_ref_125m,
I => pllout_clk_125m);
cmp_clk_333m_buf : BUFG
port map (
O => clk_ddr_333m,
I => pllout_clk_333m);
-- logic AND of all async reset sources (active high)
rstlogic_arst <= (not pllout_locked) and (not gn_rst_n_i);
-- Clocks required to have synced resets
cmp_rstlogic_reset : gc_reset_multi_aasd
generic map (
g_CLOCKS => 3,
g_RST_LEN => 16) -- 16 clock cycles
port map (
arst_i => rstlogic_arst,
clks_i (0) => clk_sys_62m5,
clks_i (1) => clk_ref_125m,
clks_i (2) => clk_ddr_333m,
rst_n_o (0) => rst_sys_62m5_n,
rst_n_o (1) => rst_ref_125m_n,
rst_n_o (2) => rst_ddr_333m_n);
-- Not used.
wrc_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => x"00000000");
end generate;
g_onewire: if g_WITH_ONEWIRE and not g_WITH_WR generate
i_onewire: entity work.xwb_ds182x_readout
generic map (
g_CLOCK_FREQ_KHZ => 62_500,
g_USE_INTERNAL_PPS => True)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_gbl_n,
wb_i => therm_id_out,
wb_o => therm_id_in,
pps_p_i => '0',
onewire_b => onewire_b
);
end generate;
g_no_onewire: if not g_WITH_ONEWIRE and not g_WITH_WR generate
therm_id_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => x"00000000");
onewire_b <= 'Z';
end generate;
g_spi: if g_WITH_SPI and not g_WITH_WR generate
i_spi: entity work.xwb_spi
generic map (
g_interface_mode => CLASSIC,
g_address_granularity => BYTE,
g_divider_len => open,
g_max_char_len => open,
g_num_slaves => 1
)
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_gbl_n,
slave_i => flash_spi_out,
slave_o => flash_spi_in,
desc_o => open,
int_o => irqs(1),
pad_cs_o(0) => spi_ncs_o,
pad_sclk_o => spi_sclk_o,
pad_mosi_o => spi_mosi_o,
pad_miso_i => spi_miso_i
);
end generate;
g_no_spi: if not g_WITH_SPI and not g_WITH_WR generate
flash_spi_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => x"00000000");
end generate;
-- DDR3 controller
gen_with_ddr: if g_WITH_DDR generate
cmp_ddr_ctrl_bank3 : entity work.ddr3_ctrl
generic map(
g_RST_ACT_LOW => 0, -- active high reset (simpler internal logic)
......@@ -1013,5 +1151,4 @@ begin -- architecture top
ddr_dma_wb_o.err <= '0';
ddr_dma_wb_o.rty <= '0';
end architecture top;
......@@ -264,8 +264,8 @@ TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
# refclock is 62.5MHz and we don't use g_divide_input_by_2.
#PIN "WRC_PLATFORM/cmp_pllrefclk_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2017/02/20
NET "inst_template/cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = inst_template/cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>;
TIMESPEC TS_cmp_xwrc_board_spec_cmp_xwrc_platform_gen_phy_spartan6_cmp_gtp_ch1_gtp_clkout_int_1_ = PERIOD "inst_template/cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
NET "inst_template/g_wr.cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = inst_template/g_wr.cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>;
TIMESPEC TS_cmp_xwrc_board_spec_cmp_xwrc_platform_gen_phy_spartan6_cmp_gtp_ch1_gtp_clkout_int_1_ = PERIOD "inst_template/cmp_xwrc_board_spec/g_wr.cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
# PIN "cmp_clk_dmtd_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
##Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/08/07
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
......
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