Merge software and HDL

96a9e065 · Federico Vaga · ae47b9d7 · 270ca1d9 · 96a9e065 · 96a9e065
Commit 96a9e065 authored Jul 18, 2019 by Federico Vaga
30 changed files
--- a/hdl/.gitmodules
+++ b/hdl/.gitmodules
+[submodule "hdl/ip_cores/wr-cores"]
+	path = hdl/ip_cores/wr-cores
+	url = https://ohwr.org/project/wr-cores.git
+[submodule "hdl/ip_cores/general-cores"]
+	path = hdl/ip_cores/general-cores
+	url = https://ohwr.org/project/general-cores.git
+[submodule "hdl/ip_cores/gn4124-core"]
+	path = hdl/ip_cores/gn4124-core
+	url = https://ohwr.org/project/gn4124-core.git
+[submodule "hdl/ip_cores/ddr3-sp6-core"]
+	path = hdl/ip_cores/ddr3-sp6-core
+	url = https://ohwr.org/project/ddr3-sp6-core.git
--- a/hdl/Manifest.py
+++ b/hdl/Manifest.py
+modules = { "local" : [ "hdl/rtl" ] }
--- a/ddr3-sp6-core @ bb5b8f75
+++ b/ddr3-sp6-core @ bb5b8f75
+Subproject commit bb5b8f75e6f85335b43fef320375404686a74008
--- a/general-cores @ ac43a1db
+++ b/general-cores @ ac43a1db
+Subproject commit ac43a1dbde29bcbd9126d877477e77b620176bac
--- a/gn4124-core @ 2d01bc96
+++ b/gn4124-core @ 2d01bc96
+Subproject commit 2d01bc96a015a14ae90a449a52b86105c5c99b75
--- a/wr-cores @ 9b78baa4
+++ b/wr-cores @ 9b78baa4
+Subproject commit 9b78baa4feeae0461fc9846f9af683ba34f8dcc5
--- a/hdl/hdl/rtl/Manifest.py
+++ b/hdl/hdl/rtl/Manifest.py
+files = ["spec_template.vhd", "spec_template_regs.vhd", "spec_template_wr.vhd"]
--- a/hdl/hdl/rtl/spec_template.vhd
+++ b/hdl/hdl/rtl/spec_template.vhd
--- a/hdl/hdl/rtl/spec_template_regs.cheby
+++ b/hdl/hdl/rtl/spec_template_regs.cheby
+memory-map:
+  name: spec_template_regs
+  bus: wb-32-be
+  size: 0x2000
+  children:
+    - submap:
+        name: metadata
+        description: a ROM containing the carrier metadata
+        size: 0x40
+        interface: sram
+    - block:
+       name: csr
+       description: carrier and fmc status and control
+       address: 0x40
+       children:
+       - reg:
+          name: app_offset
+          description: offset to the application metadata
+          access: ro
+          width: 32
+       - reg:
+          name: resets
+          description: global and application resets
+          access: rw
+          width: 32
+          children:
+           - field:
+              name: global
+              range: 0
+           - field:
+              name: appl
+              range: 1
+       - reg:
+          name: fmc_presence
+          description: presence lines for the fmcs
+          access: ro
+          width: 32
+       - reg:
+          name: gn4124_status
+          description: status of gennum
+          access: ro
+          width: 32
+          # field 0: pll locked.
+       - reg:
+          name: ddr_status
+          description: status of the ddr3 controller
+          access: ro
+          width: 32
+          children:
+           - field:
+               description: Set when calibration is done.
+               name: calib_done
+               range: 0
+       - reg:
+          name: pcb_rev
+          description: pcb revision
+          access: ro
+          width: 32
+          children:
+           - field:
+              name: rev
+              range: 3-0
+    - submap:
+        name: therm_id
+        description: Thermometer and unique id
+        address: 0x70
+        size: 0x10
+        interface: wb-32-be
+        x-hdl:
+          busgroup: True
+    - submap:
+        name: fmc_i2c
+        description: i2c controllers to the fmcs
+        address: 0x80
+        size: 0x20
+        interface: wb-32-be
+        x-hdl:
+          busgroup: True
+    - submap:
+        name: flash_spi
+        description: spi controller to the flash
+        address: 0xa0
+        size: 0x20
+        interface: wb-32-be
+        x-hdl:
+          busgroup: True
+    - submap:
+        name: dma
+        description: dma registers for the gennum core
+        address: 0xc0
+        size: 0x40
+        interface: wb-32-be
+        x-hdl:
+          busgroup: True
+    - submap:
+        name: vic
+        description: vector interrupt controller
+        address: 0x100
+        size: 0x100
+        interface: wb-32-be
+        x-hdl:
+          busgroup: True
+    - submap:
+        name: buildinfo
+        description: a ROM containing build information
+        size: 0x100
+        interface: sram
+    - submap:
+        name: wrc_regs
+        address: 0x1000
+        description: white-rabbit core registers
+        size: 0x1000
+        interface: wb-32-be
+        x-hdl:
+          busgroup: True
--- a/hdl/hdl/rtl/spec_template_regs.vhd
+++ b/hdl/hdl/rtl/spec_template_regs.vhd
--- a/hdl/hdl/rtl/spec_template_wr.vhd
+++ b/hdl/hdl/rtl/spec_template_wr.vhd
--- a/hdl/hdl/syn/full/.gitignore
+++ b/hdl/hdl/syn/full/.gitignore
+*
+!.gitignore
+!Manifest.py
+!*.ucf
+!syn_extra_steps.tcl
--- a/hdl/hdl/syn/full/Manifest.py
+++ b/hdl/hdl/syn/full/Manifest.py
+target = "xilinx"
+action = "synthesis"
+
+# Allow the user to override fetchto using:
+#  hdlmake -p "fetchto='xxx'"
+if locals().get('fetchto', None) is None:
+  fetchto = "../../ip_cores"
+
+syn_device = "xc6slx45t"
+syn_grade = "-3"
+syn_package = "fgg484"
+syn_project = "spec_full.xise"
+syn_tool = "ise"
+syn_top = "spec_full"
+
+board = "spec"
+ctrls = ["bank3_64b_32b" ]
+
+files = [ "buildinfo_pkg.vhd" ]
+
+modules = {
+  "local" : [
+      "../../top/full",
+      ],
+  "git" : [
+      "https://ohwr.org/project/wr-cores.git",
+      "https://ohwr.org/project/general-cores.git",
+      "https://ohwr.org/project/gn4124-core.git",
+      "https://ohwr.org/project/ddr3-sp6-core.git",
+  ],
+}
+
+
+# Do not fail during hdlmake fetch
+try:
+  exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
+except:
+  pass
+
+syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
--- a/hdl/hdl/syn/full/syn_extra_steps.tcl
+++ b/hdl/hdl/syn/full/syn_extra_steps.tcl
+# get project file from 1st command-line argument
+set project_file [lindex $argv 0]
+
+if {![file exists $project_file]} {
+    report ERROR "Missing file $project_file, exiting."
+    exit -1
+}
+
+xilinx::project open $project_file
+
+# Some of these are not respected by ISE when passed through hdlmake,
+# so we add them all ourselves after creating the project
+#
+# Not respected by ISE when passed through hdlmake:
+# 1. Pack I/O Registers/Latches into IOBs
+# 2. Register Duplication Map
+
+xilinx::project set "Enable Multi-Threading" "2" -process "Map"
+xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
+
+xilinx::project set "Pack I/O Registers into IOBs" "Yes"
+xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
+
+xilinx::project set "Register Balancing" "Yes"
+xilinx::project set "Register Duplication Map" "On"
+
+#xilinx::project set "Placer Extra Effort Map" "Normal"
+#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
+
+xilinx::project save
+
+xilinx::project close
--- a/hdl/hdl/syn/golden/Manifest.py
+++ b/hdl/hdl/syn/golden/Manifest.py
+target = "xilinx"
+action = "synthesis"
+
+fetchto = "../../ip_cores"
+
+syn_device = "xc6slx45t"
+syn_grade = "-3"
+syn_package = "fgg484"
+syn_project = "spec_golden.xise"
+syn_tool = "ise"
+syn_top = "spec_golden"
+
+modules = {
+  "local" : [
+      "../../top/golden",
+      ],
+  "git" : [
+      "https://ohwr.org/project/wr-cores.git",
+      "https://ohwr.org/project/general-cores.git",
+      "https://ohwr.org/project/gn4124-core.git",
+  ],
+}
--- a/hdl/hdl/syn/golden_wr-150T/.gitignore
+++ b/hdl/hdl/syn/golden_wr-150T/.gitignore
+*
+!.gitignore
+!Manifest.py
+!*.ucf
+!syn_extra_steps.tcl
--- a/hdl/hdl/syn/golden_wr-150T/Manifest.py
+++ b/hdl/hdl/syn/golden_wr-150T/Manifest.py
+target = "xilinx"
+action = "synthesis"
+
+# Allow the user to override fetchto using:
+#  hdlmake -p "fetchto='xxx'"
+if locals().get('fetchto', None) is None:
+  fetchto = "../../ip_cores"
+
+syn_device = "xc6slx150t"
+syn_grade = "-3"
+syn_package = "fgg484"
+syn_project = "spec_golden_wr.xise"
+syn_tool = "ise"
+syn_top = "spec_golden_wr"
+
+board = "spec"
+ctrls = ["bank3_64b_32b" ]
+
+files = [ "buildinfo_pkg.vhd" ]
+
+modules = {
+  "local" : [
+      "../../top/golden_wr",
+      ],
+  "git" : [
+      "https://ohwr.org/project/wr-cores.git",
+      "https://ohwr.org/project/general-cores.git",
+      "https://ohwr.org/project/gn4124-core.git",
+      "https://ohwr.org/project/ddr3-sp6-core.git",
+  ],
+}
+
+# Do not fail during hdlmake fetch
+try:
+  exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
+except:
+  pass
+
+syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
--- a/hdl/hdl/syn/golden_wr-150T/syn_extra_steps.tcl
+++ b/hdl/hdl/syn/golden_wr-150T/syn_extra_steps.tcl
+# get project file from 1st command-line argument
+set project_file [lindex $argv 0]
+
+if {![file exists $project_file]} {
+    report ERROR "Missing file $project_file, exiting."
+    exit -1
+}
+
+xilinx::project open $project_file
+
+# Some of these are not respected by ISE when passed through hdlmake,
+# so we add them all ourselves after creating the project
+#
+# Not respected by ISE when passed through hdlmake:
+# 1. Pack I/O Registers/Latches into IOBs
+# 2. Register Duplication Map
+
+xilinx::project set "Enable Multi-Threading" "2" -process "Map"
+xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
+
+xilinx::project set "Pack I/O Registers into IOBs" "Yes"
+xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
+
+xilinx::project set "Register Balancing" "Yes"
+xilinx::project set "Register Duplication Map" "On"
+
+#xilinx::project set "Placer Extra Effort Map" "Normal"
+#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
+
+xilinx::project save
+
+xilinx::project close
--- a/hdl/hdl/syn/golden_wr/.gitignore
+++ b/hdl/hdl/syn/golden_wr/.gitignore
+*
+!.gitignore
+!Manifest.py
+!*.ucf
+!syn_extra_steps.tcl
--- a/hdl/hdl/syn/golden_wr/Manifest.py
+++ b/hdl/hdl/syn/golden_wr/Manifest.py
+target = "xilinx"
+action = "synthesis"
+
+# Allow the user to override fetchto using:
+#  hdlmake -p "fetchto='xxx'"
+if locals().get('fetchto', None) is None:
+  fetchto = "../../ip_cores"
+
+syn_device = "xc6slx45t"
+syn_grade = "-3"
+syn_package = "fgg484"
+syn_project = "spec_golden_wr.xise"
+syn_tool = "ise"
+syn_top = "spec_golden_wr"
+
+board = "spec"
+ctrls = ["bank3_64b_32b" ]
+
+files = [ "buildinfo_pkg.vhd" ]
+
+modules = {
+  "local" : [
+      "../../top/golden_wr",
+      ],
+  "git" : [
+      "https://ohwr.org/project/wr-cores.git",
+      "https://ohwr.org/project/general-cores.git",
+      "https://ohwr.org/project/gn4124-core.git",
+      "https://ohwr.org/project/ddr3-sp6-core.git",
+  ],
+}
+
+# Do not fail during hdlmake fetch
+try:
+  exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
+except:
+  pass
+
+syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
--- a/hdl/hdl/syn/golden_wr/syn_extra_steps.tcl
+++ b/hdl/hdl/syn/golden_wr/syn_extra_steps.tcl
+# get project file from 1st command-line argument
+set project_file [lindex $argv 0]
+
+if {![file exists $project_file]} {
+    report ERROR "Missing file $project_file, exiting."
+    exit -1
+}
+
+xilinx::project open $project_file
+
+# Some of these are not respected by ISE when passed through hdlmake,
+# so we add them all ourselves after creating the project
+#
+# Not respected by ISE when passed through hdlmake:
+# 1. Pack I/O Registers/Latches into IOBs
+# 2. Register Duplication Map
+
+xilinx::project set "Enable Multi-Threading" "2" -process "Map"
+xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
+
+xilinx::project set "Pack I/O Registers into IOBs" "Yes"
+xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
+
+xilinx::project set "Register Balancing" "Yes"
+xilinx::project set "Register Duplication Map" "On"
+
+#xilinx::project set "Placer Extra Effort Map" "Normal"
+#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
+
+xilinx::project save
+
+xilinx::project close
--- a/hdl/hdl/top/full/Manifest.py
+++ b/hdl/hdl/top/full/Manifest.py
+files = ["spec_full.vhd", "spec_full.ucf"]
+modules = {'local': ["../../rtl"]}
--- a/hdl/hdl/top/full/spec_full.ucf
+++ b/hdl/hdl/top/full/spec_full.ucf
--- a/hdl/hdl/top/full/spec_full.vhd
+++ b/hdl/hdl/top/full/spec_full.vhd
--- a/hdl/hdl/top/golden/Manifest.py
+++ b/hdl/hdl/top/golden/Manifest.py
+files = ["spec_golden.vhd", "spec_golden.ucf"]
+modules = {'local': ["../../rtl"]}
--- a/hdl/hdl/top/golden/spec_golden.ucf
+++ b/hdl/hdl/top/golden/spec_golden.ucf
+#bank 0
+
+NET "clk_125m_pllref_n_i" LOC = F10;
+NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
+
+NET "clk_125m_pllref_p_i" LOC = G9;
+NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
+
+#NET "SFP_MOD_DEF1_b" LOC = C17;
+#NET "SFP_MOD_DEF1_b" IOSTANDARD = "LVCMOS25";
+#NET "SFP_MOD_DEF0_b" LOC = G15;
+#NET "SFP_MOD_DEF0_b" IOSTANDARD = "LVCMOS25";
+#NET "SFP_MOD_DEF2_b" LOC = G16;
+#NET "SFP_MOD_DEF2_b" IOSTANDARD = "LVCMOS25";
+#NET "SFP_RATE_SELECT_b" LOC = H14;
+#NET "SFP_RATE_SELECT_b" IOSTANDARD = "LVCMOS25";
+#NET "SFP_TX_FAULT_i" LOC = A17;
+#NET "SFP_TX_FAULT_i" IOSTANDARD = "LVCMOS25";
+#NET "SFP_TX_DISABLE_o" LOC = F17;
+#NET "SFP_TX_DISABLE_o" IOSTANDARD = "LVCMOS25";
+#NET "SFP_LOS_i" LOC = D18;
+#NET "SFP_LOS_i" IOSTANDARD = "LVCMOS25";
+
+#NET "BUTTON1_I" LOC = C22;
+#NET "BUTTON1_I" IOSTANDARD = "LVCMOS18";
+#NET "BUTTON2_I" LOC = D21;
+#NET "BUTTON2_I" IOSTANDARD = "LVCMOS18";
+
+NET "SPI_NCS_O"  LOC = AA3;
+NET "SPI_NCS_O"  IOSTANDARD = "LVCMOS25";
+NET "SPI_SCLK_O" LOC = Y20;
+NET "SPI_SCLK_O"  IOSTANDARD = "LVCMOS25";
+NET "SPI_MOSI_O" LOC = AB20;
+NET "SPI_MOSI_O"  IOSTANDARD = "LVCMOS25";
+NET "SPI_MISO_I" LOC = AA20;
+NET "SPI_MISO_I"  IOSTANDARD = "LVCMOS25";
+
+NET "GN_RST_N" LOC = N20;
+NET "GN_RST_N" IOSTANDARD = "LVCMOS18";
+NET "GN_L2P_CLK_N" LOC = K22;
+NET "GN_L2P_CLK_N" IOSTANDARD = "DIFF_SSTL18_I";
+NET "GN_L2P_CLK_P" LOC = K21;
+NET "GN_L2P_CLK_P" IOSTANDARD = "DIFF_SSTL18_I";
+NET "GN_L2P_DFRAME" LOC = U22;
+NET "GN_L2P_DFRAME" IOSTANDARD = "SSTL18_I";
+NET "GN_L2P_EDB" LOC = U20;
+NET "GN_L2P_EDB" IOSTANDARD = "SSTL18_I";
+NET "GN_L2P_RDY" LOC = U19;
+NET "GN_L2P_RDY" IOSTANDARD = "SSTL18_I";
+NET "GN_L2P_VALID" LOC = T18;
+NET "GN_L2P_VALID" IOSTANDARD = "SSTL18_I";
+NET "GN_L_WR_RDY[0]" LOC = R20;
+NET "GN_L_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
+NET "GN_L_WR_RDY[1]" LOC = T22;
+NET "GN_L_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
+
+NET "GN_P2L_CLK_N" LOC = M19;
+NET "GN_P2L_CLK_N" IOSTANDARD = "DIFF_SSTL18_I";
+NET "GN_P2L_CLK_P" LOC = M20;
+NET "GN_P2L_CLK_P" IOSTANDARD = "DIFF_SSTL18_I";
+
+NET "GN_P2L_DFRAME" LOC = J22;
+NET "GN_P2L_DFRAME" IOSTANDARD = "SSTL18_I";
+
+NET "GN_P2L_RDY" LOC = J16;
+NET "GN_P2L_RDY" IOSTANDARD = "SSTL18_I";
+
+NET "GN_P2L_VALID" LOC = L19;
+NET "GN_P2L_VALID" IOSTANDARD = "SSTL18_I";
+
+NET "GN_P_RD_D_RDY[0]" LOC = N16;
+NET "GN_P_RD_D_RDY[0]" IOSTANDARD = "SSTL18_I";
+NET "GN_P_RD_D_RDY[1]" LOC = P19;
+NET "GN_P_RD_D_RDY[1]" IOSTANDARD = "SSTL18_I";
+
+NET "GN_P_WR_RDY[0]" LOC = L15;
+NET "GN_P_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
+NET "GN_P_WR_RDY[1]" LOC = K16;
+NET "GN_P_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
+NET "GN_P_WR_REQ[0]" LOC = M22;
+NET "GN_P_WR_REQ[0]" IOSTANDARD = "SSTL18_I";
+NET "GN_P_WR_REQ[1]" LOC = M21;
+NET "GN_P_WR_REQ[1]" IOSTANDARD = "SSTL18_I";
+
+NET "GN_RX_ERROR" LOC = J17;
+NET "GN_RX_ERROR" IOSTANDARD = "SSTL18_I";
+NET "GN_TX_ERROR" LOC = M17;
+NET "GN_TX_ERROR" IOSTANDARD = "SSTL18_I";
+
+NET "GN_VC_RDY[0]" LOC = B21;
+NET "GN_VC_RDY[0]" IOSTANDARD = "SSTL18_I";
+NET "GN_VC_RDY[1]" LOC = B22;
+NET "GN_VC_RDY[1]" IOSTANDARD = "SSTL18_I";
+
+NET "GN_L2P_DATA[0]" LOC = P16;
+NET "GN_L2P_DATA[0]" IOSTANDARD = "SSTL18_I";
+NET "GN_L2P_DATA[1]" LOC = P21;
+NET "GN_L2P_DATA[1]" IOSTANDARD = "SSTL18_I";
+NET "GN_L2P_DATA[2]" LOC = P18;
+NET "GN_L2P_DATA[2]" IOSTANDARD = "SSTL18_I";
+NET "GN_L2P_DATA[3]" LOC = T20;
+NET "GN_L2P_DATA[3]" IOSTANDARD = "SSTL18_I";
+NET "GN_L2P_DATA[4]" LOC = V21;
+NET "GN_L2P_DATA[4]" IOSTANDARD = "SSTL18_I";
+
+NET "GN_L2P_DATA[5]" LOC = V19;
+NET "GN_L2P_DATA[5]" IOSTANDARD = "SSTL18_I";
+
+NET "GN_L2P_DATA[6]" LOC = W22;
+NET "GN_L2P_DATA[6]" IOSTANDARD = "SSTL18_I";
+NET "GN_L2P_DATA[7]" LOC = Y22;
+NET "GN_L2P_DATA[7]" IOSTANDARD = "SSTL18_I";
+
+NET "GN_L2P_DATA[8]" LOC = P22;
+NET "GN_L2P_DATA[8]" IOSTANDARD = "SSTL18_I";
+NET "GN_L2P_DATA[9]" LOC = R22;
+NET "GN_L2P_DATA[9]" IOSTANDARD = "SSTL18_I";
+NET "GN_L2P_DATA[10]" LOC = T21;
+NET "GN_L2P_DATA[10]" IOSTANDARD = "SSTL18_I";
+NET "GN_L2P_DATA[11]" LOC = T19;
+NET "GN_L2P_DATA[11]" IOSTANDARD = "SSTL18_I";
+NET "GN_L2P_DATA[12]" LOC = V22;
+NET "GN_L2P_DATA[12]" IOSTANDARD = "SSTL18_I";
+NET "GN_L2P_DATA[13]" LOC = V20;
+NET "GN_L2P_DATA[13]" IOSTANDARD = "SSTL18_I";
+NET "GN_L2P_DATA[14]" LOC = W20;
+NET "GN_L2P_DATA[14]" IOSTANDARD = "SSTL18_I";
+NET "GN_L2P_DATA[15]" LOC = Y21;
+NET "GN_L2P_DATA[15]" IOSTANDARD = "SSTL18_I";
+
+
+NET "GN_P2L_DATA[0]" LOC = K20;
+NET "GN_P2L_DATA[0]" IOSTANDARD = "SSTL18_I";
+NET "GN_P2L_DATA[1]" LOC = H22;
+NET "GN_P2L_DATA[1]" IOSTANDARD = "SSTL18_I";
+NET "GN_P2L_DATA[2]" LOC = H21;
+NET "GN_P2L_DATA[2]" IOSTANDARD = "SSTL18_I";
+NET "GN_P2L_DATA[3]" LOC = L17;
+NET "GN_P2L_DATA[3]" IOSTANDARD = "SSTL18_I";
+NET "GN_P2L_DATA[4]" LOC = K17;
+NET "GN_P2L_DATA[4]" IOSTANDARD = "SSTL18_I";
+NET "GN_P2L_DATA[5]" LOC = G22;
+NET "GN_P2L_DATA[5]" IOSTANDARD = "SSTL18_I";
+NET "GN_P2L_DATA[6]" LOC = G20;
+NET "GN_P2L_DATA[6]" IOSTANDARD = "SSTL18_I";
+NET "GN_P2L_DATA[7]" LOC = K18;
+NET "GN_P2L_DATA[7]" IOSTANDARD = "SSTL18_I";
+NET "GN_P2L_DATA[8]" LOC = K19;
+NET "GN_P2L_DATA[8]" IOSTANDARD = "SSTL18_I";
+NET "GN_P2L_DATA[9]" LOC = H20;
+NET "GN_P2L_DATA[9]" IOSTANDARD = "SSTL18_I";
+NET "GN_P2L_DATA[10]" LOC = J19;
+NET "GN_P2L_DATA[10]" IOSTANDARD = "SSTL18_I";
+NET "GN_P2L_DATA[11]" LOC = E22;
+NET "GN_P2L_DATA[11]" IOSTANDARD = "SSTL18_I";
+NET "GN_P2L_DATA[12]" LOC = E20;
+NET "GN_P2L_DATA[12]" IOSTANDARD = "SSTL18_I";
+NET "GN_P2L_DATA[13]" LOC = F22;
+NET "GN_P2L_DATA[13]" IOSTANDARD = "SSTL18_I";
+NET "GN_P2L_DATA[14]" LOC = F21;
+NET "GN_P2L_DATA[14]" IOSTANDARD = "SSTL18_I";
+NET "GN_P2L_DATA[15]" LOC = H19;
+NET "GN_P2L_DATA[15]" IOSTANDARD = "SSTL18_I";
+
+# GPIO 8 and 9 of the Genum
+NET "GN_GPIO[0]" LOC = U16;
+NET "GN_GPIO[0]" IOSTANDARD = "LVCMOS25";
+NET "GN_GPIO[1]" LOC = AB19;
+NET "GN_GPIO[1]" IOSTANDARD = "LVCMOS25";
+
+#NET "LED_RED" LOC = D5;
+#NET "LED_RED" IOSTANDARD = "LVCMOS25";
+#NET "LED_GREEN" LOC = E5;
+#NET "LED_GREEN" IOSTANDARD = "LVCMOS25";
+
+# Onewire interface -> thermometer
+NET "onewire_b" LOC = D4;
+NET "onewire_b" IOSTANDARD = "LVCMOS25";
+
+#----------------------------------------
+# FMC slot management
+#----------------------------------------
+NET "fmc0_prsnt_m2c_n_i" LOC = AB14;
+NET "fmc0_scl_b"         LOC = F7;
+NET "fmc0_sda_b"         LOC = F8;
+
+NET "fmc0_prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
+NET "fmc0_scl_b"         IOSTANDARD = "LVCMOS25";
+NET "fmc0_sda_b"         IOSTANDARD = "LVCMOS25";
+
+#---------------------------------------------------------------------------------------------
+# False Path
+#---------------------------------------------------------------------------------------------
+# GN4124
+NET "gn_rst_n" TIG;
+#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/01/20
+NET "inst_template/cmp_gn4124_core/cmp_clk_in/P_clk" TNM_NET = inst_template/cmp_gn4124_core/cmp_clk_in/P_clk;
+#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2011/02/04
+NET "clk_125m_pllref_p_i" TNM_NET = clk_125m_pllref_p_i;
+TIMESPEC TS_clk_125m_pllref_p_i = PERIOD "clk_125m_pllref_p_i" 8 ns HIGH 50%;
+NET "clk_125m_pllref_n_i" TNM_NET = clk_125m_pllref_n_i;
+TIMESPEC TS_clk_125m_pllref_n_i = PERIOD "clk_125m_pllref_n_i" 8 ns HIGH 50%;
+
+NET "GN_P2L_CLK_p" TNM_NET = "p2l_clkp_grp";
+NET "GN_P2L_CLK_n" TNM_NET = "p2l_clkn_grp";
+TIMESPEC TS_cmp_gn4124_core_cmp_clk_in_P_clk = PERIOD "inst_template/cmp_gn4124_core/cmp_clk_in/P_clk" 5 ns HIGH 50%;
+
--- a/hdl/hdl/top/golden/spec_golden.vhd
+++ b/hdl/hdl/top/golden/spec_golden.vhd
+--------------------------------------------------------------------------------
+-- CERN BE-CO-HT
+-- SPEC
+-- https://ohwr.org/projects/spec
+--------------------------------------------------------------------------------
+--
+-- unit name:   spec_golden
+--
+-- description: SPEC golden design, without WR.
+--
+--------------------------------------------------------------------------------
+-- Copyright CERN 2019
+--------------------------------------------------------------------------------
+-- Copyright and related rights are licensed under the Solderpad Hardware
+-- License, Version 2.0 (the "License"); you may not use this file except
+-- in compliance with the License. You may obtain a copy of the License at
+-- http://solderpad.org/licenses/SHL-2.0.
+-- Unless required by applicable law or agreed to in writing, software,
+-- hardware and materials distributed under this License is distributed on an
+-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
+-- or implied. See the License for the specific language governing permissions
+-- and limitations under the License.
+--------------------------------------------------------------------------------
+
+library IEEE;
+use IEEE.STD_LOGIC_1164.all;
+
+entity spec_golden is
+  port (
+    -- Global ports
+    clk_125m_pllref_p_i : in std_logic;  -- 125 MHz PLL reference
+    clk_125m_pllref_n_i : in std_logic;
+
+    gn_RST_N : in std_logic;           -- Reset from GN4124 (RSTOUT18_N)
+
+    -- General Purpose Interface
+    gn_GPIO : inout std_logic_vector(1 downto 0);  -- GPIO[0] -> GN4124 GPIO8
+                                                -- GPIO[1] -> GN4124 GPIO9
+    -- PCIe to Local [Inbound Data] - RX
+    gn_P2L_RDY    : out std_logic;       -- Rx Buffer Full Flag
+    gn_P2L_CLK_n  : in  std_logic;       -- Receiver Source Synchronous Clock-
+    gn_P2L_CLK_p  : in  std_logic;       -- Receiver Source Synchronous Clock+
+    gn_P2L_DATA   : in  std_logic_vector(15 downto 0);  -- Parallel receive data
+    gn_P2L_DFRAME : in  std_logic;       -- Receive Frame
+    gn_P2L_VALID  : in  std_logic;       -- Receive Data Valid
+
+    -- Inbound Buffer Request/Status
+    gn_P_WR_REQ : in  std_logic_vector(1 downto 0);  -- PCIe Write Request
+    gn_P_WR_RDY : out std_logic_vector(1 downto 0);  -- PCIe Write Ready
+    gn_RX_ERROR : out std_logic;                     -- Receive Error
+
+    -- Local to Parallel [Outbound Data] - TX
+    gn_L2P_DATA   : out std_logic_vector(15 downto 0);  -- Parallel transmit data
+    gn_L2P_DFRAME : out std_logic;       -- Transmit Data Frame
+    gn_L2P_VALID  : out std_logic;       -- Transmit Data Valid
+    gn_L2P_CLK_n  : out std_logic;  -- Transmitter Source Synchronous Clock-
+    gn_L2P_CLK_p  : out std_logic;  -- Transmitter Source Synchronous Clock+
+    gn_L2P_EDB    : out std_logic;       -- Packet termination and discard
+
+    -- Outbound Buffer Status
+    gn_L2P_RDY    : in std_logic;        -- Tx Buffer Full Flag
+    gn_L_WR_RDY   : in std_logic_vector(1 downto 0);  -- Local-to-PCIe Write
+    gn_P_RD_D_RDY : in std_logic_vector(1 downto 0);  -- PCIe-to-Local Read Response Data Ready
+    gn_TX_ERROR   : in std_logic;        -- Transmit Error
+    gn_VC_RDY     : in std_logic_vector(1 downto 0);  -- Channel ready
+
+    -- Font panel LEDs
+--  LED_RED   : out std_logic;
+--  LED_GREEN : out std_logic;
+
+    -- I2C to the FMC
+    fmc0_scl_b : inout std_logic;
+    fmc0_sda_b : inout std_logic;
+
+    --  FMC presence  (there is a pull-up)
+    fmc0_prsnt_m2c_n_i: in std_logic;
+
+    onewire_b : inout std_logic;
+  
+--  button1_i : in std_logic;
+--  button2_i : in std_logic;
+
+    spi_sclk_o : out std_logic; 
+    spi_ncs_o  : out std_logic;
+    spi_mosi_o : out std_logic;
+    spi_miso_i : in  std_logic
+    );
+end spec_golden;
+
+architecture rtl of spec_golden is
+begin
+  inst_template: entity work.spec_template
+    generic map (
+      g_with_vic => true,
+      g_with_onewire => true,
+      g_with_spi => true
+    )
+    port map (
+      clk_125m_pllref_p_i => clk_125m_pllref_p_i,
+      clk_125m_pllref_n_i => clk_125m_pllref_n_i,
+      gn_rst_n => gn_rst_n,
+      gn_gpio => gn_gpio,
+      gn_p2l_rdy => gn_p2l_rdy,
+      gn_p2l_clk_n => gn_p2l_clk_n,
+      gn_p2l_clk_p => gn_p2l_clk_p,
+      gn_p2l_data => gn_p2l_data,
+      gn_p2l_dframe => gn_p2l_dframe,
+      gn_p2l_valid => gn_p2l_valid,
+      gn_p_wr_req => gn_p_wr_req,
+      gn_p_wr_rdy => gn_p_wr_rdy,
+      gn_rx_error => gn_rx_error,
+      gn_l2p_data => gn_l2p_data,
+      gn_l2p_dframe => gn_l2p_dframe,
+      gn_l2p_valid => gn_l2p_valid,
+      gn_l2p_clk_n => gn_l2p_clk_n,
+      gn_l2p_clk_p => gn_l2p_clk_p,
+      gn_l2p_edb => gn_l2p_edb,
+      gn_l2p_rdy => gn_l2p_rdy,
+      gn_l_wr_rdy => gn_l_wr_rdy,
+      gn_p_rd_d_rdy => gn_p_rd_d_rdy,
+      gn_tx_error => gn_tx_error,
+      gn_vc_rdy => gn_vc_rdy,
+      fmc0_scl_b => fmc0_scl_b,
+      fmc0_sda_b => fmc0_sda_b,
+      fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
+      onewire_b => onewire_b,
+      spi_sclk_o => spi_sclk_o,
+      spi_ncs_o => spi_ncs_o,
+      spi_mosi_o => spi_mosi_o,
+      spi_miso_i => spi_miso_i
+    );
+end rtl;
--- a/hdl/hdl/top/golden_wr/Manifest.py
+++ b/hdl/hdl/top/golden_wr/Manifest.py
+files = ["spec_golden_wr.vhd", "spec_golden_wr.ucf"]
+modules = {'local': ["../../rtl"]}
--- a/hdl/hdl/top/golden_wr/spec_golden_wr.ucf
+++ b/hdl/hdl/top/golden_wr/spec_golden_wr.ucf
--- a/hdl/hdl/top/golden_wr/spec_golden_wr.vhd
+++ b/hdl/hdl/top/golden_wr/spec_golden_wr.vhd