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Simple PCIe FMC carrier SPEC
Commit 8fbf7438 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: introduce simplified top-level for DMA testing and update testbench

parent 90be31a5
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Showing with 539 additions and 108 deletions
ddr3-sp6-core @ ba3e6787
Subproject commit 1a1293900e6334bc41251ee84d0ae7d19980e584 Subproject commit ba3e6787e6c98cd1fd944fbea18d081c3cb96904
general-cores @ b9925c97
Subproject commit e6bd92bb9f040a667004718053116e119132a5e3 Subproject commit b9925c97707698310e232ae2736e3d3d4b1b5971
gn4124-core @ d5e7a9f2
Subproject commit 91d5eface7608d306991d2c1aa4e6f5210e9305c Subproject commit d5e7a9f24aad042caa27a907c5389ddd94e99a3c
hdl/rtl/spec_base_wr.vhd
View file @ 8fbf7438
...@@ -74,6 +74,11 @@ entity spec_base_wr is ...@@ -74,6 +74,11 @@ entity spec_base_wr is
g_SIMULATION : boolean := False; g_SIMULATION : boolean := False;
-- Increase information messages during simulation -- Increase information messages during simulation
g_VERBOSE : boolean := False; g_VERBOSE : boolean := False;
-- if TRUE, use 200MHz PCI clock also for DMA transfers. Note
-- that this might be very hard to achieve timing closure with.
-- if FALSE, use the 125MHz "ref" clock and async_fifos for
-- clock domain crossing between this clock and the PCI one.
g_DMA_USE_PCI_CLK : boolean := FALSE;
g_SIM_BYPASS_GENNUM : boolean := False g_SIM_BYPASS_GENNUM : boolean := False
); );
port ( port (
...@@ -333,6 +338,9 @@ architecture top of spec_base_wr is ...@@ -333,6 +338,9 @@ architecture top of spec_base_wr is
signal gn_wb_out : t_wishbone_master_out; signal gn_wb_out : t_wishbone_master_out;
signal gn_wb_in : t_wishbone_master_in; signal gn_wb_in : t_wishbone_master_in;
signal wb_dma_clk : std_logic;
signal wb_dma_rst_n : std_logic;
-- The wishbone bus to the carrier part. -- The wishbone bus to the carrier part.
signal carrier_wb_out : t_wishbone_slave_out; signal carrier_wb_out : t_wishbone_slave_out;
signal carrier_wb_in : t_wishbone_slave_in; signal carrier_wb_in : t_wishbone_slave_in;
...@@ -392,6 +400,8 @@ architecture top of spec_base_wr is ...@@ -392,6 +400,8 @@ architecture top of spec_base_wr is
signal rst_125m_ref_n : std_logic; signal rst_125m_ref_n : std_logic;
signal clk_125m_ref : std_logic; signal clk_125m_ref : std_logic;
signal clk_10m_ext : std_logic; signal clk_10m_ext : std_logic;
signal clk_200m_gnm : std_logic;
signal rst_200m_gnm_n : std_logic;
-- I2C EEPROM -- I2C EEPROM
signal eeprom_sda_in : std_logic; signal eeprom_sda_in : std_logic;
...@@ -425,19 +435,27 @@ begin -- architecture top ...@@ -425,19 +435,27 @@ begin -- architecture top
gen_with_gennum : if g_SIMULATION = false or g_sim_bypass_gennum = false generate gen_with_gennum : if g_SIMULATION = false or g_sim_bypass_gennum = false generate
-- DMA WB clock and reset selection
gen_sync_wb_dma : if g_DMA_USE_PCI_CLK = TRUE generate
wb_dma_clk <= clk_200m_gnm;
wb_dma_rst_n <= rst_200m_gnm_n;
end generate gen_sync_wb_dma;
gen_async_wb_dma : if g_DMA_USE_PCI_CLK = FALSE generate
wb_dma_clk <= clk_125m_ref;
wb_dma_rst_n <= rst_125m_ref_n;
-- wb_dma_clk <= clk_62m5_sys;
-- wb_dma_rst_n <= rst_62m5_sys_n;
end generate gen_async_wb_dma;
cmp_gn4124_core : entity work.xwb_gn4124_core cmp_gn4124_core : entity work.xwb_gn4124_core
generic map ( generic map (
g_WITH_DMA => g_WITH_DDR, g_WITH_DMA => g_WITH_DDR,
g_DMA_USE_PCI_CLK => g_DMA_USE_PCI_CLK,
g_WBM_TO_WB_FIFO_SIZE => 16, g_WBM_TO_WB_FIFO_SIZE => 16,
g_WBM_TO_WB_FIFO_FULL_THRES => 12, g_WBM_TO_WB_FIFO_FULL_THRES => 12,
g_WBM_FROM_WB_FIFO_SIZE => 16, g_WBM_FROM_WB_FIFO_SIZE => 16,
g_WBM_FROM_WB_FIFO_FULL_THRES => 12, g_WBM_FROM_WB_FIFO_FULL_THRES => 12
g_P2L_FIFO_SIZE => 256,
g_P2L_FIFO_FULL_THRES => 175,
g_L2P_ADDR_FIFO_FULL_SIZE => 256,
g_L2P_ADDR_FIFO_FULL_THRES => 175,
g_L2P_DATA_FIFO_FULL_SIZE => 256,
g_L2P_DATA_FIFO_FULL_THRES => 175
) )
port map ( port map (
--------------------------------------------------------- ---------------------------------------------------------
...@@ -445,6 +463,11 @@ begin -- architecture top ...@@ -445,6 +463,11 @@ begin -- architecture top
rst_n_a_i => gn_rst_n_i, rst_n_a_i => gn_rst_n_i,
status_o => gennum_status, status_o => gennum_status,
---------------------------------------------------------
-- 200MHz PCI clock output and synchronous reset for applications
clk_200m_o => clk_200m_gnm,
rst_200m_n_o => rst_200m_gnm_n,
--------------------------------------------------------- ---------------------------------------------------------
-- P2L Direction -- P2L Direction
-- --
...@@ -488,10 +511,10 @@ begin -- architecture top ...@@ -488,10 +511,10 @@ begin -- architecture top
--------------------------------------------------------- ---------------------------------------------------------
-- DMA registers wishbone interface (slave classic) -- DMA registers wishbone interface (slave classic)
wb_dma_cfg_clk_i => clk_62m5_sys, wb_dma_cfg_clk_i => clk_62m5_sys,
wb_dma_cfg_rst_n_i => rst_62m5_sys_n, wb_dma_cfg_rst_n_i => rst_62m5_sys_n,
wb_dma_cfg_i => dma_out, wb_dma_cfg_i => dma_out,
wb_dma_cfg_o => dma_in, wb_dma_cfg_o => dma_in,
--------------------------------------------------------- ---------------------------------------------------------
-- CSR wishbone interface (master pipelined) -- CSR wishbone interface (master pipelined)
...@@ -502,8 +525,8 @@ begin -- architecture top ...@@ -502,8 +525,8 @@ begin -- architecture top
--------------------------------------------------------- ---------------------------------------------------------
-- L2P DMA Interface (Pipelined Wishbone master) -- L2P DMA Interface (Pipelined Wishbone master)
wb_dma_dat_clk_i => clk_62m5_sys, wb_dma_dat_clk_i => wb_dma_clk,
wb_dma_dat_rst_n_i => rst_gbl_n, wb_dma_dat_rst_n_i => wb_dma_rst_n,
wb_dma_dat_o => gn_wb_ddr_out, wb_dma_dat_o => gn_wb_ddr_out,
wb_dma_dat_i => gn_wb_ddr_in wb_dma_dat_i => gn_wb_ddr_in
); );
...@@ -1110,8 +1133,8 @@ begin -- architecture top ...@@ -1110,8 +1133,8 @@ begin -- architecture top
p0_wr_underrun_o => open, p0_wr_underrun_o => open,
p0_wr_error_o => open, p0_wr_error_o => open,
wb1_rst_n_i => rst_gbl_n, wb1_rst_n_i => wb_dma_rst_n,
wb1_clk_i => clk_62m5_sys, wb1_clk_i => wb_dma_clk,
wb1_sel_i => gn_wb_ddr_out.sel, wb1_sel_i => gn_wb_ddr_out.sel,
wb1_cyc_i => gn_wb_ddr_out.cyc, wb1_cyc_i => gn_wb_ddr_out.cyc,
wb1_stb_i => gn_wb_ddr_out.stb, wb1_stb_i => gn_wb_ddr_out.stb,
......
hdl/syn/dma_test/.gitignore 0 → 100644
View file @ 8fbf7438
*
!.gitignore
!Manifest.py
!*.ucf
!syn_extra_steps.tcl
hdl/syn/dma_test/Manifest.py 0 → 100644
View file @ 8fbf7438
target = "xilinx"
action = "synthesis"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_dma_test.xise"
syn_tool = "ise"
syn_top = "spec_dma_test"
board = "spec"
spec_base_ucf = ['ddr3']
ctrls = ["bank3_32b_32b" ]
files = [ "buildinfo_pkg.vhd" ]
modules = {
"local" : [
"../../top/dma_test", "../../syn/common"
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
syn_post_project_cmd = "$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
hdl/syn/dma_test/syn_extra_steps.tcl 0 → 100644
View file @ 8fbf7438
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
xilinx::project set "Pack I/O Registers into IOBs" "Yes"
xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
#xilinx::project set "Placer Extra Effort Map" "Normal"
#xilinx::project set "Extra Effort (Highest PAR level only)" "Normal"
xilinx::project save
xilinx::project close
hdl/testbench/spec_ddr_dma/Manifest.py → hdl/testbench/dma_test/Manifest.py
View file @ 8fbf7438
...@@ -15,7 +15,6 @@ if locals().get('fetchto', None) is None: ...@@ -15,7 +15,6 @@ if locals().get('fetchto', None) is None:
include_dirs = [ include_dirs = [
fetchto + "/gn4124-core/hdl/sim/gn4124_bfm", fetchto + "/gn4124-core/hdl/sim/gn4124_bfm",
fetchto + "/general-cores/sim/", fetchto + "/general-cores/sim/",
# fetchto + "/general-cores/modules/wishbone/wb_spi/",
fetchto + "/ddr3-sp6-core/hdl/sim/", fetchto + "/ddr3-sp6-core/hdl/sim/",
] ]
...@@ -26,7 +25,7 @@ files = [ ...@@ -26,7 +25,7 @@ files = [
modules = { modules = {
"local" : [ "local" : [
"../../top/full", "../../top/dma_test",
], ],
"git" : [ "git" : [
"https://ohwr.org/project/wr-cores.git", "https://ohwr.org/project/wr-cores.git",
...@@ -42,4 +41,4 @@ try: ...@@ -42,4 +41,4 @@ try:
except: except:
pass pass
ctrls = ["bank3_64b_32b" ] ctrls = ["bank3_32b_32b" ]
hdl/testbench/spec_ddr_dma/main.sv → hdl/testbench/dma_test/main.sv
View file @ 8fbf7438
...@@ -31,21 +31,17 @@ module main; ...@@ -31,21 +31,17 @@ module main;
// 125Mhz // 125Mhz
always #4ns clk_125m_pllref <= ~clk_125m_pllref; always #4ns clk_125m_pllref <= ~clk_125m_pllref;
// 20Mhz
always #25ns clk_20m_vcxo <= ~clk_20m_vcxo;
spec_full spec_dma_test
#( #(
.g_dma_use_pci_clk (0),
.g_SIMULATION(1) .g_SIMULATION(1)
) )
DUT DUT
( (
.button1_n_i (rst_n), .button1_n_i (rst_n),
.clk_20m_vcxo_i (clk_20m_vcxo),
.clk_125m_pllref_p_i (clk_125m_pllref), .clk_125m_pllref_p_i (clk_125m_pllref),
.clk_125m_pllref_n_i (~clk_125m_pllref), .clk_125m_pllref_n_i (~clk_125m_pllref),
.clk_125m_gtp_p_i (clk_125m_pllref),
.clk_125m_gtp_n_i (~clk_125m_pllref),
.gn_rst_n_i (i_gn4124.rst_n), .gn_rst_n_i (i_gn4124.rst_n),
.gn_p2l_clk_n_i (i_gn4124.p2l_clk_n), .gn_p2l_clk_n_i (i_gn4124.p2l_clk_n),
.gn_p2l_clk_p_i (i_gn4124.p2l_clk_p), .gn_p2l_clk_p_i (i_gn4124.p2l_clk_p),
...@@ -117,6 +113,7 @@ module main; ...@@ -117,6 +113,7 @@ module main;
typedef enum bit {RD,WR} dma_dir_t; typedef enum bit {RD,WR} dma_dir_t;
task dma_xfer(input CBusAccessor acc, task dma_xfer(input CBusAccessor acc,
input uint64_t host_addr,
input uint32_t start_addr, input uint32_t start_addr,
input uint32_t length, input uint32_t length,
input dma_dir_t dma_dir, input dma_dir_t dma_dir,
...@@ -130,8 +127,8 @@ module main; ...@@ -130,8 +127,8 @@ module main;
// Setup DMA addresses // Setup DMA addresses
acc.write(`DMA_BASE + 'h08, start_addr); // dma start addr acc.write(`DMA_BASE + 'h08, start_addr); // dma start addr
acc.write(`DMA_BASE + 'h0C, 'h20000000); // host addr low acc.write(`DMA_BASE + 'h0C, host_addr & 'hffffffff); // host addr low
acc.write(`DMA_BASE + 'h10, 'h00000000); // host addr high acc.write(`DMA_BASE + 'h10, host_addr >> 32); // host addr high
acc.write(`DMA_BASE + 'h14, length); // length in bytes acc.write(`DMA_BASE + 'h14, length); // length in bytes
acc.write(`DMA_BASE + 'h18, 'h00000000); // next low acc.write(`DMA_BASE + 'h18, 'h00000000); // next low
acc.write(`DMA_BASE + 'h1C, 'h00000000); // next high acc.write(`DMA_BASE + 'h1C, 'h00000000); // next high
...@@ -171,13 +168,39 @@ module main; ...@@ -171,13 +168,39 @@ module main;
typedef virtual IGN4124PCIMaster vIGN4124PCIMaster; typedef virtual IGN4124PCIMaster vIGN4124PCIMaster;
task dma_read_pattern(vIGN4124PCIMaster i_gn4124);
int i;
uint64_t val, expected;
CBusAccessor acc;
acc = i_gn4124.get_accessor();
acc.set_default_xfer_size(4);
// Read pattern from device memory
dma_xfer(acc, 'h20000000, 'h0, 4 * 'h20, RD);
// Verify pattern
for (i = 'h00; i < 'h20; i++)
begin
expected = i+1;
expected |= (i+1) << 8;
expected |= (i+1) << 16;
expected |= (i+1) << 24;
i_gn4124.host_mem_read(i*4, val);
if (val != expected)
$fatal(1, "<%t> READ-BACK ERROR at host address 0x%x: expected 0x%8x, got 0x%8x",
$realtime, i*4, expected, val);
end
endtask // dma_read_pattern
task dma_test(vIGN4124PCIMaster i_gn4124, task dma_test(vIGN4124PCIMaster i_gn4124,
input uint32_t word_count); input uint32_t word_count);
int i; int i;
uint32_t word_addr; uint32_t word_addr, word_remain, word_ptr;
uint64_t val, expected; uint64_t val, expected, host_addr;
uint64_t data_queue[$]; uint64_t data_queue[$];
CBusAccessor acc; CBusAccessor acc;
...@@ -194,14 +217,33 @@ module main; ...@@ -194,14 +217,33 @@ module main;
data_queue.push_back(val); data_queue.push_back(val);
end end
// Write data to device memory // Write data to device memory
dma_xfer(acc, word_addr * 4, word_count * 4, WR); word_ptr = word_addr;
word_remain = word_count;
host_addr = 'h20000000;
while (word_remain != 0)
begin
if (word_remain > 1024)
begin
dma_xfer(acc, host_addr, word_ptr * 4, 4096, WR);
word_remain -= 1024;
word_ptr += 1024;
host_addr += 4096;
end
else
begin
dma_xfer(acc, host_addr, word_ptr * 4, word_remain * 4, WR);
word_ptr += word_remain;
word_remain = 0;
host_addr = 'h20000000;
end
end
// Clear host memory // Clear host memory
for (i = 0; i < word_count; i++) for (i = 0; i < word_count; i++)
begin begin
i_gn4124.host_mem_write(i*4, 0); i_gn4124.host_mem_write(i*4, 0);
end end
// Read data from device memory // Read data from device memory
dma_xfer(acc, word_addr * 4, word_count * 4, RD); dma_xfer(acc, host_addr, word_addr * 4, word_count * 4, RD);
// Compare against written data // Compare against written data
for (i = 0; i < word_count; i++) for (i = 0; i < word_count; i++)
begin begin
...@@ -229,9 +271,15 @@ module main; ...@@ -229,9 +271,15 @@ module main;
$display ("Simulation START"); $display ("Simulation START");
$display(); $display();
#2us; #10us;
dma_test(vi_gn4124, 'h20); dma_read_pattern(vi_gn4124);
for (i = 2; i < 13; i++)
begin
#1us;
dma_test(vi_gn4124, 2**i);
end
$display(); $display();
$display ("Simulation PASSED"); $display ("Simulation PASSED");
...@@ -241,17 +289,4 @@ module main; ...@@ -241,17 +289,4 @@ module main;
end end
initial begin
// Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE
force DUT.inst_spec_base.gen_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D1.OPMODE_dly = 0;
force DUT.inst_spec_base.gen_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D2.OPMODE_dly = 0;
force DUT.inst_spec_base.gen_wr.cmp_xwrc_board_spec.cmp_board_common.cmp_xwr_core.
WRPC.LM32_CORE.gen_profile_medium_icache.U_Wrapped_LM32.cpu.
multiplier.D3.OPMODE_dly = 0;
end // initial begin
endmodule // main endmodule // main
hdl/testbench/dma_test/wave.do 0 → 100644
View file @ 8fbf7438
This diff is collapsed.
hdl/testbench/spec_ddr_dma/wave.do deleted 100644 → 0
View file @ 90be31a5
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -color Coral /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/rst_n_i
add wave -noupdate -expand -group Command -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_cmd_clk_o
add wave -noupdate -expand -group Command -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_cmd_en_o
add wave -noupdate -expand -group Command -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_cmd_instr_o
add wave -noupdate -expand -group Command -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_cmd_bl_o
add wave -noupdate -expand -group Command -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr_o
add wave -noupdate -expand -group Command -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_cmd_empty_i
add wave -noupdate -expand -group Command -color Gold /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_cmd_full_i
add wave -noupdate -expand -group Write -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_wr_clk_o
add wave -noupdate -expand -group Write -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_wr_en_o
add wave -noupdate -expand -group Write -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_wr_mask_o
add wave -noupdate -expand -group Write -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_wr_data_o
add wave -noupdate -expand -group Write -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_wr_full_i
add wave -noupdate -expand -group Write -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_wr_empty_i
add wave -noupdate -expand -group Write -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_wr_count_i
add wave -noupdate -expand -group Write -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_wr_underrun_i
add wave -noupdate -expand -group Write -color Magenta /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_wr_error_i
add wave -noupdate -expand -group Read -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_rd_clk_o
add wave -noupdate -expand -group Read -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_rd_en_o
add wave -noupdate -expand -group Read -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_rd_data_i
add wave -noupdate -expand -group Read -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_rd_full_i
add wave -noupdate -expand -group Read -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_rd_empty_i
add wave -noupdate -expand -group Read -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_rd_count_i
add wave -noupdate -expand -group Read -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_rd_overflow_i
add wave -noupdate -expand -group Read -color Cyan /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/ddr_rd_error_i
add wave -noupdate -expand -group WB /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/wb_clk_i
add wave -noupdate -expand -group WB /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/wb_sel_i
add wave -noupdate -expand -group WB /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/wb_cyc_i
add wave -noupdate -expand -group WB /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/wb_stb_i
add wave -noupdate -expand -group WB /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/wb_we_i
add wave -noupdate -expand -group WB /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/wb_addr_i
add wave -noupdate -expand -group WB /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/wb_data_i
add wave -noupdate -expand -group WB /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/wb_data_o
add wave -noupdate -expand -group WB /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/wb_ack_o
add wave -noupdate -expand -group WB /main/DUT/inst_spec_base/gen_with_ddr/cmp_ddr_ctrl_bank3/cmp_ddr3_ctrl_wb_1/wb_stall_o
add wave -noupdate -expand -group {P2L DATA} -color {Blue Violet} /main/DUT/inst_spec_base/gen_with_gennum/cmp_gn4124_core/cmp_wrapped_gn4124/p2l_data_i
add wave -noupdate -expand -group {P2L DATA} -color {Blue Violet} /main/DUT/inst_spec_base/gen_with_gennum/cmp_gn4124_core/cmp_wrapped_gn4124/p2l_dframe_i
add wave -noupdate -expand -group {P2L DATA} -color {Blue Violet} /main/DUT/inst_spec_base/gen_with_gennum/cmp_gn4124_core/cmp_wrapped_gn4124/p2l_valid_i
add wave -noupdate -expand -group {L2P DATA} -color {Steel Blue} /main/DUT/inst_spec_base/gen_with_gennum/cmp_gn4124_core/cmp_wrapped_gn4124/l2p_data_o
add wave -noupdate -expand -group {L2P DATA} -color {Steel Blue} /main/DUT/inst_spec_base/gen_with_gennum/cmp_gn4124_core/cmp_wrapped_gn4124/l2p_dframe_o
add wave -noupdate -expand -group {L2P DATA} -color {Steel Blue} /main/DUT/inst_spec_base/gen_with_gennum/cmp_gn4124_core/cmp_wrapped_gn4124/l2p_valid_o
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {11653084600 fs} 0}
quietly wave cursor active 1
configure wave -namecolwidth 350
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 2
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 400000
configure wave -gridperiod 800000
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 fs} {39360300 ps}
hdl/top/dma_test/Manifest.py 0 → 100644
View file @ 8fbf7438
files = ["spec_dma_test.vhd"]
modules = {'local': ["../../rtl"]}
hdl/top/dma_test/spec_dma_test.vhd 0 → 100644
View file @ 8fbf7438
--------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- SPEC
-- https://ohwr.org/projects/spec
--------------------------------------------------------------------------------
--
-- unit name: spec_dma_test
--
-- description: A bitstream for testing DMA with a dummy application that pre-
-- loads the first 32 words (128 bytes) of the DDR with a predefined pattern:
--
-- 0x00: 0x01010101
-- 0x04: 0x02020202
-- ...
-- 0x7c: 0x20202020
--
--------------------------------------------------------------------------------
-- Copyright CERN 2020
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.wishbone_pkg.all;
entity spec_dma_test is
generic (
g_DMA_USE_PCI_CLK : boolean := FALSE;
g_SIMULATION : boolean := FALSE
);
port (
-- Global ports
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
-- From GN4124 Local bus
gn_rst_n_i : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- PCIe to Local [Inbound Data] - RX
gn_p2l_clk_n_i : in std_logic; -- Receiver Source Synchronous Clock-
gn_p2l_clk_p_i : in std_logic; -- Receiver Source Synchronous Clock+
gn_p2l_rdy_o : out std_logic; -- Rx Buffer Full Flag
gn_p2l_dframe_i : in std_logic; -- Receive Frame
gn_p2l_valid_i : in std_logic; -- Receive Data Valid
gn_p2l_data_i : in std_logic_vector(15 downto 0); -- Parallel receive data
-- Inbound Buffer Request/Status
gn_p_wr_req_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
gn_p_wr_rdy_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
gn_rx_error_o : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
gn_l2p_clk_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
gn_l2p_clk_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
gn_l2p_dframe_o : out std_logic; -- Transmit Data Frame
gn_l2p_valid_o : out std_logic; -- Transmit Data Valid
gn_l2p_edb_o : out std_logic; -- Packet termination and discard
gn_l2p_data_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
-- Outbound Buffer Status
gn_l2p_rdy_i : in std_logic; -- Tx Buffer Full Flag
gn_l_wr_rdy_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
gn_p_rd_d_rdy_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
gn_tx_error_i : in std_logic; -- Transmit Error
gn_vc_rdy_i : in std_logic_vector(1 downto 0); -- Channel ready
-- General Purpose Interface
gn_gpio_b : inout std_logic_vector(1 downto 0); -- gn_gpio[0] -> GN4124 GPIO8
-- gn_gpio[1] -> GN4124 GPIO9
-- PCB version
pcbrev_i : in std_logic_vector(3 downto 0);
button1_n_i : in std_logic;
-- I2C to the FMC
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic;
-- FMC presence (there is a pull-up)
fmc0_prsnt_m2c_n_i : in std_logic;
-- DDR3
ddr_a_o : out std_logic_vector(13 downto 0);
ddr_ba_o : out std_logic_vector(2 downto 0);
ddr_cas_n_o : out std_logic;
ddr_ck_n_o : out std_logic;
ddr_ck_p_o : out std_logic;
ddr_cke_o : out std_logic;
ddr_dq_b : inout std_logic_vector(15 downto 0);
ddr_ldm_o : out std_logic;
ddr_ldqs_n_b : inout std_logic;
ddr_ldqs_p_b : inout std_logic;
ddr_odt_o : out std_logic;
ddr_ras_n_o : out std_logic;
ddr_reset_n_o : out std_logic;
ddr_rzq_b : inout std_logic;
ddr_udm_o : out std_logic;
ddr_udqs_n_b : inout std_logic;
ddr_udqs_p_b : inout std_logic;
ddr_we_n_o : out std_logic
);
end spec_dma_test;
architecture arch of spec_dma_test is
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal gn_wb_out : t_wishbone_master_out;
signal gn_wb_in : t_wishbone_master_in;
signal wb_ddr_out : t_wishbone_master_out;
signal wb_ddr_in : t_wishbone_master_in;
type fsm_state_type is (S_IDLE, S_WRITE, S_DONE);
signal fsm_current_state : fsm_state_type;
begin
inst_spec_base : entity work.spec_base_wr
generic map (
g_WITH_VIC => TRUE,
g_WITH_ONEWIRE => FALSE,
g_WITH_SPI => FALSE,
g_WITH_DDR => TRUE,
g_DDR_DATA_SIZE => 32,
g_WITH_WR => FALSE,
g_DMA_USE_PCI_CLK => g_DMA_USE_PCI_CLK,
g_SIMULATION => g_SIMULATION
)
port map (
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
gn_rst_n_i => gn_rst_n_i,
gn_p2l_clk_n_i => gn_p2l_clk_n_i,
gn_p2l_clk_p_i => gn_p2l_clk_p_i,
gn_p2l_rdy_o => gn_p2l_rdy_o,
gn_p2l_dframe_i => gn_p2l_dframe_i,
gn_p2l_valid_i => gn_p2l_valid_i,
gn_p2l_data_i => gn_p2l_data_i,
gn_p_wr_req_i => gn_p_wr_req_i,
gn_p_wr_rdy_o => gn_p_wr_rdy_o,
gn_rx_error_o => gn_rx_error_o,
gn_l2p_clk_n_o => gn_l2p_clk_n_o,
gn_l2p_clk_p_o => gn_l2p_clk_p_o,
gn_l2p_dframe_o => gn_l2p_dframe_o,
gn_l2p_valid_o => gn_l2p_valid_o,
gn_l2p_edb_o => gn_l2p_edb_o,
gn_l2p_data_o => gn_l2p_data_o,
gn_l2p_rdy_i => gn_l2p_rdy_i,
gn_l_wr_rdy_i => gn_l_wr_rdy_i,
gn_p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
gn_tx_error_i => gn_tx_error_i,
gn_vc_rdy_i => gn_vc_rdy_i,
gn_gpio_b => gn_gpio_b,
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
pcbrev_i => pcbrev_i,
button1_n_i => button1_n_i,
ddr_a_o => ddr_a_o,
ddr_ba_o => ddr_ba_o,
ddr_cas_n_o => ddr_cas_n_o,
ddr_ck_n_o => ddr_ck_n_o,
ddr_ck_p_o => ddr_ck_p_o,
ddr_cke_o => ddr_cke_o,
ddr_dq_b => ddr_dq_b,
ddr_ldm_o => ddr_ldm_o,
ddr_ldqs_n_b => ddr_ldqs_n_b,
ddr_ldqs_p_b => ddr_ldqs_p_b,
ddr_odt_o => ddr_odt_o,
ddr_ras_n_o => ddr_ras_n_o,
ddr_reset_n_o => ddr_reset_n_o,
ddr_rzq_b => ddr_rzq_b,
ddr_udm_o => ddr_udm_o,
ddr_udqs_n_b => ddr_udqs_n_b,
ddr_udqs_p_b => ddr_udqs_p_b,
ddr_we_n_o => ddr_we_n_o,
ddr_dma_clk_i => clk_sys_62m5,
ddr_dma_rst_n_i => rst_sys_62m5_n,
ddr_dma_wb_cyc_i => wb_ddr_out.cyc,
ddr_dma_wb_stb_i => wb_ddr_out.stb,
ddr_dma_wb_adr_i => wb_ddr_out.adr,
ddr_dma_wb_sel_i => wb_ddr_out.sel,
ddr_dma_wb_we_i => wb_ddr_out.we,
ddr_dma_wb_dat_i => wb_ddr_out.dat,
ddr_dma_wb_ack_o => wb_ddr_in.ack,
ddr_dma_wb_stall_o => wb_ddr_in.stall,
ddr_dma_wb_dat_o => wb_ddr_in.dat,
clk_62m5_sys_o => clk_sys_62m5,
rst_62m5_sys_n_o => rst_sys_62m5_n,
spi_miso_i => '0',
app_wb_o => gn_wb_out,
app_wb_i => gn_wb_in
);
gn_wb_in <= (ack => '1', err | rty | stall => '0', dat => (others => '0'));
p_fsm : process (clk_sys_62m5) is
variable pattern : unsigned(7 downto 0) := (others => '0');
begin -- process p_fsm
if rising_edge(clk_sys_62m5) then
if rst_sys_62m5_n = '0' then
fsm_current_state <= S_IDLE;
pattern := (others => '0');
wb_ddr_out.adr <= (others => '0');
wb_ddr_out.dat <= (others => '0');
wb_ddr_out.cyc <= '0';
wb_ddr_out.stb <= '0';
else
wb_ddr_out.sel <= "1111";
wb_ddr_out.we <= '1';
case fsm_current_state is
when S_IDLE =>
wb_ddr_out.cyc <= '1';
fsm_current_state <= S_WRITE;
when S_WRITE =>
if wb_ddr_in.stall = '0' then
pattern := pattern + 1;
wb_ddr_out.cyc <= '1';
wb_ddr_out.stb <= '1';
wb_ddr_out.dat <= std_logic_vector(pattern & pattern & pattern & pattern);
wb_ddr_out.adr(7 downto 0) <= std_logic_vector(pattern - 1);
if pattern = 32 then
fsm_current_state <= S_DONE;
end if;
end if;
when S_DONE =>
if wb_ddr_in.stall = '0' then
wb_ddr_out.cyc <= '0';
wb_ddr_out.stb <= '0';
end if;
end case;
end if;
end if;
end process p_fsm;
end architecture arch;
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