Use the standard directory structure.

79d5bdb3 · Tristan Gingold · f08912f0 · f08912f0 · f08912f0 · f08912f0
Commit 79d5bdb3 authored Jul 10, 2019 by Tristan Gingold
18 changed files
--- a/hdl/golden/top/Manifest.py
+++ b/hdl/golden/top/Manifest.py
-files = ["spec_golden.vhd", "spec_devices.vhd", "spec_golden.ucf"]
-modules = {'local': ["../../template"]}
--- a/hdl/golden/top/spec_devices.cheby
+++ b/hdl/golden/top/spec_devices.cheby
-memory-map:
-  name: golden_devices
-  bus: wb-32-be
-  size: 0x400
-  children:
-    - submap:
-       name: metadata
-       description: a ROM containing the carrier metadata
-       size: 0x40
-       interface: sram
-    - reg:
-       address: 0x40
-       name: app_offset
-       description: offset to the application metadata
-       access: ro
-       width: 32
-    - submap:
-        name: therm_id
-        description: Thermometer and unique id
-        size: 0x10
-        interface: wb-32-be
-        x-hdl:
-          busgroup: True
-    - block:
-       name: csr
-       description: carrier and fmc status and control
-       children:
-       - reg:
-          name: resets
-          description: global and application resets
-          access: rw
-          width: 32
-          children:
-           - field:
-              name: global
-              range: 0
-           - field:
-              name: appl
-              range: 1
-       - reg:
-          name: fmc_presence
-          description: presence lines for the fmcs
-          access: ro
-          width: 32
-    - submap:
-        name: fmc_i2c
-        description: i2c controllers to the fmcs
-        address: 0x80
-        size: 0x20
-        interface: wb-32-be
-        x-hdl:
-          busgroup: True
-    - submap:
-        name: flash_spi
-        description: spi controller to the flash
-        address: 0xa0
-        size: 0x20
-        interface: wb-32-be
-        x-hdl:
-          busgroup: True
-    - submap:
-        name: dma
-        description: dma registers for the gennum core
-        address: 0xc0
-        size: 0x40
-        interface: wb-32-be
-        x-hdl:
-          busgroup: True
-    - submap:
-        name: vic
-        description: vector interrupt controller
-        size: 0x100
-        interface: wb-32-be
-        x-hdl:
-          busgroup: True
-    - submap:
-        name: wrc
-        description: white-rabbit core
-        size: 0x100
-        interface: wb-32-be
-        x-hdl:
-          busgroup: True
-    - submap:
-        name: app
-        description: the application
-        size: 0x100
-        interface: wb-32-be
-        x-hdl:
-          busgroup: True
--- a/hdl/golden/top/spec_devices.vhd
+++ b/hdl/golden/top/spec_devices.vhd
--- a/hdl/rtl/Manifest.py
+++ b/hdl/rtl/Manifest.py
+files = ["spec_template.vhd", "spec_template_regs.vhd", "spec_template_wr.vhd"]
--- a/hdl/template/spec_template.vhd
+++ b/hdl/template/spec_template.vhd
--- a/hdl/template/spec_template_regs.cheby
+++ b/hdl/template/spec_template_regs.cheby
--- a/hdl/template/spec_template_regs.vhd
+++ b/hdl/template/spec_template_regs.vhd
--- a/hdl/template_wr/spec_template_wr.vhd
+++ b/hdl/template_wr/spec_template_wr.vhd
--- a/hdl/golden/syn/Manifest.py
+++ b/hdl/golden/syn/Manifest.py
 target = "xilinx"
 action = "synthesis"

-fetchto = "../ip_cores"
+fetchto = "../../ip_cores"

 syn_device = "xc6slx45t"
 syn_grade = "-3"
@@ -10,8 +10,10 @@ syn_project = "spec_golden.xise"
 syn_tool = "ise"
 syn_top = "spec_golden"

-modules = { "local" : "../top",
-            "git" : [ "git://ohwr.org/hdl-core-lib/wr-cores.git::proposed_master",
-            "git://ohwr.org/hdl-core-lib/general-cores.git::proposed_master",
-            "git://ohwr.org/hdl-core-lib/gn4124-core.git::proposed_master" ]
+modules = { 
+  "local" : "../../top/golden",
+  "git" : [ "https://ohwr.org/project/wr-cores.git::proposed_master",
+            "https://ohwr.org/project/general-cores.git::proposed_master",
+            "https://ohwr.org/project/gn4124-core.git::proposed_master" ]
 }
+
--- a/hdl/golden_wr/syn/Manifest.py
+++ b/hdl/golden_wr/syn/Manifest.py
@@ -15,7 +15,7 @@ board = "spec"
 ctrls = ["bank3_64b_32b" ]

 modules = { 
-  "local" : "../top",
+  "local" : "../../top/golden_wr",
  "git" : [ "https://ohwr.org/project/wr-cores.git::proposed_master",
            "https://ohwr.org/project/general-cores.git::proposed_master",
            "https://ohwr.org/project/etherbone-core.git::proposed_master",

--- a/hdl/template/Manifest.py
+++ b/hdl/template/Manifest.py
-files = ["spec_template.vhd", "spec_template_regs.vhd"]
--- a/hdl/template_wr/Manifest.py
+++ b/hdl/template_wr/Manifest.py
-files = ["spec_template_wr.vhd", "../template/spec_template_regs.vhd"]
--- a/hdl/top/golden/Manifest.py
+++ b/hdl/top/golden/Manifest.py
+files = ["spec_golden.vhd", "spec_golden.ucf"]
+modules = {'local': ["../../rtl"]}
--- a/hdl/golden/top/spec_golden.ucf
+++ b/hdl/golden/top/spec_golden.ucf
--- a/hdl/golden/top/spec_golden.vhd
+++ b/hdl/golden/top/spec_golden.vhd
--- a/hdl/golden_wr/top/Manifest.py
+++ b/hdl/golden_wr/top/Manifest.py
 files = ["spec_golden_wr.vhd", "spec_golden_wr.ucf"]
-modules = {'local': ["../../template_wr"]}
+modules = {'local': ["../../rtl"]}
--- a/hdl/golden_wr/top/spec_golden_wr.ucf
+++ b/hdl/golden_wr/top/spec_golden_wr.ucf
--- a/hdl/golden_wr/top/spec_golden_wr.vhd
+++ b/hdl/golden_wr/top/spec_golden_wr.vhd