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Simple PCIe FMC carrier SPEC
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Simple PCIe FMC carrier SPEC
Commits
79c7901f
Commit
79c7901f
authored
Jul 16, 2019
by
Tristan Gingold
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spec template: use buildinfo
parent
1f8f3af7
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2 changed files
with
21 additions
and
26 deletions
+21
-26
spec_template_wr.vhd
hdl/rtl/spec_template_wr.vhd
+11
-20
Manifest.py
hdl/syn/golden_wr/Manifest.py
+10
-6
No files found.
hdl/rtl/spec_template_wr.vhd
View file @
79c7901f
...
...
@@ -43,7 +43,7 @@ use work.gn4124_core_pkg.all;
use
work
.
wr_xilinx_pkg
.
all
;
use
work
.
wr_board_pkg
.
all
;
use
work
.
wr_spec_pkg
.
all
;
use
work
.
synthesis_descriptor
.
all
;
use
work
.
buildinfo_pkg
.
all
;
use
work
.
wr_fabric_pkg
.
all
;
use
work
.
streamers_pkg
.
all
;
...
...
@@ -652,29 +652,20 @@ begin -- architecture top
-- Build information
p_buildinfo
:
process
(
clk_sys_62m5
)
is
constant
toolver
:
string
:
=
f_bits2string
(
c_sdb_synthesis_info
.
syn_tool_version
);
constant
syndate
:
string
:
=
f_bits2string
(
c_sdb_synthesis_info
.
syn_date
);
constant
buildinfo
:
string
:
=
"buildinfo:1"
&
LF
&
"module:"
&
c_sdb_synthesis_info
.
syn_module_name
&
LF
&
"commit:"
&
c_sdb_synthesis_info
.
syn_commit_id
&
LF
&
"syntool:"
&
c_sdb_synthesis_info
.
syn_tool_name
&
LF
&
"toolver:"
&
toolver
(
3
to
toolver
'right
)
&
LF
&
"syndate:"
&
syndate
(
3
to
syndate
'right
)
&
LF
&
"synauth:"
&
c_sdb_synthesis_info
.
syn_username
&
LF
&
NUL
&
NUL
&
NUL
&
NUL
&
NUL
&
NUL
&
NUL
&
NUL
;
variable
addr
:
natural
;
variable
b
:
std_logic_vector
(
7
downto
0
);
begin
if
rising_edge
(
clk_sys_62m5
)
then
addr
:
=
to_integer
(
unsigned
(
buildinfo_addr
))
*
4
;
if
addr
<
buildinfo
'right
-
4
then
buildinfo_data
<=
f_string2svl
(
buildinfo
(
1
+
addr
to
4
+
addr
));
else
buildinfo_data
<=
x"00000000"
;
end
if
;
for
i
in
0
to
3
loop
if
addr
+
i
<
buildinfo
'length
then
b
:
=
std_logic_vector
(
to_unsigned
(
character
'pos
(
buildinfo
(
buildinfo
'left
+
addr
+
i
)),
8
));
else
b
:
=
x"00"
;
end
if
;
buildinfo_data
(
7
+
i
*
8
downto
i
*
8
)
<=
b
;
end
loop
;
end
if
;
end
process
;
...
...
hdl/syn/golden_wr/Manifest.py
View file @
79c7901f
target
=
"xilinx"
action
=
"synthesis"
fetchto
=
"../ip_cores"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if
locals
()
.
get
(
'fetchto'
,
None
)
is
None
:
fetchto
=
"../ip_cores"
syn_device
=
"xc6slx45t"
syn_grade
=
"-3"
...
...
@@ -9,12 +12,11 @@ syn_package = "fgg484"
syn_project
=
"spec_golden_wr.xise"
syn_tool
=
"ise"
syn_top
=
"spec_golden_wr"
syn_properties
=
[
[
"-generics"
,
"dpram=
\"
3
\"
"
]]
board
=
"spec"
ctrls
=
[
"bank3_64b_32b"
]
files
=
[
"
synthesis_descriptor
.vhd"
]
files
=
[
"
buildinfo_pkg
.vhd"
]
modules
=
{
"local"
:
"../../top/golden_wr"
,
...
...
@@ -25,6 +27,8 @@ modules = {
"https://ohwr.org/project/ddr3-sp6-core.git::proposed_master"
]
}
syn_post_project_cmd
=
\
"$(TCL_INTERPRETER) "
+
fetchto
+
"/general-cores/tools/sdb_desc_gen.tcl "
+
\
syn_tool
+
" $(PROJECT_FILE);"
# Do not fail during hdlmake fetch
try
:
exec
(
open
(
fetchto
+
"/general-cores/tools/gen_buildinfo.py"
)
.
read
())
except
:
pass
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