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Simple PCIe FMC carrier SPEC
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Simple PCIe FMC carrier SPEC
Commits
798a6866
Commit
798a6866
authored
Sep 04, 2019
by
Tristan Gingold
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adjust ucf and goldens.
parent
41d53adb
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4 changed files
with
103 additions
and
103 deletions
+103
-103
spec_template_wr.vhd
hdl/rtl/spec_template_wr.vhd
+2
-2
spec_template_common.ucf
hdl/syn/common/spec_template_common.ucf
+2
-2
spec_golden.vhd
hdl/top/golden/spec_golden.vhd
+49
-49
spec_golden_wr.vhd
hdl/top/golden_wr/spec_golden_wr.vhd
+50
-50
No files found.
hdl/rtl/spec_template_wr.vhd
View file @
798a6866
...
...
@@ -163,7 +163,7 @@ entity spec_template_wr is
-- Green LED next to the SFP: indicates if the link is up.
led_link_o
:
out
std_logic
;
button1_
i
:
in
std_logic
:
=
'1'
;
button1_
n_i
:
in
std_logic
:
=
'1'
;
---------------------------------------------------------------------------
-- UART
...
...
@@ -743,7 +743,7 @@ begin -- architecture top
g_RX_STREAMER_PARAMS
=>
g_RX_STREAMER_PARAMS
,
g_FABRIC_IFACE
=>
g_FABRIC_IFACE
)
port
map
(
areset_n_i
=>
button1_i
,
areset_n_i
=>
button1_
n_
i
,
areset_edge_n_i
=>
gn_rst_n_i
,
clk_20m_vcxo_i
=>
clk_20m_vcxo_i
,
clk_125m_pllref_p_i
=>
clk_125m_pllref_p_i
,
...
...
hdl/syn/common/spec_template_common.ucf
View file @
798a6866
...
...
@@ -152,8 +152,8 @@ NET "*/gc_reset_async_in" TIG;
# Declaration of domains
NET "inst_spec_template/clk_
sys_62m5
" TNM_NET = sys_clk;
NET "inst_spec_template/clk_
ref_125m
" TNM_NET = ref_clk;
NET "inst_spec_template/clk_
62m5_sys
" TNM_NET = sys_clk;
NET "inst_spec_template/clk_
125m_ref
" TNM_NET = ref_clk;
NET "*/cmp_gn4124_core/cmp_wrapped_gn4124/sys_clk" TNM_NET = pci_clk;
NET "*/cmp_gn4124_core/cmp_wrapped_gn4124/io_clk" TNM_NET = pci_clk;
...
...
hdl/top/golden/spec_golden.vhd
View file @
798a6866
...
...
@@ -32,38 +32,38 @@ entity spec_golden is
clk_125m_pllref_p_i
:
in
std_logic
;
-- 125 MHz PLL reference
clk_125m_pllref_n_i
:
in
std_logic
;
gn_RST_N
:
in
std_logic
;
-- Reset from GN4124 (RSTOUT18_N)
gn_RST_N
_i
:
in
std_logic
;
-- Reset from GN4124 (RSTOUT18_N)
-- General Purpose Interface
gn_GPIO
:
inout
std_logic_vector
(
1
downto
0
);
-- GPIO[0] -> GN4124 GPIO8
gn_GPIO
_b
:
inout
std_logic_vector
(
1
downto
0
);
-- GPIO[0] -> GN4124 GPIO8
-- GPIO[1] -> GN4124 GPIO9
-- PCIe to Local [Inbound Data] - RX
gn_P2L_RDY
:
out
std_logic
;
-- Rx Buffer Full Flag
gn_P2L_CLK_n
:
in
std_logic
;
-- Receiver Source Synchronous Clock-
gn_P2L_CLK_p
:
in
std_logic
;
-- Receiver Source Synchronous Clock+
gn_P2L_DATA
:
in
std_logic_vector
(
15
downto
0
);
-- Parallel receive data
gn_P2L_DFRAME
:
in
std_logic
;
-- Receive Frame
gn_P2L_VALID
:
in
std_logic
;
-- Receive Data Valid
gn_P2L_RDY
_o
:
out
std_logic
;
-- Rx Buffer Full Flag
gn_P2L_CLK_n
_i
:
in
std_logic
;
-- Receiver Source Synchronous Clock-
gn_P2L_CLK_p
_i
:
in
std_logic
;
-- Receiver Source Synchronous Clock+
gn_P2L_DATA
_i
:
in
std_logic_vector
(
15
downto
0
);
-- Parallel receive data
gn_P2L_DFRAME
_i
:
in
std_logic
;
-- Receive Frame
gn_P2L_VALID
_i
:
in
std_logic
;
-- Receive Data Valid
-- Inbound Buffer Request/Status
gn_P_WR_REQ
:
in
std_logic_vector
(
1
downto
0
);
-- PCIe Write Request
gn_P_WR_RDY
:
out
std_logic_vector
(
1
downto
0
);
-- PCIe Write Ready
gn_RX_ERROR
:
out
std_logic
;
-- Receive Error
gn_P_WR_REQ
_i
:
in
std_logic_vector
(
1
downto
0
);
-- PCIe Write Request
gn_P_WR_RDY
_o
:
out
std_logic_vector
(
1
downto
0
);
-- PCIe Write Ready
gn_RX_ERROR
_o
:
out
std_logic
;
-- Receive Error
-- Local to Parallel [Outbound Data] - TX
gn_L2P_DATA
:
out
std_logic_vector
(
15
downto
0
);
-- Parallel transmit data
gn_L2P_DFRAME
:
out
std_logic
;
-- Transmit Data Frame
gn_L2P_VALID
:
out
std_logic
;
-- Transmit Data Valid
gn_L2P_CLK_n
:
out
std_logic
;
-- Transmitter Source Synchronous Clock-
gn_L2P_CLK_p
:
out
std_logic
;
-- Transmitter Source Synchronous Clock+
gn_L2P_EDB
:
out
std_logic
;
-- Packet termination and discard
gn_L2P_DATA
_o
:
out
std_logic_vector
(
15
downto
0
);
-- Parallel transmit data
gn_L2P_DFRAME
_o
:
out
std_logic
;
-- Transmit Data Frame
gn_L2P_VALID
_o
:
out
std_logic
;
-- Transmit Data Valid
gn_L2P_CLK_n
_o
:
out
std_logic
;
-- Transmitter Source Synchronous Clock-
gn_L2P_CLK_p
_o
:
out
std_logic
;
-- Transmitter Source Synchronous Clock+
gn_L2P_EDB
_o
:
out
std_logic
;
-- Packet termination and discard
-- Outbound Buffer Status
gn_L2P_RDY
:
in
std_logic
;
-- Tx Buffer Full Flag
gn_L_WR_RDY
:
in
std_logic_vector
(
1
downto
0
);
-- Local-to-PCIe Write
gn_P_RD_D_RDY
:
in
std_logic_vector
(
1
downto
0
);
-- PCIe-to-Local Read Response Data Ready
gn_TX_ERROR
:
in
std_logic
;
-- Transmit Error
gn_VC_RDY
:
in
std_logic_vector
(
1
downto
0
);
-- Channel ready
gn_L2P_RDY
_i
:
in
std_logic
;
-- Tx Buffer Full Flag
gn_L_WR_RDY
_i
:
in
std_logic_vector
(
1
downto
0
);
-- Local-to-PCIe Write
gn_P_RD_D_RDY
_i
:
in
std_logic_vector
(
1
downto
0
);
-- PCIe-to-Local Read Response Data Ready
gn_TX_ERROR
_i
:
in
std_logic
;
-- Transmit Error
gn_VC_RDY
_i
:
in
std_logic_vector
(
1
downto
0
);
-- Channel ready
-- PCB version
pcbrev_i
:
in
std_logic_vector
(
3
downto
0
);
...
...
@@ -72,7 +72,7 @@ entity spec_golden is
-- LED_RED : out std_logic;
-- LED_GREEN : out std_logic;
button1_i
:
in
std_logic
;
button1_
n_
i
:
in
std_logic
;
-- I2C to the FMC
fmc0_scl_b
:
inout
std_logic
;
...
...
@@ -97,40 +97,40 @@ architecture rtl of spec_golden is
signal
gn_wb_out
:
t_wishbone_master_out
;
signal
gn_wb_in
:
t_wishbone_master_in
;
begin
inst_template
:
entity
work
.
spec_template_wr
inst_
spec_
template
:
entity
work
.
spec_template_wr
generic
map
(
g_WITH_VIC
=>
True
,
g_WITH_ONEWIRE
=>
True
,
g_WITH_SPI
=>
True
,
g_WITH_DDR
=>
False
,
g_WITH_WR
=>
False
,
g_simulation
=>
0
g_simulation
=>
False
)
port
map
(
clk_125m_pllref_p_i
=>
clk_125m_pllref_p_i
,
clk_125m_pllref_n_i
=>
clk_125m_pllref_n_i
,
gn_rst_n_i
=>
gn_rst_n
,
gn_p2l_clk_n_i
=>
gn_p2l_clk_n
,
gn_p2l_clk_p_i
=>
gn_p2l_clk_p
,
gn_p2l_rdy_o
=>
gn_p2l_rdy
,
gn_p2l_dframe_i
=>
gn_p2l_dframe
,
gn_p2l_valid_i
=>
gn_p2l_valid
,
gn_p2l_data_i
=>
gn_p2l_data
,
gn_p_wr_req_i
=>
gn_p_wr_req
,
gn_p_wr_rdy_o
=>
gn_p_wr_rdy
,
gn_rx_error_o
=>
gn_rx_error
,
gn_l2p_clk_n_o
=>
gn_l2p_clk_n
,
gn_l2p_clk_p_o
=>
gn_l2p_clk_p
,
gn_l2p_dframe_o
=>
gn_l2p_dframe
,
gn_l2p_valid_o
=>
gn_l2p_valid
,
gn_l2p_edb_o
=>
gn_l2p_edb
,
gn_l2p_data_o
=>
gn_l2p_data
,
gn_l2p_rdy_i
=>
gn_l2p_rdy
,
gn_l_wr_rdy_i
=>
gn_l_wr_rdy
,
gn_p_rd_d_rdy_i
=>
gn_p_rd_d_rdy
,
gn_tx_error_i
=>
gn_tx_error
,
gn_vc_rdy_i
=>
gn_vc_rdy
,
gn_gpio_b
=>
gn_gpio
,
gn_rst_n_i
=>
gn_rst_n
_i
,
gn_p2l_clk_n_i
=>
gn_p2l_clk_n
_i
,
gn_p2l_clk_p_i
=>
gn_p2l_clk_p
_i
,
gn_p2l_rdy_o
=>
gn_p2l_rdy
_o
,
gn_p2l_dframe_i
=>
gn_p2l_dframe
_i
,
gn_p2l_valid_i
=>
gn_p2l_valid
_i
,
gn_p2l_data_i
=>
gn_p2l_data
_i
,
gn_p_wr_req_i
=>
gn_p_wr_req
_i
,
gn_p_wr_rdy_o
=>
gn_p_wr_rdy
_o
,
gn_rx_error_o
=>
gn_rx_error
_o
,
gn_l2p_clk_n_o
=>
gn_l2p_clk_n
_o
,
gn_l2p_clk_p_o
=>
gn_l2p_clk_p
_o
,
gn_l2p_dframe_o
=>
gn_l2p_dframe
_o
,
gn_l2p_valid_o
=>
gn_l2p_valid
_o
,
gn_l2p_edb_o
=>
gn_l2p_edb
_o
,
gn_l2p_data_o
=>
gn_l2p_data
_o
,
gn_l2p_rdy_i
=>
gn_l2p_rdy
_i
,
gn_l_wr_rdy_i
=>
gn_l_wr_rdy
_i
,
gn_p_rd_d_rdy_i
=>
gn_p_rd_d_rdy
_i
,
gn_tx_error_i
=>
gn_tx_error
_i
,
gn_vc_rdy_i
=>
gn_vc_rdy
_i
,
gn_gpio_b
=>
gn_gpio
_b
,
fmc0_scl_b
=>
fmc0_scl_b
,
fmc0_sda_b
=>
fmc0_sda_b
,
fmc0_prsnt_m2c_n_i
=>
fmc0_prsnt_m2c_n_i
,
...
...
@@ -151,8 +151,8 @@ begin
ddr_dma_wb_i
.
dat
=>
x"0000_0000_0000_0000"
,
ddr_dma_wb_o
=>
open
,
clk_
sys_62m5
_o
=>
clk_sys_62m5
,
rst_
sys_62m5
_n_o
=>
rst_sys_62m5_n
,
clk_
62m5_sys
_o
=>
clk_sys_62m5
,
rst_
62m5_sys
_n_o
=>
rst_sys_62m5_n
,
-- Everything is handled by the carrier.
app_wb_o
=>
gn_wb_out
,
...
...
hdl/top/golden_wr/spec_golden_wr.vhd
View file @
798a6866
...
...
@@ -33,7 +33,7 @@ entity spec_golden_wr is
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_SIMULATION
:
integer
:
=
0
g_SIMULATION
:
boolean
:
=
False
);
port
(
---------------------------------------------------------------------------
...
...
@@ -47,33 +47,33 @@ entity spec_golden_wr is
-- GN4124 PCIe bridge signals
---------------------------------------------------------------------------
-- From GN4124 Local bus
gn_rst_n
:
in
std_logic
;
-- Reset from GN4124 (RSTOUT18_N)
gn_rst_n
_i
:
in
std_logic
;
-- Reset from GN4124 (RSTOUT18_N)
-- PCIe to Local [Inbound Data] - RX
gn_p2l_clk_n
:
in
std_logic
;
-- Receiver Source Synchronous Clock-
gn_p2l_clk_p
:
in
std_logic
;
-- Receiver Source Synchronous Clock+
gn_p2l_rdy
:
out
std_logic
;
-- Rx Buffer Full Flag
gn_p2l_dframe
:
in
std_logic
;
-- Receive Frame
gn_p2l_valid
:
in
std_logic
;
-- Receive Data Valid
gn_p2l_data
:
in
std_logic_vector
(
15
downto
0
);
-- Parallel receive data
gn_p2l_clk_n
_i
:
in
std_logic
;
-- Receiver Source Synchronous Clock-
gn_p2l_clk_p
_i
:
in
std_logic
;
-- Receiver Source Synchronous Clock+
gn_p2l_rdy
_o
:
out
std_logic
;
-- Rx Buffer Full Flag
gn_p2l_dframe
_i
:
in
std_logic
;
-- Receive Frame
gn_p2l_valid
_i
:
in
std_logic
;
-- Receive Data Valid
gn_p2l_data
_i
:
in
std_logic_vector
(
15
downto
0
);
-- Parallel receive data
-- Inbound Buffer Request/Status
gn_p_wr_req
:
in
std_logic_vector
(
1
downto
0
);
-- PCIe Write Request
gn_p_wr_rdy
:
out
std_logic_vector
(
1
downto
0
);
-- PCIe Write Ready
gn_rx_error
:
out
std_logic
;
-- Receive Error
gn_p_wr_req
_i
:
in
std_logic_vector
(
1
downto
0
);
-- PCIe Write Request
gn_p_wr_rdy
_o
:
out
std_logic_vector
(
1
downto
0
);
-- PCIe Write Ready
gn_rx_error
_o
:
out
std_logic
;
-- Receive Error
-- Local to Parallel [Outbound Data] - TX
gn_l2p_clk_n
:
out
std_logic
;
-- Transmitter Source Synchronous Clock-
gn_l2p_clk_p
:
out
std_logic
;
-- Transmitter Source Synchronous Clock+
gn_l2p_dframe
:
out
std_logic
;
-- Transmit Data Frame
gn_l2p_valid
:
out
std_logic
;
-- Transmit Data Valid
gn_l2p_edb
:
out
std_logic
;
-- Packet termination and discard
gn_l2p_data
:
out
std_logic_vector
(
15
downto
0
);
-- Parallel transmit data
gn_l2p_clk_n
_o
:
out
std_logic
;
-- Transmitter Source Synchronous Clock-
gn_l2p_clk_p
_o
:
out
std_logic
;
-- Transmitter Source Synchronous Clock+
gn_l2p_dframe
_o
:
out
std_logic
;
-- Transmit Data Frame
gn_l2p_valid
_o
:
out
std_logic
;
-- Transmit Data Valid
gn_l2p_edb
_o
:
out
std_logic
;
-- Packet termination and discard
gn_l2p_data
_o
:
out
std_logic_vector
(
15
downto
0
);
-- Parallel transmit data
-- Outbound Buffer Status
gn_l2p_rdy
:
in
std_logic
;
-- Tx Buffer Full Flag
gn_l_wr_rdy
:
in
std_logic_vector
(
1
downto
0
);
-- Local-to-PCIe Write
gn_p_rd_d_rdy
:
in
std_logic_vector
(
1
downto
0
);
-- PCIe-to-Local Read Response Data Ready
gn_tx_error
:
in
std_logic
;
-- Transmit Error
gn_vc_rdy
:
in
std_logic_vector
(
1
downto
0
);
-- Channel ready
gn_l2p_rdy
_i
:
in
std_logic
;
-- Tx Buffer Full Flag
gn_l_wr_rdy
_i
:
in
std_logic_vector
(
1
downto
0
);
-- Local-to-PCIe Write
gn_p_rd_d_rdy
_i
:
in
std_logic_vector
(
1
downto
0
);
-- PCIe-to-Local Read Response Data Ready
gn_tx_error
_i
:
in
std_logic
;
-- Transmit Error
gn_vc_rdy
_i
:
in
std_logic_vector
(
1
downto
0
);
-- Channel ready
-- General Purpose Interface
gn_gpio
:
inout
std_logic_vector
(
1
downto
0
);
-- gn_gpio[0] -> GN4124 GPIO8
gn_gpio
_b
:
inout
std_logic_vector
(
1
downto
0
);
-- gn_gpio[0] -> GN4124 GPIO8
-- gn_gpio[1] -> GN4124 GPIO9
-- I2C interface for accessing FMC EEPROM.
...
...
@@ -111,7 +111,7 @@ entity spec_golden_wr is
-- Green LED next to the SFP: indicates if the link is up.
led_link_o
:
out
std_logic
;
button1_i
:
in
std_logic
;
button1_
n_
i
:
in
std_logic
;
---------------------------------------------------------------------------
-- UART
...
...
@@ -160,7 +160,7 @@ architecture top of spec_golden_wr is
signal
gn_wb_out
:
t_wishbone_master_out
;
signal
gn_wb_in
:
t_wishbone_master_in
;
begin
inst_template
:
entity
work
.
spec_template_wr
inst_
spec_
template
:
entity
work
.
spec_template_wr
generic
map
(
g_WITH_VIC
=>
True
,
g_WITH_ONEWIRE
=>
False
,
...
...
@@ -173,28 +173,28 @@ begin
port
map
(
clk_125m_pllref_p_i
=>
clk_125m_pllref_p_i
,
clk_125m_pllref_n_i
=>
clk_125m_pllref_n_i
,
gn_rst_n_i
=>
gn_rst_n
,
gn_p2l_clk_n_i
=>
gn_p2l_clk_n
,
gn_p2l_clk_p_i
=>
gn_p2l_clk_p
,
gn_p2l_rdy_o
=>
gn_p2l_rdy
,
gn_p2l_dframe_i
=>
gn_p2l_dframe
,
gn_p2l_valid_i
=>
gn_p2l_valid
,
gn_p2l_data_i
=>
gn_p2l_data
,
gn_p_wr_req_i
=>
gn_p_wr_req
,
gn_p_wr_rdy_o
=>
gn_p_wr_rdy
,
gn_rx_error_o
=>
gn_rx_error
,
gn_l2p_clk_n_o
=>
gn_l2p_clk_n
,
gn_l2p_clk_p_o
=>
gn_l2p_clk_p
,
gn_l2p_dframe_o
=>
gn_l2p_dframe
,
gn_l2p_valid_o
=>
gn_l2p_valid
,
gn_l2p_edb_o
=>
gn_l2p_edb
,
gn_l2p_data_o
=>
gn_l2p_data
,
gn_l2p_rdy_i
=>
gn_l2p_rdy
,
gn_l_wr_rdy_i
=>
gn_l_wr_rdy
,
gn_p_rd_d_rdy_i
=>
gn_p_rd_d_rdy
,
gn_tx_error_i
=>
gn_tx_error
,
gn_vc_rdy_i
=>
gn_vc_rdy
,
gn_gpio_b
=>
gn_gpio
,
gn_rst_n_i
=>
gn_rst_n
_i
,
gn_p2l_clk_n_i
=>
gn_p2l_clk_n
_i
,
gn_p2l_clk_p_i
=>
gn_p2l_clk_p
_i
,
gn_p2l_rdy_o
=>
gn_p2l_rdy
_o
,
gn_p2l_dframe_i
=>
gn_p2l_dframe
_i
,
gn_p2l_valid_i
=>
gn_p2l_valid
_i
,
gn_p2l_data_i
=>
gn_p2l_data
_i
,
gn_p_wr_req_i
=>
gn_p_wr_req
_i
,
gn_p_wr_rdy_o
=>
gn_p_wr_rdy
_o
,
gn_rx_error_o
=>
gn_rx_error
_o
,
gn_l2p_clk_n_o
=>
gn_l2p_clk_n
_o
,
gn_l2p_clk_p_o
=>
gn_l2p_clk_p
_o
,
gn_l2p_dframe_o
=>
gn_l2p_dframe
_o
,
gn_l2p_valid_o
=>
gn_l2p_valid
_o
,
gn_l2p_edb_o
=>
gn_l2p_edb
_o
,
gn_l2p_data_o
=>
gn_l2p_data
_o
,
gn_l2p_rdy_i
=>
gn_l2p_rdy
_i
,
gn_l_wr_rdy_i
=>
gn_l_wr_rdy
_i
,
gn_p_rd_d_rdy_i
=>
gn_p_rd_d_rdy
_i
,
gn_tx_error_i
=>
gn_tx_error
_i
,
gn_vc_rdy_i
=>
gn_vc_rdy
_i
,
gn_gpio_b
=>
gn_gpio
_b
,
fmc0_scl_b
=>
fmc0_scl_b
,
fmc0_sda_b
=>
fmc0_sda_b
,
fmc0_prsnt_m2c_n_i
=>
fmc0_prsnt_m2c_n_i
,
...
...
@@ -206,7 +206,7 @@ begin
pcbrev_i
=>
pcbrev_i
,
led_act_o
=>
led_act_o
,
led_link_o
=>
led_link_o
,
button1_
i
=>
button1
_i
,
button1_
n_i
=>
button1_n
_i
,
uart_rxd_i
=>
uart_rxd_i
,
uart_txd_o
=>
uart_txd_o
,
clk_20m_vcxo_i
=>
clk_20m_vcxo_i
,
...
...
@@ -238,8 +238,8 @@ begin
ddr_dma_wb_i
.
dat
=>
x"0000_0000_0000_0000"
,
ddr_dma_wb_o
=>
open
,
clk_
sys_62m5
_o
=>
clk_sys_62m5
,
rst_
sys_62m5
_n_o
=>
rst_sys_62m5_n
,
clk_
62m5_sys
_o
=>
clk_sys_62m5
,
rst_
62m5_sys
_n_o
=>
rst_sys_62m5_n
,
-- Everything is handled by the carrier.
app_wb_o
=>
gn_wb_out
,
...
...
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