Commit 6bf976cb authored by Federico Vaga's avatar Federico Vaga

sw|doc: better explaination about the 4KiB write split

Signed-off-by: Federico Vaga's avatarFederico Vaga <>
parent 3164b2c7
......@@ -294,7 +294,9 @@ You can get the maximum transfer size by calling ``dma_get_max_seg_size()``.::
.. warning::
The HDL DMA engine implementation does not support very well
``DMA_MEM_TO_DEV`` transfers. To overcome some bugs users must
split their transfers in 4KiB chunks.
The GN4124 chip has a 4KiB payload. When doing a ``DMA_DEV_TO_MEM``
the HDL DMA engine splits transfers in 4KiB chunks, but for
``DMA_MEM_TO_DEV`` transfers the split should happen in the
driver: it does not happen. The DMA engine implementation
supports ``DMA_MEM_TO_DEV`` manly for testing purposes; to avoid
complications in the driver the 4KiB split is left to users.
......@@ -172,10 +172,8 @@ static int spec_fpga_dbg_dma_transfer(struct spec_fpga_dbg_dma *dbgdma,
dir, count, offset);
* Compensate HDL limitation.
* The gennum core has no DMA size limits for reading. Unfortunatelly,
* the implementation is not symmetric and on write the limit is
* 4096 Bytes
* The GN4124 chip has a 4KiB payload. For DMA_DEV_TO_MEM this is
* handled by the HDL core. For DMA_MEM_TO_DEV, the split is done here.
if (dir == DMA_DEV_TO_MEM)
max_segment = dma_get_max_seg_size(dbgdma->dchan->device->dev);
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