Add wbgen files for test_ddr design.

4635a19a · Matthieu Cattin · d744bbba · 4635a19a
Commit 4635a19a authored Feb 24, 2011 by Matthieu Cattin
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gpio_regs.wb hdl/test_ddr/wb_gen/gpio_regs.wb +68 -0

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--- a/hdl/test_ddr/wb_gen/gpio_regs.wb
+++ b/hdl/test_ddr/wb_gen/gpio_regs.wb
+peripheral {
+  name = "Control and status registers";
+  description = "Wishbone slave to test CSR wishbone on SPEC board";
+  hdl_entity = "gpio_regs";
+
+  prefix = "gpio";
+
+  reg {
+    name = "Status";
+    prefix = "stat";
+    field {
+      name = "Status register";
+      type = SLV;
+      size = 32;
+      access_bus = READ_ONLY;
+      access_dev = WRITE_ONLY;
+    };
+  };
+
+  reg {
+    name = "Control_1";
+    prefix = "ctrl_1";
+    field {
+      name = "Control register 1";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+  };
+
+  reg {
+    name = "Control_2";
+    prefix = "ctrl_2";
+    field {
+      name = "Control register 2";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+  };
+
+  reg {
+    name = "Control_3";
+    prefix = "ctrl_3";
+    field {
+      name = "Control register 3";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+  };
+
+  reg {
+    name = "LED_control";
+    prefix = "led_ctrl";
+    field {
+      name = "Register for front panel LED control";
+      type = SLV;
+      size = 32;
+      access_bus = READ_WRITE;
+      access_dev = READ_ONLY;
+    };
+  };
+
+};