Merge remote-tracking branch 'ohwr/bugfix/v2.1.3' into develop

3acff59a · Federico Vaga · f24b4863 · a2ae2c94 · 461b30fe · 3acff59a
Commit 3acff59a authored Nov 16, 2020 by Federico Vaga
4 changed files
--- a/gn4124-core @ 461b30fe
+++ b/gn4124-core @ 461b30fe
-Subproject commit c629364388453726da401909b5154306ab4e6930
+Subproject commit 461b30fe1f5e4e0c99f2265cdbf5843d31e31a4b
--- a/hdl/rtl/spec_base_wr.vhd
+++ b/hdl/rtl/spec_base_wr.vhd
@@ -604,7 +604,7 @@ begin  -- architecture top
          metadata_data <= x"53504543";
        when x"2" =>
          -- Version (0xVVMMmmmm VV: version, MM: major, mmmm: minor)
-          metadata_data <= x"02010001";
+          metadata_data <= x"02010003";
        when x"3" =>
          -- BOM
          metadata_data <= x"fffe0000";
@@ -668,8 +668,15 @@ begin  -- architecture top
  rst_gbl_n <= rst_62m5_sys_n and (not csr_rst_gbl);

  -- reset for DDR including soft reset.
-  -- This is treated as async and will be re-synced by the DDR controller
+  -- Add a FF to ease timing.
+  process(clk_333m_ddr, rst_333m_ddr_n, csr_rst_gbl)
+  begin
+    if rst_333m_ddr_n = '0' or csr_rst_gbl = '1' then
+      ddr_rst <= '1';
+    elsif rising_edge (clk_333m_ddr) then
      ddr_rst <= not rst_333m_ddr_n or csr_rst_gbl;
+    end if;
+  end process;

  rst_csr_app_n <= not (csr_rst_gbl or csr_rst_app);


--- a/hdl/syn/common/spec_base_common.ucf
+++ b/hdl/syn/common/spec_base_common.ucf
@@ -157,25 +157,12 @@ NET "inst_spec_base/clk_125m_ref"              TNM_NET = ref_clk;
 NET "*/gen_with_gennum.cmp_gn4124_core/cmp_wrapped_gn4124/sys_clk" TNM_NET = pci_clk;
 NET "*/gen_with_gennum.cmp_gn4124_core/cmp_wrapped_gn4124/io_clk"  TNM_NET = pci_clk;

-TIMEGRP "sys_grp" = "sys_clk" "ref_clk";
+# Note: sys and ref are always related

-TIMEGRP "sys_sync_ffs"  = "sync_ffs" EXCEPT "sys_grp";
-TIMEGRP "pci_sync_ffs"  = "sync_ffs" EXCEPT "pci_clk";
+# sys <-> pci
+TIMESPEC TS_sys_to_pci = FROM sys_clk TO pci_clk 5 ns DATAPATHONLY;
+TIMESPEC TS_pci_to_sys = FROM pci_clk TO sys_clk 5 ns DATAPATHONLY;

-# Exceptions for crossings via gc_sync_ffs
-
-NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs";
-
-TIMESPEC TS_sys_sync_ffs  = FROM sys_grp TO "sys_sync_ffs" TIG;
-TIMESPEC TS_pci_sync_ffs  = FROM pci_clk TO "pci_sync_ffs" TIG;
-
-# Exceptions for crossings via gc_sync_register
-
-NET "*/gc_sync_register_in[*]" TNM = FFS "sync_reg";
-
-TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_grp";
-TIMEGRP "pci_sync_reg" = "sync_reg" EXCEPT "pci_clk";
-
-TIMESPEC TS_ref_sync_reg = FROM ref_clk TO "sys_sync_reg"  8ns  DATAPATHONLY;
-TIMESPEC TS_sys_sync_reg = FROM sys_clk TO "sys_sync_reg"  16ns DATAPATHONLY;
-TIMESPEC TS_pci_sync_reg = FROM pci_clk TO "pci_sync_reg"  5ns  DATAPATHONLY;
+# ref <-> pci
+TIMESPEC TS_ref_to_pci = FROM ref_clk TO pci_clk 5 ns DATAPATHONLY;
+TIMESPEC TS_pci_to_ref = FROM pci_clk TO ref_clk 5 ns DATAPATHONLY;
--- a/hdl/syn/common/spec_base_ddr3.ucf
+++ b/hdl/syn/common/spec_base_ddr3.ucf
@@ -98,6 +98,16 @@ NET "inst_spec_base/clk_333m_ddr" TNM_NET = ddr_clk;
 NET "inst_spec_base/*cmp_ddr_ctrl_bank3/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_clk;
 NET "inst_spec_base/*cmp_ddr_ctrl_bank3/*/memc3_mcb_raw_wrapper_inst/ioi_drp_clk"        TNM_NET = ddr_clk;

+# Note: ref, sys and ddr are always related
+
+# ddr <-> pci
+TIMESPEC TS_ddr_to_pci = FROM ddr_clk TO pci_clk 3 ns DATAPATHONLY;
+TIMESPEC TS_pci_to_ddr = FROM pci_clk TO ddr_clk 3 ns DATAPATHONLY;
+
+# ddr <-> sys
+TIMESPEC TS_ddr_to_sys = FROM ddr_clk TO sys_clk 3 ns DATAPATHONLY;
+TIMESPEC TS_sys_to_ddr = FROM sys_clk TO ddr_clk 3 ns DATAPATHONLY;
+
 # DDR does not use any sync modules

 #TIMEGRP "ddr_sync_ffs"  = "sync_ffs" EXCEPT "ddr_clk";
@@ -109,20 +119,3 @@ NET "inst_spec_base/*cmp_ddr_ctrl_bank3/*/memc3_mcb_raw_wrapper_inst/ioi_drp_clk
 #TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr_sync_reg" 3ns DATAPATHONLY;

 #TIMESPEC TS_ddr_sync_word = FROM sync_word TO ddr_clk  9ns DATAPATHONLY;
-
-#---------------------------------------
-# DMA
-#---------------------------------------
-
-NET "inst_spec_base/gen_with_gennum.cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma.cmp_dma_controller/dma_async_*" TNM = FFS "dma_ffs";
-
-TIMESPEC TS_dma_async_ffs = FROM dma_ffs TO pci_clk  15ns  DATAPATHONLY;
-
-# Exceptions for crossings via gc_sync_word_* (3x multicycle)
-
-NET "*/gc_sync_word_data[*]" TNM = FFS "sync_word";
-
-TIMESPEC TS_sys_sync_word = FROM sync_word TO sys_clk 48ns DATAPATHONLY;
-TIMESPEC TS_ref_sync_word = FROM sync_word TO ref_clk 24ns DATAPATHONLY;
-# no gc_sync_word used in GN4124
-#TIMESPEC TS_pci_sync_word = FROM sync_word TO pci_clk 15ns DATAPATHONLY;