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Simple PCIe FMC carrier SPEC
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Simple PCIe FMC carrier SPEC
Commits
3acff59a
Commit
3acff59a
authored
Nov 16, 2020
by
Federico Vaga
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Merge remote-tracking branch 'ohwr/bugfix/v2.1.3' into develop
parents
f24b4863
a2ae2c94
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4 changed files
with
28 additions
and
41 deletions
+28
-41
gn4124-core
hdl/ip_cores/gn4124-core
+1
-1
spec_base_wr.vhd
hdl/rtl/spec_base_wr.vhd
+10
-3
spec_base_common.ucf
hdl/syn/common/spec_base_common.ucf
+7
-20
spec_base_ddr3.ucf
hdl/syn/common/spec_base_ddr3.ucf
+10
-17
No files found.
gn4124-core
@
461b30fe
Subproject commit
c629364388453726da401909b5154306ab4e6930
Subproject commit
461b30fe1f5e4e0c99f2265cdbf5843d31e31a4b
hdl/rtl/spec_base_wr.vhd
View file @
3acff59a
...
@@ -604,7 +604,7 @@ begin -- architecture top
...
@@ -604,7 +604,7 @@ begin -- architecture top
metadata_data
<=
x"53504543"
;
metadata_data
<=
x"53504543"
;
when
x"2"
=>
when
x"2"
=>
-- Version (0xVVMMmmmm VV: version, MM: major, mmmm: minor)
-- Version (0xVVMMmmmm VV: version, MM: major, mmmm: minor)
metadata_data
<=
x"0201000
1
"
;
metadata_data
<=
x"0201000
3
"
;
when
x"3"
=>
when
x"3"
=>
-- BOM
-- BOM
metadata_data
<=
x"fffe0000"
;
metadata_data
<=
x"fffe0000"
;
...
@@ -668,8 +668,15 @@ begin -- architecture top
...
@@ -668,8 +668,15 @@ begin -- architecture top
rst_gbl_n
<=
rst_62m5_sys_n
and
(
not
csr_rst_gbl
);
rst_gbl_n
<=
rst_62m5_sys_n
and
(
not
csr_rst_gbl
);
-- reset for DDR including soft reset.
-- reset for DDR including soft reset.
-- This is treated as async and will be re-synced by the DDR controller
-- Add a FF to ease timing.
ddr_rst
<=
not
rst_333m_ddr_n
or
csr_rst_gbl
;
process
(
clk_333m_ddr
,
rst_333m_ddr_n
,
csr_rst_gbl
)
begin
if
rst_333m_ddr_n
=
'0'
or
csr_rst_gbl
=
'1'
then
ddr_rst
<=
'1'
;
elsif
rising_edge
(
clk_333m_ddr
)
then
ddr_rst
<=
not
rst_333m_ddr_n
or
csr_rst_gbl
;
end
if
;
end
process
;
rst_csr_app_n
<=
not
(
csr_rst_gbl
or
csr_rst_app
);
rst_csr_app_n
<=
not
(
csr_rst_gbl
or
csr_rst_app
);
...
...
hdl/syn/common/spec_base_common.ucf
View file @
3acff59a
...
@@ -157,25 +157,12 @@ NET "inst_spec_base/clk_125m_ref" TNM_NET = ref_clk;
...
@@ -157,25 +157,12 @@ NET "inst_spec_base/clk_125m_ref" TNM_NET = ref_clk;
NET "*/gen_with_gennum.cmp_gn4124_core/cmp_wrapped_gn4124/sys_clk" TNM_NET = pci_clk;
NET "*/gen_with_gennum.cmp_gn4124_core/cmp_wrapped_gn4124/sys_clk" TNM_NET = pci_clk;
NET "*/gen_with_gennum.cmp_gn4124_core/cmp_wrapped_gn4124/io_clk" TNM_NET = pci_clk;
NET "*/gen_with_gennum.cmp_gn4124_core/cmp_wrapped_gn4124/io_clk" TNM_NET = pci_clk;
TIMEGRP "sys_grp" = "sys_clk" "ref_clk";
# Note: sys and ref are always related
TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "sys_grp";
# sys <-> pci
TIMEGRP "pci_sync_ffs" = "sync_ffs" EXCEPT "pci_clk";
TIMESPEC TS_sys_to_pci = FROM sys_clk TO pci_clk 5 ns DATAPATHONLY;
TIMESPEC TS_pci_to_sys = FROM pci_clk TO sys_clk 5 ns DATAPATHONLY;
# Exceptions for crossings via gc_sync_ffs
# ref <-> pci
TIMESPEC TS_ref_to_pci = FROM ref_clk TO pci_clk 5 ns DATAPATHONLY;
NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs";
TIMESPEC TS_pci_to_ref = FROM pci_clk TO ref_clk 5 ns DATAPATHONLY;
TIMESPEC TS_sys_sync_ffs = FROM sys_grp TO "sys_sync_ffs" TIG;
TIMESPEC TS_pci_sync_ffs = FROM pci_clk TO "pci_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register
NET "*/gc_sync_register_in[*]" TNM = FFS "sync_reg";
TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_grp";
TIMEGRP "pci_sync_reg" = "sync_reg" EXCEPT "pci_clk";
TIMESPEC TS_ref_sync_reg = FROM ref_clk TO "sys_sync_reg" 8ns DATAPATHONLY;
TIMESPEC TS_sys_sync_reg = FROM sys_clk TO "sys_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_pci_sync_reg = FROM pci_clk TO "pci_sync_reg" 5ns DATAPATHONLY;
hdl/syn/common/spec_base_ddr3.ucf
View file @
3acff59a
...
@@ -98,6 +98,16 @@ NET "inst_spec_base/clk_333m_ddr" TNM_NET = ddr_clk;
...
@@ -98,6 +98,16 @@ NET "inst_spec_base/clk_333m_ddr" TNM_NET = ddr_clk;
NET "inst_spec_base/*cmp_ddr_ctrl_bank3/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_clk;
NET "inst_spec_base/*cmp_ddr_ctrl_bank3/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_clk;
NET "inst_spec_base/*cmp_ddr_ctrl_bank3/*/memc3_mcb_raw_wrapper_inst/ioi_drp_clk" TNM_NET = ddr_clk;
NET "inst_spec_base/*cmp_ddr_ctrl_bank3/*/memc3_mcb_raw_wrapper_inst/ioi_drp_clk" TNM_NET = ddr_clk;
# Note: ref, sys and ddr are always related
# ddr <-> pci
TIMESPEC TS_ddr_to_pci = FROM ddr_clk TO pci_clk 3 ns DATAPATHONLY;
TIMESPEC TS_pci_to_ddr = FROM pci_clk TO ddr_clk 3 ns DATAPATHONLY;
# ddr <-> sys
TIMESPEC TS_ddr_to_sys = FROM ddr_clk TO sys_clk 3 ns DATAPATHONLY;
TIMESPEC TS_sys_to_ddr = FROM sys_clk TO ddr_clk 3 ns DATAPATHONLY;
# DDR does not use any sync modules
# DDR does not use any sync modules
#TIMEGRP "ddr_sync_ffs" = "sync_ffs" EXCEPT "ddr_clk";
#TIMEGRP "ddr_sync_ffs" = "sync_ffs" EXCEPT "ddr_clk";
...
@@ -109,20 +119,3 @@ NET "inst_spec_base/*cmp_ddr_ctrl_bank3/*/memc3_mcb_raw_wrapper_inst/ioi_drp_clk
...
@@ -109,20 +119,3 @@ NET "inst_spec_base/*cmp_ddr_ctrl_bank3/*/memc3_mcb_raw_wrapper_inst/ioi_drp_clk
#TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr_sync_reg" 3ns DATAPATHONLY;
#TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr_sync_reg" 3ns DATAPATHONLY;
#TIMESPEC TS_ddr_sync_word = FROM sync_word TO ddr_clk 9ns DATAPATHONLY;
#TIMESPEC TS_ddr_sync_word = FROM sync_word TO ddr_clk 9ns DATAPATHONLY;
#---------------------------------------
# DMA
#---------------------------------------
NET "inst_spec_base/gen_with_gennum.cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma.cmp_dma_controller/dma_async_*" TNM = FFS "dma_ffs";
TIMESPEC TS_dma_async_ffs = FROM dma_ffs TO pci_clk 15ns DATAPATHONLY;
# Exceptions for crossings via gc_sync_word_* (3x multicycle)
NET "*/gc_sync_word_data[*]" TNM = FFS "sync_word";
TIMESPEC TS_sys_sync_word = FROM sync_word TO sys_clk 48ns DATAPATHONLY;
TIMESPEC TS_ref_sync_word = FROM sync_word TO ref_clk 24ns DATAPATHONLY;
# no gc_sync_word used in GN4124
#TIMESPEC TS_pci_sync_word = FROM sync_word TO pci_clk 15ns DATAPATHONLY;
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