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Simple PCIe FMC carrier SPEC
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Simple PCIe FMC carrier SPEC
Commits
386bdfe6
Commit
386bdfe6
authored
Mar 10, 2020
by
Federico Vaga
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Merge remote-tracking branch 'ohwr/develop' into develop
parents
23ec1586
266a209c
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3 changed files
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3 additions
and
4 deletions
+3
-4
general-cores
hdl/ip_cores/general-cores
+1
-1
spec_base_wr.vhd
hdl/rtl/spec_base_wr.vhd
+2
-2
spec_base_ddr3.ucf
hdl/syn/common/spec_base_ddr3.ucf
+0
-1
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general-cores
@
56d855fc
Subproject commit
be61ce73a43d0231e8edc2f12133b918e3d1c9e4
Subproject commit
56d855fc3d97c43e6f21ad669ecfda90971f0982
hdl/rtl/spec_base_wr.vhd
View file @
386bdfe6
...
...
@@ -1027,8 +1027,8 @@ begin -- architecture top
g_RST_ACT_LOW
=>
0
,
-- active high reset (simpler internal logic)
g_BANK_PORT_SELECT
=>
get_ddr3_bank_port_select
,
g_MEMCLK_PERIOD
=>
3000
,
g_SIMULATION
=>
boolean
'image
(
g_SIMULATION
),
g_CALIB_SOFT_IP
=>
"TRUE"
,
g_SIMULATION
=>
to_upper
(
boolean
'image
(
g_SIMULATION
)
),
g_CALIB_SOFT_IP
=>
to_upper
(
boolean
'image
(
not
g_SIMULATION
))
,
g_P0_MASK_SIZE
=>
g_DDR_DATA_SIZE
/
8
,
g_P0_DATA_PORT_SIZE
=>
g_DDR_DATA_SIZE
,
g_P0_BYTE_ADDR_WIDTH
=>
30
,
...
...
hdl/syn/common/spec_base_ddr3.ucf
View file @
386bdfe6
...
...
@@ -84,7 +84,6 @@ NET "ddr_udqs_n_b" IN_TERM = NONE;
NET "inst_spec_base/*cmp_ddr_ctrl_bank?/*/c?_pll_lock" TIG;
NET "inst_spec_base/*cmp_ddr_ctrl_bank?/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "inst_spec_base/*cmp_ddr_ctrl_bank?/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
#NET "inst_base/*cmp_ddr_ctrl_bank?/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
# Ignore async reset to DDR controller
NET "inst_spec_base/ddr_rst" TPTHRU = ddr_rst;
...
...
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