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Simple PCIe FMC carrier SPEC
Commit 37f1748a authored by Federico Vaga's avatar Federico Vaga
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Merge remote-tracking branch 'origin/proposed_master' into develop

parents cd150b30 7ebae5ae
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Manifest.py
View file @ 37f1748a
modules = { "local" : [ "hdl/rtl" ] } modules = { "local" : [ "hdl/rtl" ] }
if action == "synthesis":
modules["local"].append("hdl/syn/common")
hdl/rtl/Manifest.py
View file @ 37f1748a
files = ["spec_template.vhd", "spec_template_regs.vhd", "spec_template_wr.vhd"] files = ["spec_template_regs.vhd", "spec_template_wr.vhd"]
hdl/rtl/spec_template.vhd deleted 100644 → 0
View file @ cd150b30
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hdl/rtl/spec_template_wr.vhd
View file @ 37f1748a
...@@ -453,7 +453,7 @@ begin -- architecture top ...@@ -453,7 +453,7 @@ begin -- architecture top
-- Interrupt interface -- Interrupt interface
-- Note: the dma_irq are synchronized with the wb_master_clk clock -- Note: the dma_irq are synchronized with the wb_master_clk clock
-- inside the gn4124 core. -- inside the gn4124 core.
dma_irq_o => irqs(3 downto 2), dma_irq_o => irqs(2),
-- Note: this is a simple assignment. -- Note: this is a simple assignment.
irq_p_i => irq_master, irq_p_i => irq_master,
irq_p_o => gn_gpio_b(0), irq_p_o => gn_gpio_b(0),
...@@ -481,67 +481,22 @@ begin -- architecture top ...@@ -481,67 +481,22 @@ begin -- architecture top
); );
-- Mini-crossbar from gennum to carrier and application bus. -- Mini-crossbar from gennum to carrier and application bus.
carrier_app_xb: process (clk_sys_62m5) inst_split: entity work.xwb_split
is generic map (
type t_ca_state is (S_IDLE, S_APP, S_CARRIER); g_mask => x"ffff_e000"
variable ca_state : t_ca_state; )
variable can_stall : std_logic; port map (
constant c_IDLE_WB_MASTER_IN : t_wishbone_master_in := clk_sys_i => clk_sys_62m5,
(ack => '0', err => '0', rty => '0', stall => '0', dat => c_DUMMY_WB_DATA); rst_n_i => rst_sys_62m5_n,
begin slave_i => gn_wb_out,
if rising_edge(clk_sys_62m5) then slave_o => gn_wb_in,
if rst_sys_62m5_n = '0' then master_i (0) => carrier_wb_out,
ca_state := S_IDLE; master_i (1) => app_wb_i,
gn_wb_in <= c_IDLE_WB_MASTER_IN; master_o (0) => carrier_wb_in,
app_wb_o <= c_DUMMY_WB_MASTER_OUT; master_o (1) => app_wb_o
carrier_wb_in <= c_DUMMY_WB_MASTER_OUT; );
else
case ca_state is inst_devs: entity work.spec_template_regs
when S_IDLE =>
gn_wb_in <= c_IDLE_WB_MASTER_IN;
app_wb_o <= c_DUMMY_WB_MASTER_OUT;
carrier_wb_in <= c_DUMMY_WB_MASTER_OUT;
if gn_wb_out.cyc = '1'
and gn_wb_out.stb = '1'
then
-- New transaction.
-- Stall so that there is no new requests from the master.
gn_wb_in.stall <= '1';
can_stall := '1';
if gn_wb_out.adr (31 downto 13) = (31 downto 13 => '0') then
ca_state := S_CARRIER;
-- Pass to carrier
carrier_wb_in <= gn_wb_out;
else
ca_state := S_APP;
app_wb_o <= gn_wb_out;
end if;
end if;
when S_CARRIER =>
-- Pass from carrier.
-- Maintain stb as long as the carrier stalls.
carrier_wb_in.stb <= carrier_wb_out.stall and can_stall;
can_stall := can_stall and carrier_wb_out.stall;
gn_wb_in <= carrier_wb_out;
gn_wb_in.stall <= '1';
if carrier_wb_out.ack = '1' then
ca_state := S_IDLE;
end if;
when S_APP =>
-- Pass from application
app_wb_o.stb <= app_wb_i.stall and can_stall;
can_stall := can_stall and app_wb_i.stall;
gn_wb_in <= app_wb_i;
gn_wb_in.stall <= '1';
if app_wb_i.ack = '1' or app_wb_i.err = '1' then
ca_state := S_IDLE;
end if;
end case;
end if;
end if;
end process carrier_app_xb;
i_devs: entity work.spec_template_regs
port map ( port map (
rst_n_i => rst_sys_62m5_n, rst_n_i => rst_sys_62m5_n,
clk_i => clk_sys_62m5, clk_i => clk_sys_62m5,
...@@ -642,11 +597,11 @@ begin -- architecture top ...@@ -642,11 +597,11 @@ begin -- architecture top
if g_WITH_WR then if g_WITH_WR then
metadata_data(3) <= '1'; metadata_data(3) <= '1';
end if; end if;
-- Buildinfo
metadata_data(4) <= '1';
if g_WITH_DDR then if g_WITH_DDR then
metadata_data(4) <= '1'; metadata_data(5) <= '1';
end if; end if;
-- Buildinfo
metadata_data(5) <= '1';
when others => when others =>
metadata_data <= x"00000000"; metadata_data <= x"00000000";
end case; end case;
...@@ -683,7 +638,7 @@ begin -- architecture top ...@@ -683,7 +638,7 @@ begin -- architecture top
rst_sys_62m5_n_o <= rst_sys_62m5_n and rst_csr_app_n; rst_sys_62m5_n_o <= rst_sys_62m5_n and rst_csr_app_n;
clk_sys_62m5_o <= clk_sys_62m5; clk_sys_62m5_o <= clk_sys_62m5;
i_rst_csr_app_sync : gc_sync_ffs inst_rst_csr_app_sync : gc_sync_ffs
port map ( port map (
clk_i => clk_ref_125m, clk_i => clk_ref_125m,
rst_n_i => '1', rst_n_i => '1',
...@@ -693,7 +648,7 @@ begin -- architecture top ...@@ -693,7 +648,7 @@ begin -- architecture top
rst_ref_125m_n_o <= rst_ref_125m_n and rst_csr_app_sync_n; rst_ref_125m_n_o <= rst_ref_125m_n and rst_csr_app_sync_n;
clk_ref_125m_o <= clk_ref_125m; clk_ref_125m_o <= clk_ref_125m;
i_i2c: entity work.xwb_i2c_master inst_i2c: entity work.xwb_i2c_master
generic map ( generic map (
g_interface_mode => CLASSIC, g_interface_mode => CLASSIC,
g_address_granularity => BYTE, g_address_granularity => BYTE,
...@@ -723,11 +678,13 @@ begin -- architecture top ...@@ -723,11 +678,13 @@ begin -- architecture top
irqs(irq_user_i'range) <= irq_user_i; irqs(irq_user_i'range) <= irq_user_i;
end generate gen_user_irq; end generate gen_user_irq;
g_vic: if g_with_vic generate gen_vic: if g_with_vic generate
i_vic: entity work.xwb_vic inst_vic: entity work.xwb_vic
generic map ( generic map (
g_address_granularity => BYTE, g_address_granularity => BYTE,
g_num_interrupts => num_interrupts g_num_interrupts => num_interrupts,
g_FIXED_POLARITY => True,
g_POLARITY => '1'
) )
port map ( port map (
clk_sys_i => clk_sys_62m5, clk_sys_i => clk_sys_62m5,
...@@ -739,11 +696,12 @@ begin -- architecture top ...@@ -739,11 +696,12 @@ begin -- architecture top
); );
end generate; end generate;
g_no_vic: if not g_with_vic generate gen_no_vic: if not g_with_vic generate
vic_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => x"00000000"); vic_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => x"00000000");
irq_master <= '0'; irq_master <= '0';
end generate; end generate;
irqs(3) <= '0';
irqs(4) <= '0'; irqs(4) <= '0';
irqs(5) <= '0'; irqs(5) <= '0';
...@@ -751,7 +709,7 @@ begin -- architecture top ...@@ -751,7 +709,7 @@ begin -- architecture top
-- The WR PTP core board package (WB Slave + WB Master #2 (Etherbone)) -- The WR PTP core board package (WB Slave + WB Master #2 (Etherbone))
----------------------------------------------------------------------------- -----------------------------------------------------------------------------
g_wr: if g_WITH_WR generate gen_wr: if g_WITH_WR generate
-- OneWire -- OneWire
signal onewire_data : std_logic; signal onewire_data : std_logic;
signal onewire_oe : std_logic; signal onewire_oe : std_logic;
...@@ -886,7 +844,7 @@ begin -- architecture top ...@@ -886,7 +844,7 @@ begin -- architecture top
irqs(1) <= '0'; irqs(1) <= '0';
end generate; end generate;
g_no_wr: if not g_WITH_WR generate gen_no_wr: if not g_WITH_WR generate
signal clk_125m_pllref : std_logic; signal clk_125m_pllref : std_logic;
signal pllout_clk_fb_pllref : std_logic; signal pllout_clk_fb_pllref : std_logic;
signal pllout_clk_62m5 : std_logic; signal pllout_clk_62m5 : std_logic;
...@@ -975,8 +933,8 @@ begin -- architecture top ...@@ -975,8 +933,8 @@ begin -- architecture top
wrc_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => x"00000000"); wrc_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => x"00000000");
end generate; end generate;
g_onewire: if g_WITH_ONEWIRE and not g_WITH_WR generate gen_onewire: if g_WITH_ONEWIRE and not g_WITH_WR generate
i_onewire: entity work.xwb_ds182x_readout inst_onewire: entity work.xwb_ds182x_readout
generic map ( generic map (
g_CLOCK_FREQ_KHZ => 62_500, g_CLOCK_FREQ_KHZ => 62_500,
g_USE_INTERNAL_PPS => True) g_USE_INTERNAL_PPS => True)
...@@ -992,13 +950,13 @@ begin -- architecture top ...@@ -992,13 +950,13 @@ begin -- architecture top
); );
end generate; end generate;
g_no_onewire: if not g_WITH_ONEWIRE and not g_WITH_WR generate gen_no_onewire: if not g_WITH_ONEWIRE and not g_WITH_WR generate
therm_id_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => x"00000000"); therm_id_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => x"00000000");
onewire_b <= 'Z'; onewire_b <= 'Z';
end generate; end generate;
g_spi: if g_WITH_SPI and not g_WITH_WR generate gen_spi: if g_WITH_SPI and not g_WITH_WR generate
i_spi: entity work.xwb_spi inst_spi: entity work.xwb_spi
generic map ( generic map (
g_interface_mode => CLASSIC, g_interface_mode => CLASSIC,
g_address_granularity => BYTE, g_address_granularity => BYTE,
...@@ -1020,7 +978,7 @@ begin -- architecture top ...@@ -1020,7 +978,7 @@ begin -- architecture top
); );
end generate; end generate;
g_no_spi: if not g_WITH_SPI and not g_WITH_WR generate gen_no_spi: if not g_WITH_SPI and not g_WITH_WR generate
flash_spi_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => x"00000000"); flash_spi_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => x"00000000");
end generate; end generate;
......
hdl/syn/common/Manifest.py 0 → 100644
View file @ 37f1748a
files = ["spec_template_common.ucf"]
ucf_dict = {'wr': "spec_template_wr.ucf",
'onewire': "spec_template_onewire.ucf",
'spi': "spec_template_spi.ucf",
'ddr3': "spec_template_ddr3.ucf"}
for p in spec_template_ucf:
f = ucf_dict.get(p, None)
assert f is not None, "unknown name {} in 'spec_template_ucf'".format(p)
files.append(f)
hdl/syn/common/spec_template_common.ucf 0 → 100644
View file @ 37f1748a
#===============================================================================
# IO Constraints
#===============================================================================
#----------------------------------------
# Clocks
#----------------------------------------
NET "clk_125m_pllref_n_i" LOC = F10;
NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_pllref_p_i" LOC = G9;
NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# GN4124 PCIe bridge signals
#----------------------------------------
NET "gn_rst_n_i" LOC = N20;
NET "gn_p2l_clk_n_i" LOC = M19;
NET "gn_p2l_clk_p_i" LOC = M20;
NET "gn_p2l_rdy_o" LOC = J16;
NET "gn_p2l_dframe_i" LOC = J22;
NET "gn_p2l_valid_i" LOC = L19;
NET "gn_p2l_data_i[0]" LOC = K20;
NET "gn_p2l_data_i[1]" LOC = H22;
NET "gn_p2l_data_i[2]" LOC = H21;
NET "gn_p2l_data_i[3]" LOC = L17;
NET "gn_p2l_data_i[4]" LOC = K17;
NET "gn_p2l_data_i[5]" LOC = G22;
NET "gn_p2l_data_i[6]" LOC = G20;
NET "gn_p2l_data_i[7]" LOC = K18;
NET "gn_p2l_data_i[8]" LOC = K19;
NET "gn_p2l_data_i[9]" LOC = H20;
NET "gn_p2l_data_i[10]" LOC = J19;
NET "gn_p2l_data_i[11]" LOC = E22;
NET "gn_p2l_data_i[12]" LOC = E20;
NET "gn_p2l_data_i[13]" LOC = F22;
NET "gn_p2l_data_i[14]" LOC = F21;
NET "gn_p2l_data_i[15]" LOC = H19;
NET "gn_p_wr_req_i[0]" LOC = M22;
NET "gn_p_wr_req_i[1]" LOC = M21;
NET "gn_p_wr_rdy_o[0]" LOC = L15;
NET "gn_p_wr_rdy_o[1]" LOC = K16;
NET "gn_rx_error_o" LOC = J17;
NET "gn_l2p_clk_n_o" LOC = K22;
NET "gn_l2p_clk_p_o" LOC = K21;
NET "gn_l2p_dframe_o" LOC = U22;
NET "gn_l2p_valid_o" LOC = T18;
NET "gn_l2p_edb_o" LOC = U20;
NET "gn_l2p_data_o[0]" LOC = P16;
NET "gn_l2p_data_o[1]" LOC = P21;
NET "gn_l2p_data_o[2]" LOC = P18;
NET "gn_l2p_data_o[3]" LOC = T20;
NET "gn_l2p_data_o[4]" LOC = V21;
NET "gn_l2p_data_o[5]" LOC = V19;
NET "gn_l2p_data_o[6]" LOC = W22;
NET "gn_l2p_data_o[7]" LOC = Y22;
NET "gn_l2p_data_o[8]" LOC = P22;
NET "gn_l2p_data_o[9]" LOC = R22;
NET "gn_l2p_data_o[10]" LOC = T21;
NET "gn_l2p_data_o[11]" LOC = T19;
NET "gn_l2p_data_o[12]" LOC = V22;
NET "gn_l2p_data_o[13]" LOC = V20;
NET "gn_l2p_data_o[14]" LOC = W20;
NET "gn_l2p_data_o[15]" LOC = Y21;
NET "gn_l2p_rdy_i" LOC = U19;
NET "gn_l_wr_rdy_i[0]" LOC = R20;
NET "gn_l_wr_rdy_i[1]" LOC = T22;
NET "gn_p_rd_d_rdy_i[0]" LOC = N16;
NET "gn_p_rd_d_rdy_i[1]" LOC = P19;
NET "gn_tx_error_i" LOC = M17;
NET "gn_vc_rdy_i[0]" LOC = B21;
NET "gn_vc_rdy_i[1]" LOC = B22;
NET "gn_gpio_b[0]" LOC = U16; # GPIO8
NET "gn_gpio_b[1]" LOC = AB19; # GPIO9
NET "gn_rst_n_i" IOSTANDARD = "LVCMOS18";
NET "gn_p2l_clk_n_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_p2l_clk_p_i" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_p2l_rdy_o" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_dframe_i" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_valid_i" IOSTANDARD = "SSTL18_I";
NET "gn_p2l_data_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_req_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_p_wr_rdy_o[*]" IOSTANDARD = "SSTL18_I";
NET "gn_rx_error_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_clk_n_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_l2p_clk_p_o" IOSTANDARD = "DIFF_SSTL18_I";
NET "gn_l2p_dframe_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_valid_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_edb_o" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_data_o[*]" IOSTANDARD = "SSTL18_I";
NET "gn_l2p_rdy_i" IOSTANDARD = "SSTL18_I";
NET "gn_l_wr_rdy_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_p_rd_d_rdy_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_tx_error_i" IOSTANDARD = "SSTL18_I";
NET "gn_vc_rdy_i[*]" IOSTANDARD = "SSTL18_I";
NET "gn_gpio_b[*]" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# Misc
#----------------------------------------
NET "button1_n_i" LOC = C22;
NET "button1_n_i" IOSTANDARD = "LVCMOS18";
NET "pcbrev_i[0]" LOC = P5;
NET "pcbrev_i[1]" LOC = P4;
NET "pcbrev_i[2]" LOC = AA2;
NET "pcbrev_i[3]" LOC = AA1;
NET "pcbrev_i[*]" IOSTANDARD = "LVCMOS15";
#----------------------------------------
# FMC slot management
#----------------------------------------
NET "fmc0_prsnt_m2c_n_i" LOC = AB14;
NET "fmc0_scl_b" LOC = F7;
NET "fmc0_sda_b" LOC = F8;
NET "fmc0_prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
NET "fmc0_scl_b" IOSTANDARD = "LVCMOS25";
NET "fmc0_sda_b" IOSTANDARD = "LVCMOS25";
NET "pcbrev_i*" TIG;
NET "fmc0_prsnt_m2c_n_i" TIG;
#===============================================================================
# Timing Constraints
#===============================================================================
#----------------------------------------
# Clocks
#----------------------------------------
NET "gn_p2l_clk_p_i" TNM_NET = "gn_p2l_clk";
NET "gn_p2l_clk_n_i" TNM_NET = "gn_p2l_clk";
TIMESPEC TS_gn_p2l_clk = PERIOD "gn_p2l_clk" 5 ns HIGH 50%;
NET "clk_125m_pllref_p_i" TNM_NET = "clk_125m_pllref";
NET "clk_125m_pllref_n_i" TNM_NET = "clk_125m_pllref";
TIMESPEC TS_clk_125m_pllref = PERIOD "clk_125m_pllref" 8 ns HIGH 50%;
#----------------------------------------
# Asynchronous resets
#----------------------------------------
NET "gn_rst_n_i" TIG;
# Ignore async reset inputs to reset synchronisers
NET "*/gc_reset_async_in" TIG;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
# Declaration of domains
NET "inst_spec_template/clk_sys_62m5" TNM_NET = sys_clk;
NET "inst_spec_template/clk_ref_125m" TNM_NET = ref_clk;
NET "*/cmp_gn4124_core/cmp_wrapped_gn4124/sys_clk" TNM_NET = pci_clk;
NET "*/cmp_gn4124_core/cmp_wrapped_gn4124/io_clk" TNM_NET = pci_clk;
TIMEGRP "sys_grp" = "sys_clk" "ref_clk";
TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "sys_grp";
TIMEGRP "pci_sync_ffs" = "sync_ffs" EXCEPT "pci_clk";
# Exceptions for crossings via gc_sync_ffs
NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs";
TIMESPEC TS_sys_sync_ffs = FROM sys_grp TO "sys_sync_ffs" TIG;
TIMESPEC TS_pci_sync_ffs = FROM pci_clk TO "pci_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register
NET "*/gc_sync_register_in[*]" TNM = FFS "sync_reg";
TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_grp";
TIMEGRP "pci_sync_reg" = "sync_reg" EXCEPT "pci_clk";
TIMESPEC TS_ref_sync_reg = FROM ref_clk TO "sys_sync_reg" 8ns DATAPATHONLY;
TIMESPEC TS_sys_sync_reg = FROM sys_clk TO "sys_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_pci_sync_reg = FROM pci_clk TO "pci_sync_reg" 5ns DATAPATHONLY;
# Exceptions for crossings via gc_sync_word_* (3x multicycle)
NET "*/gc_sync_word_data[*]" TNM = FFS "sync_word";
TIMESPEC TS_sys_sync_word = FROM sync_word TO sys_clk 48ns DATAPATHONLY;
TIMESPEC TS_ref_sync_word = FROM sync_word TO ref_clk 24ns DATAPATHONLY;
# no gc_sync_word used in GN4124
#TIMESPEC TS_pci_sync_word = FROM sync_word TO pci_clk 15ns DATAPATHONLY;
hdl/syn/common/spec_template_ddr3.ucf 0 → 100644
View file @ 37f1748a
## DDR-3
NET "ddr_rzq_b" LOC = K7;
NET "ddr_we_n_o" LOC = H2;
NET "ddr_udqs_p_b" LOC = V2;
NET "ddr_udqs_n_b" LOC = V1;
NET "ddr_udm_o" LOC = P3;
NET "ddr_reset_n_o" LOC = E3;
NET "ddr_ras_n_o" LOC = M5;
NET "ddr_odt_o" LOC = L6;
NET "ddr_ldqs_p_b" LOC = N3;
NET "ddr_ldqs_n_b" LOC = N1;
NET "ddr_ldm_o" LOC = N4;
NET "ddr_cke_o" LOC = F2;
NET "ddr_ck_p_o" LOC = K4;
NET "ddr_ck_n_o" LOC = K3;
NET "ddr_cas_n_o" LOC = M4;
NET "ddr_dq_b[15]" LOC = Y1;
NET "ddr_dq_b[14]" LOC = Y2;
NET "ddr_dq_b[13]" LOC = W1;
NET "ddr_dq_b[12]" LOC = W3;
NET "ddr_dq_b[11]" LOC = U1;
NET "ddr_dq_b[10]" LOC = U3;
NET "ddr_dq_b[9]" LOC = T1;
NET "ddr_dq_b[8]" LOC = T2;
NET "ddr_dq_b[7]" LOC = M1;
NET "ddr_dq_b[6]" LOC = M2;
NET "ddr_dq_b[5]" LOC = L1;
NET "ddr_dq_b[4]" LOC = L3;
NET "ddr_dq_b[3]" LOC = P1;
NET "ddr_dq_b[2]" LOC = P2;
NET "ddr_dq_b[1]" LOC = R1;
NET "ddr_dq_b[0]" LOC = R3;
NET "ddr_ba_o[2]" LOC = H1;
NET "ddr_ba_o[1]" LOC = J1;
NET "ddr_ba_o[0]" LOC = J3;
NET "ddr_a_o[13]" LOC = J6;
NET "ddr_a_o[12]" LOC = F1;
NET "ddr_a_o[11]" LOC = E1;
NET "ddr_a_o[10]" LOC = J4;
NET "ddr_a_o[9]" LOC = G1;
NET "ddr_a_o[8]" LOC = G3;
NET "ddr_a_o[7]" LOC = K6;
NET "ddr_a_o[6]" LOC = L4;
NET "ddr_a_o[5]" LOC = M3;
NET "ddr_a_o[4]" LOC = H3;
NET "ddr_a_o[3]" LOC = M6;
NET "ddr_a_o[2]" LOC = K5;
NET "ddr_a_o[1]" LOC = K1;
NET "ddr_a_o[0]" LOC = K2;
# DDR IO standards and terminations
NET "ddr_udqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_udqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ldqs_p_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ldqs_n_b" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ck_p_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_ck_n_o" IOSTANDARD = "DIFF_SSTL15_II";
NET "ddr_rzq_b" IOSTANDARD = "SSTL15_II";
NET "ddr_we_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_udm_o" IOSTANDARD = "SSTL15_II";
NET "ddr_reset_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_ras_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_odt_o" IOSTANDARD = "SSTL15_II";
NET "ddr_ldm_o" IOSTANDARD = "SSTL15_II";
NET "ddr_cke_o" IOSTANDARD = "SSTL15_II";
NET "ddr_cas_n_o" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_ba_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_a_o[*]" IOSTANDARD = "SSTL15_II";
NET "ddr_dq_b[*]" IN_TERM = NONE;
NET "ddr_ldqs_p_b" IN_TERM = NONE;
NET "ddr_ldqs_n_b" IN_TERM = NONE;
NET "ddr_udqs_p_b" IN_TERM = NONE;
NET "ddr_udqs_n_b" IN_TERM = NONE;
#----------------------------------------
# Xilinx MCB tweaks
#----------------------------------------
# These are suggested by the Xilinx-generated MCB.
# More info in the UCF file found in the "user_design/par" of the generated core.
NET "inst_spec_template/*cmp_ddr_ctrl_bank?/*/c?_pll_lock" TIG;
NET "inst_spec_template/*cmp_ddr_ctrl_bank?/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "inst_spec_template/*cmp_ddr_ctrl_bank?/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
#NET "inst_template/*cmp_ddr_ctrl_bank?/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
# Ignore async reset to DDR controller
NET "inst_spec_template/ddr_rst" TPTHRU = ddr_rst;
TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
NET "inst_spec_template/clk_ddr_333m" TNM_NET = ddr_clk;
NET "inst_spec_template/*cmp_ddr_ctrl_bank3/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_clk;
NET "inst_spec_template/*cmp_ddr_ctrl_bank3/*/memc3_mcb_raw_wrapper_inst/ioi_drp_clk" TNM_NET = ddr_clk;
# DDR does not use any sync modules
#TIMEGRP "ddr_sync_ffs" = "sync_ffs" EXCEPT "ddr_clk";
#TIMESPEC TS_ddr_sync_ffs = FROM ddr_clk TO "ddr_sync_ffs" TIG;
#TIMEGRP "ddr_sync_reg" = "sync_reg" EXCEPT "ddr_clk";
#TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr_sync_reg" 3ns DATAPATHONLY;
#TIMESPEC TS_ddr_sync_word = FROM sync_word TO ddr_clk 9ns DATAPATHONLY;
hdl/syn/common/spec_template_onewire.ucf 0 → 100644
View file @ 37f1748a
###########################################################################
## Onewire interface -> thermometer
###########################################################################
NET "onewire_b" LOC = D4;
NET "onewire_b" IOSTANDARD = "LVCMOS25";
hdl/syn/common/spec_template_spi.ucf 0 → 100644
View file @ 37f1748a
###########################################################################
## Flash memory SPI interface
###########################################################################
NET "spi_ncs_o" LOC = AA3;
NET "spi_ncs_o" IOSTANDARD = "LVCMOS25";
NET "spi_sclk_o" LOC = Y20;
NET "spi_sclk_o" IOSTANDARD = "LVCMOS25";
NET "spi_mosi_o" LOC = AB20;
NET "spi_mosi_o" IOSTANDARD = "LVCMOS25";
NET "spi_miso_i" LOC = AA20;
NET "spi_miso_i" IOSTANDARD = "LVCMOS25";
hdl/syn/common/spec_template_wr.ucf 0 → 100644
View file @ 37f1748a
#===============================================================================
# IO Location Constraints
#===============================================================================
#----------------------------------------
# Clock and reset inputs
#----------------------------------------
NET "clk_20m_vcxo_i" LOC = H12;
NET "clk_20m_vcxo_i" IOSTANDARD = "LVCMOS25";
NET "clk_125m_gtp_n_i" LOC = D11;
NET "clk_125m_gtp_n_i" IOSTANDARD = "LVDS_25";
NET "clk_125m_gtp_p_i" LOC = C11;
NET "clk_125m_gtp_p_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# DAC interfaces (for VCXO)
#----------------------------------------
NET "plldac_sclk_o" LOC = A4;
NET "plldac_sclk_o" IOSTANDARD = "LVCMOS25";
NET "plldac_din_o" LOC = C4;
NET "plldac_din_o" IOSTANDARD = "LVCMOS25";
NET "pll25dac_cs_n_o" LOC = A3;
NET "pll25dac_cs_n_o" IOSTANDARD = "LVCMOS25";
NET "pll20dac_cs_n_o" LOC = B3;
NET "pll20dac_cs_n_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# SFP slot
#----------------------------------------
NET "sfp_txp_o" LOC= B16;
NET "sfp_txn_o" LOC= A16;
NET "sfp_rxp_i" LOC= D15;
NET "sfp_rxn_i" LOC= C15;
NET "sfp_mod_def0_i" LOC = G15;
NET "sfp_mod_def0_i" IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def1_b" LOC = C17;
NET "sfp_mod_def1_b" IOSTANDARD = "LVCMOS25";
NET "sfp_mod_def2_b" LOC = G16;
NET "sfp_mod_def2_b" IOSTANDARD = "LVCMOS25";
NET "sfp_rate_select_o" LOC = H14;
NET "sfp_rate_select_o" IOSTANDARD = "LVCMOS25";
NET "sfp_tx_fault_i" LOC = B18;
NET "sfp_tx_fault_i" IOSTANDARD = "LVCMOS25";
NET "sfp_tx_disable_o" LOC = F17;
NET "sfp_tx_disable_o" IOSTANDARD = "LVCMOS25";
NET "sfp_los_i" LOC = D18;
NET "sfp_los_i" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# UART
#----------------------------------------
NET "uart_rxd_i" LOC= A2;
NET "uart_rxd_i" IOSTANDARD="LVCMOS25";
NET "uart_txd_o" LOC= B2;
NET "uart_txd_o" IOSTANDARD="LVCMOS25";
#----------------------------------------
# SFP LEDs
#----------------------------------------
NET "led_act_o" LOC = D5;
NET "led_act_o" IOSTANDARD = "LVCMOS25";
NET "led_link_o" LOC = E5;
NET "led_link_o" IOSTANDARD = "LVCMOS25";
#===============================================================================
# Timing constraints and exceptions
#===============================================================================
NET "clk_125m_gtp_p_i" TNM_NET = "clk_125m_gtp";
NET "clk_125m_gtp_n_i" TNM_NET = "clk_125m_gtp";
TIMESPEC TS_clk_125m_gtp = PERIOD "clk_125m_gtp" 8 ns HIGH 50%;
NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo";
TIMESPEC TS_clk_20m_vcxo = PERIOD "clk_20m_vcxo" 50 ns HIGH 50%;
NET "inst_spec_template/gen_wr.cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int[1]" TNM_NET = wrc_gtp_clk;
TIMESPEC TS_wrc_gtp_clk = PERIOD "wrc_gtp_clk" 8 ns HIGH 50%;
#-------------------------------------------------------------
# Constrain the phase between input and sampling clock in DMTD
#-------------------------------------------------------------
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_ref_dmtds*/clk_in" TNM = skew_limit;
TIMESPEC TS_dmtd_skew = FROM "skew_limit" TO "FFS" 1.25 ns DATAPATHONLY;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
# Declaration of domains
NET "*cmp_xwrc_board_spec/clk_pll_dmtd" TNM_NET = clk_dmtd;
NET "*cmp_xwrc_board_spec/phy8_to_wrc_rx_clk" TNM_NET = phy_clk;
TIMEGRP "dmtd_sync_ffs" = "sync_ffs" EXCEPT "clk_dmtd";
TIMEGRP "phy_sync_ffs" = "sync_ffs" EXCEPT "phy_clk";
TIMESPEC TS_dmtd_sync_ffs = FROM clk_dmtd TO "dmtd_sync_ffs" TIG;
TIMESPEC TS_phy_sync_ffs = FROM phy_clk TO "phy_sync_ffs" TIG;
TIMEGRP "dmtd_sync_reg" = "sync_reg" EXCEPT "clk_dmtd";
TIMEGRP "phy_sync_reg" = "sync_reg" EXCEPT "phy_clk";
# no gc_sync_reg for DMTD
#TIMESPEC TS_dmtd_sync_reg = FROM clk_dmtd TO "dmtd_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_phy_sync_reg = FROM phy_clk TO "phy_sync_reg" 8ns DATAPATHONLY;
# no gc_sync_word for DMTD or PHY
#TIMESPEC TS_dmtd_sync_word = FROM sync_word TO clk_dmtd 48ns DATAPATHONLY;
#TIMESPEC TS_phy_sync_word = FROM sync_word TO phy_clk 24ns DATAPATHONLY;
hdl/syn/golden_wr/Manifest.py
View file @ 37f1748a
...@@ -13,6 +13,7 @@ syn_project = "spec_golden_wr.xise" ...@@ -13,6 +13,7 @@ syn_project = "spec_golden_wr.xise"
syn_tool = "ise" syn_tool = "ise"
syn_top = "spec_golden_wr" syn_top = "spec_golden_wr"
spec_template_ucf = ['wr', 'onewire', 'spi']
board = "spec" board = "spec"
ctrls = ["bank3_64b_32b" ] ctrls = ["bank3_64b_32b" ]
...@@ -20,7 +21,7 @@ files = [ "buildinfo_pkg.vhd" ] ...@@ -20,7 +21,7 @@ files = [ "buildinfo_pkg.vhd" ]
modules = { modules = {
"local" : [ "local" : [
"../../top/golden_wr", "../../top/golden_wr", "../../syn/common"
], ],
"git" : [ "git" : [
"https://ohwr.org/project/wr-cores.git", "https://ohwr.org/project/wr-cores.git",
......
hdl/top/golden_wr/Manifest.py
View file @ 37f1748a
files = ["spec_golden_wr.vhd", "spec_golden_wr.ucf"] files = ["spec_golden_wr.vhd"]
modules = {'local': ["../../rtl"]} modules = {'local': ["../../rtl"]}
hdl/top/golden_wr/spec_golden_wr.ucf
View file @ 37f1748a
...@@ -264,8 +264,8 @@ TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%; ...@@ -264,8 +264,8 @@ TIMESPEC TS_clk_125m_gtp_n_i = PERIOD "clk_125m_gtp_n_i" 8 ns HIGH 50%;
# refclock is 62.5MHz and we don't use g_divide_input_by_2. # refclock is 62.5MHz and we don't use g_divide_input_by_2.
#PIN "WRC_PLATFORM/cmp_pllrefclk_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE; #PIN "WRC_PLATFORM/cmp_pllrefclk_bufg.O" CLOCK_DEDICATED_ROUTE = FALSE;
#Created by Constraints Editor (xc6slx45t-fgg484-3) - 2017/02/20 #Created by Constraints Editor (xc6slx45t-fgg484-3) - 2017/02/20
NET "inst_template/g_wr.cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = inst_template/g_wr.cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>; NET "inst_template/gen_wr.cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = inst_template/gen_wr.cmp_xwrc_board_spec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>;
TIMESPEC TS_cmp_xwrc_board_spec_cmp_xwrc_platform_gen_phy_spartan6_cmp_gtp_ch1_gtp_clkout_int_1_ = PERIOD "inst_template/cmp_xwrc_board_spec/g_wr.cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%; TIMESPEC TS_cmp_xwrc_board_spec_cmp_xwrc_platform_gen_phy_spartan6_cmp_gtp_ch1_gtp_clkout_int_1_ = PERIOD "inst_template/cmp_xwrc_board_spec/gen_wr.cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" 8 ns HIGH 50%;
# PIN "cmp_clk_dmtd_buf.O" CLOCK_DEDICATED_ROUTE = FALSE; # PIN "cmp_clk_dmtd_buf.O" CLOCK_DEDICATED_ROUTE = FALSE;
##Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/08/07 ##Created by Constraints Editor (xc6slx45t-fgg484-3) - 2012/08/07
INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit; INST "*/U_SOFTPLL/U_Wrapped_Softpll/gen_feedback_dmtds*/clk_in" TNM = skew_limit;
......
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