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Simple PCIe FMC carrier SPEC
Commit 2a176b30 authored by Tristan Gingold's avatar Tristan Gingold
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spec template: minor rework.

parent d9da5213
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hdl/rtl/spec_template_wr.vhd
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...@@ -484,7 +484,7 @@ begin -- architecture top ...@@ -484,7 +484,7 @@ begin -- architecture top
variable ca_state : t_ca_state; variable ca_state : t_ca_state;
variable can_stall : std_logic; variable can_stall : std_logic;
constant c_IDLE_WB_MASTER_IN : t_wishbone_master_in := constant c_IDLE_WB_MASTER_IN : t_wishbone_master_in :=
('0', '0', '0', '0', c_DUMMY_WB_DATA); (ack => '0', err => '0', rty => '0', stall => '0', dat => c_DUMMY_WB_DATA);
begin begin
if rising_edge(clk_sys_62m5) then if rising_edge(clk_sys_62m5) then
if rst_sys_62m5_n = '0' then if rst_sys_62m5_n = '0' then
......
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